JPH01144944U

JPH01144944U -

Info

Publication number: JPH01144944U
Application number: JP3968588U
Authority: JP
Priority date: 1988-03-28
Filing date: 1988-03-28
Publication date: 1989-10-05

Description

[Brief explanation of the drawing]

第１図はこの考案のブロツク図、第２図〜第５
図は実施例を示し、第２図は共有メモリアクセス
装置のブロツク回路図、第３図は各種信号のタイ
ムチヤート、第４図はデータの処理過程を示した
図、第５図は演算モードテーブルを示した図、第
６図、第７図は従来例を示し、第６図は従来の共
有メモリアクセス装置のブロツク回路図、第７図
、第８図はこの共有メモリアクセス装置の動作を
説明する為の図である。２１……ＣＰＵ、２２……ＣＲＴコントローラ
、２３……共有メモリ、２４……ライトデータラ
ツチ回路、２５……リードデータバツフア回路、
２６……演算回路、２７……ライトデータバツフ
ア回路、２８……リードデータラツチ回路、２９
……アクセスコントロール回路。 Figure 1 is a block diagram of this invention, Figures 2 to 5
The figure shows an embodiment, Figure 2 is a block circuit diagram of the shared memory access device, Figure 3 is a time chart of various signals, Figure 4 is a diagram showing the data processing process, and Figure 5 is a calculation mode table. 6 and 7 show a conventional example, FIG. 6 is a block circuit diagram of a conventional shared memory access device, and FIGS. 7 and 8 explain the operation of this shared memory access device. This is a diagram to help you. 21...CPU, 22...CRT controller, 23...Shared memory, 24...Write data latch circuit, 25...Read data buffer circuit,
26... Arithmetic circuit, 27... Write data buffer circuit, 28... Read data latch circuit, 29
...Access control circuit.

Claims

[Claims for Utility Model Registration] A shared memory access device in which a CPU accesses the shared memory using a free period of an access cycle in which a CRT controller accesses the shared memory at regular cycle intervals, wherein the CPU accesses the shared memory from the CPU to the shared memory. a write data holding circuit that temporarily stores write data from the shared memory to the CPU; a read data holding circuit that temporarily stores read data from the shared memory to the CPU; and data read from the write data holding circuit and the read data holding circuit. an arithmetic circuit that executes a predetermined arithmetic operation based on the arithmetic operation; a transfer circuit that transfers the arithmetic result obtained by the arithmetic circuit to the shared memory; and a transfer circuit that transfers the arithmetic result obtained by the arithmetic circuit to the shared memory; data retention circuit,
A shared memory access device comprising: a control circuit for controlling a transfer circuit;