JPH0250899U - - Google Patents

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Publication number
JPH0250899U
JPH0250899U JP12714688U JP12714688U JPH0250899U JP H0250899 U JPH0250899 U JP H0250899U JP 12714688 U JP12714688 U JP 12714688U JP 12714688 U JP12714688 U JP 12714688U JP H0250899 U JPH0250899 U JP H0250899U
Authority
JP
Japan
Prior art keywords
dynamic ram
register
read data
latched
completed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12714688U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12714688U priority Critical patent/JPH0250899U/ja
Publication of JPH0250899U publication Critical patent/JPH0250899U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例のマイクロプロセツ
サ使用の中央処理装置のブロツク図、第2図は第
1図のタイムチヤートである。 1……マイクロプロセツサ、2……データバス
、3……制御線バス、4……DRAM、5……D
RAM制御部、6……データバスゲート、7……
ラツチレジスタ。
FIG. 1 is a block diagram of a central processing unit using a microprocessor according to an embodiment of the present invention, and FIG. 2 is a time chart of FIG. 1...Microprocessor, 2...Data bus, 3...Control line bus, 4...DRAM, 5...D
RAM control unit, 6...Data bus gate, 7...
Latch register.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] リフレツシユを必要とするダイナミツクRAM
の制御回路において、ダイナミツクRAMの外部
に読出しデータをラツチするレジスタを設け、該
レジスタに読出しデータをラツチし、ダイナミツ
クRAMの読出しサイクルを完了させ、その直後
にダイナミツクRAMのリフレツシユ動作をする
よう構成したことを特徴とする半導体メモリ制御
装置。
Dynamic RAM that requires refresh
In the control circuit, a register for latching read data is provided outside the dynamic RAM, the read data is latched in the register, the read cycle of the dynamic RAM is completed, and the dynamic RAM is refreshed immediately thereafter. A semiconductor memory control device characterized by:
JP12714688U 1988-09-30 1988-09-30 Pending JPH0250899U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12714688U JPH0250899U (en) 1988-09-30 1988-09-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12714688U JPH0250899U (en) 1988-09-30 1988-09-30

Publications (1)

Publication Number Publication Date
JPH0250899U true JPH0250899U (en) 1990-04-10

Family

ID=31379308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12714688U Pending JPH0250899U (en) 1988-09-30 1988-09-30

Country Status (1)

Country Link
JP (1) JPH0250899U (en)

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