JPS61154066U - - Google Patents
Info
- Publication number
- JPS61154066U JPS61154066U JP3609285U JP3609285U JPS61154066U JP S61154066 U JPS61154066 U JP S61154066U JP 3609285 U JP3609285 U JP 3609285U JP 3609285 U JP3609285 U JP 3609285U JP S61154066 U JPS61154066 U JP S61154066U
- Authority
- JP
- Japan
- Prior art keywords
- image data
- memory
- thinning
- circuit
- regular intervals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000013144 data compression Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Description
第１図はこの考案の一実施例を示すブロツク図
、第２図は間引きパターンの一例を示す説明図、
第３図はその間引きパターンの場合の第１図中の
点におけるクロツクを示す図、第４図は間引い
た結果のデータを示す説明図、第５図はメモリへ
のデータの格納の態様を説明するための図である
。
符号の説明、１，２……８ビツトラツチ、３，
４……８ビツトシフトレジスタ、５，６……８進
カウンタ、７，８，１２……ＡＮＤゲート、９，
１１……１ラインカウンタ、１０……ＲＡＭ、１
３……デコーダ、１４……Ｒ／Ｗコントローラ。
FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2 is an explanatory diagram showing an example of a thinning pattern,
Figure 3 is a diagram showing the clock at the point in Figure 1 in the case of a thinning pattern, Figure 4 is an explanatory diagram showing data as a result of thinning, and Figure 5 is an explanation of how data is stored in memory. This is a diagram for Explanation of symbols, 1, 2...8 bit latch, 3,
4...8-bit shift register, 5, 6...octal counter, 7, 8, 12...AND gate, 9,
11...1 line counter, 10...RAM, 1
3...Decoder, 14...R/W controller.
Claims (1)
ための間引きのパターンを発生させる回路と、間
引きのパターンに従つて逐次間引きが行なわれた
画像データを格納し、読み出すためのメモリと、
メモリへの格納、読み出しを一定間隔で繰り返え
すよう制御する回路とを有することを特徴とする
画像データ圧縮装置。 a circuit that generates a thinning pattern for thinning out image data at regular intervals according to an image data reduction rate; a memory that stores and reads image data that has been successively thinned out according to the thinning pattern;
An image data compression device comprising: a circuit for controlling storage and reading from a memory to be repeated at regular intervals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3609285U JPS61154066U (en) | 1985-03-15 | 1985-03-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3609285U JPS61154066U (en) | 1985-03-15 | 1985-03-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61154066U true JPS61154066U (en) | 1986-09-24 |
Family
ID=30540966
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3609285U Pending JPS61154066U (en) | 1985-03-15 | 1985-03-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61154066U (en) |
-
1985
- 1985-03-15 JP JP3609285U patent/JPS61154066U/ja active Pending
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