JPH0239399U - - Google Patents
Info
- Publication number
- JPH0239399U JPH0239399U JP11501088U JP11501088U JPH0239399U JP H0239399 U JPH0239399 U JP H0239399U JP 11501088 U JP11501088 U JP 11501088U JP 11501088 U JP11501088 U JP 11501088U JP H0239399 U JPH0239399 U JP H0239399U
- Authority
- JP
- Japan
- Prior art keywords
- refresh
- memory
- request signal
- signal
- counts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Dram (AREA)
Description
第１図は本考案の一実施例のブロツク図、第２
図はメモリがシングルリード／ライトのみで動作
中のリフレツシユ動作のタイミングチヤート、第
３図はブロツクアクセス中のリフレツシユ動作の
タイミングチヤートである。
１……カウンタ、２……リフレツシユリクエス
ト信号発生回路、３……メモリアービタ、４……
メモリコントローラ、５……メモリ。
Fig. 1 is a block diagram of an embodiment of the present invention;
The figure shows a timing chart of a refresh operation when the memory is operating with only a single read/write, and FIG. 3 shows a timing chart of a refresh operation while a block is being accessed. 1...Counter, 2...Refresh request signal generation circuit, 3...Memory arbiter, 4...
Memory controller, 5... memory.
Claims (1)
ムにおけるメモリリフレツシユ回路であつて、一
定の周期のリフレツシユクロツクにより１づつカ
ウントアツプし、リフレツシユ終了信号により１
づつカウントダウンするｎビツトカウンタと、こ
のカウンタの内容が“０”でないときにリフレツ
シユリクエスト信号を発生するリフレツシユリク
エスト信号発生回路と、ブロツクアクセス時には
ブロツクアクセスの終了時又はブロツクのページ
終了時にのみリフレツシユ許可信号を出力し、一
旦リフレツシユを許可したならばリフレツシユ要
求信号が出力されている限り続けてリフレツシユ
許可信号を出力するメモリアービタと、１回のリ
フレツシユ動作毎にリフレツシユ終了信号を出力
するメモリコントローラとからなるメモリリフレ
ツシユ回路。 A memory refresh circuit in a memory system using a dynamic memory IC, which counts up by 1 by a refresh clock with a constant cycle, and counts up by 1 by a refresh end signal.
An n-bit counter that counts down in increments of 0, a refresh request signal generation circuit that generates a refresh request signal when the contents of this counter are not "0", and a refresh request signal generation circuit that generates a refresh request signal when a block is accessed. a memory arbiter that outputs a permission signal and, once refresh is permitted, continues to output the refresh permission signal as long as a refresh request signal is output; and a memory controller that outputs a refresh end signal for each refresh operation. A memory refresh circuit consisting of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11501088U JPH0239399U (en) | 1988-09-02 | 1988-09-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11501088U JPH0239399U (en) | 1988-09-02 | 1988-09-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0239399U true JPH0239399U (en) | 1990-03-16 |
Family
ID=31356278
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11501088U Pending JPH0239399U (en) | 1988-09-02 | 1988-09-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0239399U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58182193A (en) * | 1982-04-19 | 1983-10-25 | Toshiba Corp | Refresh controller |
-
1988
- 1988-09-02 JP JP11501088U patent/JPH0239399U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58182193A (en) * | 1982-04-19 | 1983-10-25 | Toshiba Corp | Refresh controller |
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