JPS63107050U

JPS63107050U -

Info

Publication number: JPS63107050U
Application number: JP19861686U
Authority: JP
Priority date: 1986-12-26
Filing date: 1986-12-26
Publication date: 1988-07-11

Description

[Brief explanation of the drawing]

第１図は本案の一実施例を示すブロツク図、第
２図ａはメモリリードサイクルを示すタイミング
チヤート、第２図ｂはメモリライトサイクルを示
すタイミングチヤート、第２図ｃはメモリテスト
サイクルを示すタイミングチヤート、第３図は従
来のメモリテストのフローチヤート、第４図は本
案によるメモリテストのフローチヤートである。１……ＣＰＵ、２……メモリ、３……反転回路
、４……デジタルコンパレータ、５……ＪＫフリ
ツプフロツプ、６―１，６―２，６―３……バツ
フア、７……出力ポート、８……コントロール回
路。 FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 a is a timing chart showing a memory read cycle, FIG. 2 b is a timing chart showing a memory write cycle, and FIG. 2 c is a memory test cycle. A timing chart, FIG. 3 is a flowchart of a conventional memory test, and FIG. 4 is a flowchart of a memory test according to the present invention. 1...CPU, 2...Memory, 3...Inverting circuit, 4...Digital comparator, 5...JK flip-flop, 6-1, 6-2, 6-3...Buffer, 7...Output port, 8 ...control circuit.

Claims

[Scope of utility model registration request]

CPU, readable/writable memory, and the CP
A computer system comprising: control means for performing read-modify-write control on the memory in accordance with a memory write instruction from the CPU; a comparison means for comparing data read from the memory using hardware; a hardware holding means for holding discrepancy information detected by the comparison means; and a write cycle in the latter half of the read-modify-write cycle. A memory check circuit comprising hardware data inverting means for generating complement data of write data from the CPU and supplying it as write data to the memory.