JPH04170649A - Bus control circuit - Google Patents

Abstract

PURPOSE:To speed up an I/O reading cycle from a processor or the like by supposing that an address continued to the preceding read address coincides with the succeeding read address and preparing the data beforehand. CONSTITUTION:An address register 2 holds an address obtained at the time of accessing reading from a processor or the like. A transfer master 3 counts up the addresses stored in the register 2 only by one cycle, holds the count-up value, reads out the succeeding data from an internal memory 5, and writes the read data in a read data buffer 6. When a read request is outputted again through a bus 1, an address comparator 4 compares the address from the master 3 with the address of data stored in the buffer 6, and when both the contents coincide with each other, outputs the contents of the buffer 6 to the bus 1. Consequently, data reading time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus connection circuit, and particularly to a bus connection circuit for reading data from an I10 module.

[Conventional technology]

Conventionally, the technology for reading data from the I10 module has been to output data from internal memory according to the address after a read cycle from a processor or the like occurs.

[Problem to be solved by the invention]

The above-described conventional bus control circuit has the disadvantage that it takes time to read data because the internal memory is accessed after a read request from a processor or the like is generated.

[Means to solve the problem]

The bus connection circuit of the present invention includes a register that holds the previous read address, counts up the address, reads data of the next succeeding address from the internal memory,
a transfer master for writing to the read data buffer;
A read data buffer that holds the data and outputs the held data onto the bus if the address matches the held data when the next read access from a processor etc. is performed; and an address comparator for determining whether the next access matches.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

A bus 1 is connected to a processor, etc., and performs data read/write to the I10 module.An address register 2 holds an address at the time of read access from the processor, etc. The transfer master 3 counts up the address held in the address register 2 for one cycle, rereads the next data from the internal memory 5, and then writes it to the read data buffer 6.

When a read request is made again via bus 1, the value obtained by counting up the address is compared with the address of the data held in the read data buffer, and if they match, the contents of read data buffer 6 are transferred to bus 1. Output.

If they do not match, the contents of the current read address are output from the internal memory onto bus 1. Further, the contents of the address register are updated to the current read address, and the above procedure is repeated again.

〔Effect of the invention〕

As explained above, the present invention assumes that the address consecutive to the previous read address will match the next read address, and prepares that data in advance so that the I10 read cycle from the processor etc. This has the effect of speeding up the process.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Bus connected to processor etc., 2... Address register, 3... Transfer master, 4... Address comparator, 5... Internal memory, 6... Read data buffer, 7 ...I10 control unit.

Claims (1)

[Claims] a register that holds an internal memory read request address from a processor or the like; a transfer master that holds the request address after counting up, reads data at the counted up address from the internal memory, and writes it to a read data buffer; A bus control circuit comprising: a read data buffer that holds the data; and an address comparator that compares the next internal memory read access address from a processor or the like with the address of the data in the read data buffer.