JPH03132852A - Bus asynchronous control system - Google Patents

Abstract

PURPOSE:To shorten a bus sequence and to increase the access speed by discontinuing the hitherto synchronous control when a temporary holding mechanism is hit to perform the control to temporarily switch to the asynchronous control and therefore eliminating the overhead which is caused with synchronization of an asynchronizing signal. CONSTITUTION:The bus width set between the temporary holding mechanisms 3/4 and a memory 2 is at least double as much as the bus width set between the mechanisms 3/4 and a processor 1. Then the data equivalent to 2 words are read at one time out of the memory 2 and outputted to the processor 1. When the coincidence is secured between the address outputted from a cycle continued from the processor 1 and the addresses which are temporarily held by the mechanisms 3 and 4, i.e., both mechanisms 3 and 4 are hit, the held data are outputted and the bus synchronous control is temporarily switched to the asynchronous control. Then the data on the mechanisms 3 and 4 are read out. In a mishit mode, however, the electric power is suppressed for the held data and at the same time a direct access is given to the memory 2. Thus it is possible to temporarily eliminate the overhead caused when an asynchronizing signal is turned into the sunchronizing one and to improve the processing ability of the processor.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a bus asynchronous control method that includes a temporary holding mechanism that temporarily holds data between a processor and a memory, and controls the bus between them asynchronously. The purpose is to temporarily eliminate overhead and improve the processing performance of the processor, and a temporary storage mechanism is provided between the processor and the memory to hold data, and the processor asynchronously controls the bus connecting between them. a bus control system, wherein the bus width between the temporary holding mechanism and the memory is at least twice the bus width between the processor and the temporary holding mechanism;
More than 28 minutes of data is read from the memory at a time and outputted to the processor, and the temporary holding mechanism temporarily holds this data along with address information, and the temporary holding mechanism outputs it in a subsequent read cycle. When the stored address does not match the temporarily held address, the processor directly accesses the memory, and when they match, it outputs the held data and temporarily changes the bus synchronous control to asynchronous control. The configuration is such that the data in the temporary holding mechanism is read out.

[Industrial application field]

The present invention relates to a bus asynchronous control system that includes a temporary holding mechanism for temporarily holding data between a processor and a memory and that controls a bus asynchronously.

[Conventional technology]

Conventionally, in a processor that performs asynchronous bus control, bus arbitration, D-RAM control, or accurate timing control of bus access has been performed by a synchronous circuit that operates in synchronization with a predetermined clock.

This is due to the requirements in the circuit configuration to easily control conflicts between bus requests that are output asynchronously and at irregular timings from devices that can become bus masters that make up the system, and to secure control margins. .

In addition, the row address strobe signal (RAS), which is a signal that controls the D-RAM, and the addressing (ADRCNG)
), column address signal (CAS), output enable signal (OE) and write enable signal (WE)
This is also to accurately control the timing of control signals such as, etc., and to minimize the effects of changes in device characteristics due to temperature, voltage, and aging.

FIGS. 4(a) and 4(a) are timing charts of the conventional system. In the figure, CLK is a clock, and DTSD# is a data center signal indicating that a bus sequence is being executed.

# is a negative logic symbol, and is turned on when it is “0” (during data transmission)
shows. ADDR is an address signal, and DTAK# is a data center signal indicating to the processor that the data is valid. As mentioned above, # is a negative logic symbol, and is on at "O".

In FIG. 4(a), when DTSD# is turned on in synchronization with the fall of clock CLK at tl, address ADD
If R is a match, DTAK# is turned on at the next clock fall t2. In other words, the clock and DTAK# are synchronized.

Fig. 4(b) shows that DTSD# is turned on in synchronization with the fall of the clock at tl, and if it is hit, the DSD
TAK# turns on.

[Problem to be solved by the invention]

By the way, the frequency of the clock that operates the processor,
If the frequencies of the clocks operating the bus arbiter or memory controller are different, overhead will inevitably occur when synchronizing asynchronous signals. As a result, the bus sequence becomes long, which prevents the processor from fully utilizing its potential capabilities, resulting in degraded performance.

On the other hand, as a countermeasure to this problem, in order to perform high-speed access to the bus, a memory bus with a bus width that is at least twice the data bus width of the processor is prepared, and an integer multiple of data corresponding to two words or more is read from memory at a time. , hold this in a temporary holding mechanism,
When the following cycle hits this temporarily held data, the temporarily held data is output instead of the data from memory, realizing high-speed access of the bus sequence. There is a method to shorten the time. In this case, if a miss occurs, the memory is accessed directly and the data from the memory is output.

However, even in this high-speed access method, a clock is used to control the opening/closing timing of the memory bus, the timing of data switching between the temporary holding mechanism and the memory bus, the response timing for notifying the end of the bus sequence, and the timing of bus arbitration. I was going.

If the data temporary storage mechanism only allows access by the CPU, access to the temporary storage mechanism does not require bus arbitration, so the CPU outputs the data to the memory control clock or the bus arbitration clock. There is no need to synchronize the signals.

From this point of view, when a processor performs asynchronous bus control in the conventional bus control system, overhead occurs due to synchronization of asynchronous signals output from the processor, and the processor's full potential cannot be utilized.

An object of the present invention is to use a data processing system that uses a processor that performs asynchronous bus control and has a high-speed access mechanism, and when a temporary hold mechanism is hit, the synchronous control that was being performed until then is suspended, and the asynchronous control is temporarily controlled. The purpose of this invention is to provide a bus asynchronous control method that eliminates the overhead that occurs when synchronizing asynchronous signals, shortens the bus sequence, and realizes faster access by controlling switching to do.

[Means to solve the problem]

The present invention provides a bus control system in which a temporary holding mechanism 3.4 for holding data is provided between a processor 1 and a memory 2, and the processor asynchronously controls a bus connecting between them, wherein the temporary holding mechanism The bus width between the processor and the memory is at least twice the bus width between the processor and the temporary holding mechanism, reads two words or more of data at a time from the memory, and outputs the data to the processor. The temporary holding mechanism temporarily holds this data together with address information, and in the temporary holding mechanism,
If the address output in the subsequent read cycle does not match the temporarily held address, the processor directly accesses the memory, and if they match, outputs the held data and performs bus synchronous control. Temporarily switches to asynchronous control to enable reading of data from the temporary holding mechanism.

[For production]

FIGS. 1(a) and 1(b) are system configuration diagrams to which the present invention is applied. In such a basic configuration, as shown in FIGS. 1(a) and 1(b), data is output to the processor through two routes: one from the memory and the other via the temporary storage mechanism (a). There are two configurations: (b) where a temporary holding mechanism is provided between the memory and the processor. Note that in (a) and et al., only the read sequence is shown for the data flow to simplify the explanation.

When the address output from the processor in the subsequent cycle matches the address temporarily held in the temporary holding mechanism, that is, when it is a hit, the output of the held data is valid, and when it is a miss. suppresses the output of the data held, directly accesses the memory, and outputs the obtained data to the processor.

In the conventional method, when this hit signal is synchronized, (a
), in the case of a system configuration with two data buses, open the route from the temporary holding mechanism, and
The next clock enabled the bus sequence response signal to the processor.

Similarly, in a system configuration where the temporary storage mechanism is on the data bus between the memory and the processor, as in
After synchronizing the hit signal, a response signal was returned to the processor. Even if this resulted in a hit, it was necessary to control the synchronization of the asynchronous signal.

Therefore, in the present invention, the output from the temporary holding mechanism that temporarily holds data is enabled by the hit signal and the data center signal indicating that the bus sequence is being executed, and
This data is delayed by the time necessary for it to reach the processor, from which a bus sequence response signal is formed, and this is output to the processor. Through asynchronous control, the overhead caused during synchronization is minimized and high-speed access is achieved. .

〔Example〕

FIGS. 2(a), 2(c) are timing charts of the bus asynchronous control system according to the present invention. In addition, (a),
Figures 4(a) and (b) are shown at the bottom for comparison.
) shows the timing of conventional DTAK#. As mentioned above, in the figure, CLK is a clock, DTSD# is a data center signal indicating that a bus sequence is being executed, and ADDR
is an address signal, and DTAK# is a data center signal indicating to the processor that the data is valid.

In FIG. 2(a), 1. The data center signal DTSD# is turned on by the fall of the clock CLK at
DTAK# due to address match after some delay d
turns on. Therefore, DTA is completely asynchronous to the clock.
K# is turned on.

As mentioned above, conventionally, DTSD# as shown in Fig. 4(a)
was once synchronized with the clock, and DTAK# was turned on at t2 in synchronization with the next clock.

In FIG. 2 (5), a hit is determined using the data center signal DTSD#, and if the address is a hit, DTAK# is turned on after a slight delay d.

Therefore, DTAK# is turned on completely asynchronously with the clock. As mentioned above, conventionally, as shown in Figure 4, etc.
If TSD# is valid and the address is hit, DTAK# is turned on in synchronization with the clock.

In this way, when the bus sequence is being executed and the address information output from the processor is compared with the address information held in pairs with the data from the previous read access, if they match, that is, the hit signal is If it is valid, the route from the temporary holding mechanism is valid, and after the data transit time has elapsed, that is, based on the signal that made the route valid, delayed by a delay line, etc., the response signal of the bus sequence is generated. shall be valid.

As a result, the overhead of 0 to 1 clock (average 0.5 clock) and the data passage, which were conventionally required for synchronization as shown in FIG. 4, are made effective, and
Only the delay d is used for 1 to 3 clocks in accordance with the 1 to 2 clocks required for bus sequence response (
Although it depends on the output timing of the address, it is possible to complete the sequence in normally (sufficiently shorter than one clock).

FIG. 2C shows a case where a hit is determined based only on address information and DTAK# is turned on.

In this way, DTSD# indicates that the bus sequence is being executed.
Prior to the signal, address information ADDR is output and DTAK indicating that this address information is valid.
In the processor that outputs the # signal, the DTSD
The bus sequence response signal can be prepared before # becomes valid, and the time required for delay d can even be reduced as shown in the figure.

FIG. 3 is a configuration diagram of an embodiment of a system to which the present invention is applied. In the figure, l is a processor, 2 is a memory, 3.4 is a data time holding mechanism, 5 is a determination mechanism, and 6 is a bus sequence control mechanism. In addition, Sl is an address match signal, S2
is the memory sequence suppression signal, AB is the address bus, D
It is a Bltf-9 bus.

The processor 1 can serve as a bus mask, and is a CPU or the like. The memory 2 is a main storage device that stores code information and data information. The bus sequence control mechanism 6 has a function of controlling various timings of code fetch, data read, data write, I10 access, etc. regarding the bus sequence of the processor. The temporary holding mechanism 3 is a data holding mechanism for code information, and holds data when the processor accesses the memory for code fetch. The address information output from the processor 1 and the address information temporarily stored here are always compared, and if they match, the address match signal S1 is made valid. "F" means fetch. The temporary holding mechanism 4 is a temporary data holding mechanism for data information, and holds data when the processor accesses the memory to read data. The address information output from the processor is constantly compared with the temporarily stored address information, and if they match, the address match signal is validated. "R" means lead.

The determination mechanism 5 determines the type of access (code fetch, data read, data write, I10 read, I10 write, etc.) based on the address match signal S1 output from the temporary holding mechanism 3.4 and various signals output from the processor. , a memory sequence signal S2 and a control signal S3 to the bus sequence control mechanism 6.

In such a configuration, an actual control sequence will be explained below.

■First, the processor outputs address information prior to the bus sequence.

(2) Based on this address information, the determining mechanism 5 determines whether it is a hit or a miss.

■The processor outputs the DTSD# signal.

(2) The address match signal S1 is sampled using this DTSD#.

■If there is a hit (address match), see Figure 2 (a).
), DTAK# is enabled as shown in (b).

■If there is a mishit (address mismatch), a bus request is output.

■Once bus control is established, access the memory.

Next, as shown in FIG. 2(C), address information is output prior to the bus sequence, and a signal indicating address confirmation is output faster than the DTSD# signal indicating that the bus sequence is being executed. The control sequence in this case will be explained.

■Address information is output before the bus sequence.

(2) The determination mechanism 5 determines hits and misses based on address information.

(2) A confirmation signal DACT# indicating confirmation of address information is output.

■Sampling the address match signal using this confirmation signal.

■If hit, DTAK# is valid.

■DTSD# is output.

■DTAK# is valid and the bus sequence ends.

■If there is a mishit, a pass request is output.

■Once bus control is established, access the memory.

〔Effect of the invention〕

As explained above, according to the present invention, when using a processor that performs asynchronous bus control, by temporarily eliminating the overhead that occurs when synchronizing asynchronous signals, the performance of the processor can be improved for a short period of time. You can make the most of it.

[Brief explanation of the drawing]

Figures 1 (a) and 3) are system configuration diagrams to which the present invention is applied; Figures 2 (a), (b), and (C) are timing charts of the bus asynchronous control method according to the present invention; and Figure 3 is a diagram of the present invention. A configuration diagram of an embodiment of a system to which the invention is applied,
4(a) and 4(b) are timing charts of the conventional system. (Explanation of symbols) 1... Processor, 2... Memory, 3.4... Temporary holding mechanism, 5... Judgment mechanism, 6... Bus sequence system aam, AB... Address bus, DB...Data bus, CLK...Clock, DTSD#...Data center signal, DTAK#...Data center signal, ADDR...Address signal.

Claims (1)

[Claims] 1. A bus control method comprising a temporary holding mechanism for holding data between a processor and a memory, and in which the processor asynchronously controls a bus connecting between them, the temporary holding mechanism and The bus width between the memories is at least twice the bus width between the processor and the temporary holding mechanism, and the data of two words or more is read from the memory at a time,
While outputting this to the processor, the temporary holding mechanism temporarily holds this data together with address information, and in the temporary holding mechanism, the address output by the subsequent read cycle is the same as the temporarily held address. When a match does not match, the processor directly accesses the memory, and when a match occurs, outputs the held data, temporarily switches bus synchronous control to asynchronous control, and reads the data from the temporary holding mechanism. A bus asynchronous control method featuring: 2. The processor outputs address information prior to a data send signal indicating the start of a bus sequence, and further outputs a data acknowledge signal indicating that the address information is valid, thereby controlling the bus asynchronously. 2. The method according to claim 1, wherein the data acknowledge signal determines whether the hit or miss is detected, and a response signal indicating the end of the bus sequence is enabled before or at the same time as the data center signal is output. Bus asynchronous control method.