JPS60122448A - Memory system - Google Patents

Abstract

PURPOSE:To attain high reliability or high speed of storage by designating an area to a storage device provided with the 1st storage area storing information required for error detecting bit and the 2nd area storing information which makes an error detection bit unnecessary, by means of a deciding circuit. CONSTITUTION:A memory block 2 is divided into the 1st area 21 to which a parity bit is added with significance and the 2nd area 22 whose parity bit is neglected. Moreover, an address comparison circuit 25 compares an address outputted from a microprocessing unit MPU with a set value (m) of a register 23 in reading/writing a decoder to the area 21. When an address A, where A<=m, is outputted from the MPU in writing and reading, the output of the circuit 25 is unchanged and the parity is generated and checked to the area 21. When A>m next, a ''0'' signal is outputted from the circuit 25 and a signal is changed over by a timing control circuit 18 and the write of the parity bit as to the area 22 is neglected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory system that stores a mixture of information that requires error detection bits and information that does not necessarily require overlap detection bits.

[Technical background of the invention and its problems]

FIG. 1 is a block diagram of a conventional memory system. l
is the detail of memory f4?11, which receives information such as data, addresses, control signals, etc. from a microprocessor unit (MPU) (not shown), and stores memory block 2.
Perform side allocation for data writing and reading. 1] is a parity generator (PG), which is a circuit that generates parity based on the data sent from the MPU when writing data to the memory +1 block 2. Reference numeral 12 denotes a parity check circuit (PC) which, when reading data from the memory block 2, judges whether the parity of the read data is correct or not, and outputs a data available signal. 13 is an MPH data bus, and 14 is a parity signal line through which parity bits are read and written. 15 is a signal line for sending a data available signal to the MPH. 16 is an address bus of the MPU. 17 is the MPH control bus, and various parts (control signals are exchanged) that are essential for accessing the memory block 2. 181 is the timing control circuit (TO);
It receives memory access requests from the PU and controls the sending timing of various control signals. For example, when the memory block is composed of dynamic memory, T O+8 also outputs control signals such as row atsis select and raster address select, but in Fig. 1, from case j in the explanation, only the data strobe signal is output. It is shown. Reference numeral 19 denotes a signal line to which a data strobe signal for starting all data writing in the memory block 2 is output when all writing data is stable during data writing.

The memory block 2 has n address spaces, and each address stores 8 bits of data (pits 0 to 7) and 9 bits of information IH including a parity bit (P).

FIG. 3 shows the timing of data writing in the conventional memory system, and FIG. 4 shows the timing of data reading in the conventional memory system. In each figure, data nutrobe timing 2 and data availability 2 are related to the present invention, which will be described later.

When writing data to memory block 2, the MPU:
First, send the memory ride request signal to control bus 1.
7 and at the same time write address to address path 16.
Output to. followed by a period during which these signals stabilize)
The data is output to the data bus 13 after waiting. P.G.II.
generates parity from the data on the data bus 13.

Until PGII generates parity, K waits a period of Tl from sending data. When the parity is output from PGII, the write data to memory block 2 is complete, so after a period of +2 to the history (the period for which parity is stable should be longer), the data strobe signal (ps) is sent from TOIB to the memory block. 2 is output. T
O+8 is output from the memory ride request signal (T
4+TI+T2) period, the data strobe signal (DS
) Logic is set up to output i. When data writing is completed, a write end signal is output from the memory block 2 to the MPU via the control o-, +17 bus 17 (not shown). Upon receiving this signal, the MPU lowers the memory write request signal and ends the data write cycle. As a result, in one data write cycle (T
This will require an investment of 4+T t+'r 2+T 3).

On the other hand, when reading data from memory block 2, V? :,
Then, the MPU outputs a memory read request signal to the entire control bus 17 and simultaneously outputs the read address to the address path 16. When the memory block 2 receives the memory read request and address, it starts outputting the read data on the data bus after a period of +5. PC
! 12 receives read data and parity and performs a parity check. For parity check, data 0 to 7, P
A period of +8 is required as the sum of the period for which PCl3 is stabilized and the operation time of PCl3. Then, a data available signal is outputted to the MPU for a further period of +6. When the MPH receives this data available signal, it interprets the read data as positive and takes in the data on the path. When M1'U completes data acquisition, it lowers the memory read request and ends the memory read cycle. As a result, in one cycle of reading data, (T 5 + T 8 + T 6
+T 7 ).

Now, among the data stored in memory block 2, 1
Dot information is like pixel data that is expressed as 1-bit data (even if there is a 1-bit deviation, it does not affect the output much.

As described above, when all parity bits are added to memory write data, the read/write cycle time includes the time for generating or checking the parity bits. Therefore, when a parity bit is added to the memory for storing pixel data, a large amount of data is read/written as a percentage of pixel data, so the overall processing speed of graphic processing and image processing is reduced by the memory cycle time. Sorry for the delay due to redundancy. For this reason, a memory system dedicated to pixel data includes harity bits, PG,
There are also versions with pc'l deleted.

However, if the information stored in the memory system is a mixture of information that requires valid bits, such as code data, and information that does not necessarily require parity bits, such as pixel data, the memory All parity pits were added to each Atrea in the system. Therefore, the above-mentioned high-speed reading/writing of pixel data cannot be achieved.

[Purpose of the invention]

The present invention provides a memory system that stores a mixture of information that requires a parity bit of 5m and information that does not necessarily require a parity bit, while ensuring high reliability in the storage of information that requires a parity bit. , Parity Bit The object of the present invention is to provide a memory system that deletes or ignores parity bits for information that is not necessarily required, thereby increasing the speed of reading/writing thereof.

[Summary of the invention]

In order to achieve the above object, in the memory system of the present invention, the storage device has a first area where information that makes the error detection bit significant is stored and a second area where information where the error detection bit is not used is stored. and. Then, whether the address to access this storage device specifies the first area or the address that accesses this storage device specifies the first area or
Based on the judgment result of this judgment circuit, if the address specifies the entire first area, an error detection bit data generation circuit detects an error when writing. An error detection circuit detects data errors when generating and reading out bit data for use, thereby ensuring high reliability for information in the first area. On the other hand, when the determination result indicates access to the second area, the second area is The aim is to speed up the reading/writing of information within.

[Embodiments of the Invention] Hereinafter, a memory system of the present invention will be explained in detail by way of an actual example.

FIG. 2 is a block diagram of the embodiment. Components that are the same as those of the conventional memory system shown in FIG. 1 are given the same reference numerals. The feature of this embodiment is that the memory block 2 is divided into a first area (addresses 0-m) 21 where parity bits are significantly added and a second area (addresses (m11)-n) where parity bits are ignored. The goal is to divide it into 22 parts. In the area 21, all parity pits are added, and code data and the like that require high data reliability are stored. On the contrary, the area 221c VX% stores information such as pixel data that does not necessarily need to be added to the parity bit'.

23 is a register in which the boundary m between the area 21 and the area 22 is set. The register 23 is allocated to the MPUf board, and its contents are transferred to the MPUf via the data storage 13.
It can be set from PU. 24 is a port decoder (A) for specifying data writing to the register 23;
D). 25 is an address comparison circuit (OMF). The address comparison circuit 25 is a circuit that compares the address output from the MPU with the set value m of the register 23 when decoder reading/8' to the memory block 21 is performed. In this embodiment, the output of the address comparison circuit 25 is designed to output logic "0" when the address is A) and A)m. The output of the address comparison circuit 25 is supplied to T018 and the AND gate 26. The AND gate 26 includes the output of PO12 and the address comparison circuit 2.
5 is input, and either signal is output to the MPH as a data available signal. T018 differs from the conventional case in that according to the output of the address comparison circuit 25,
Change the output timing of the data strobe signal (DS). Note that the TO 18 also controls the timing of various signals (for example, write enable, row address select, and LANUTA address select) supplied to the memory block 2, as well as the operation timing of the PGII, pC12, and address comparison circuit 25. , these signal lines are omitted from the drawing.

Figure 3 shows the timing chart when writing data, and Figure 4 shows the timing chart when writing data.
The figure shows a timing chart when reading data, and the operation of the memory system of the embodiment will be explained.

First, in writing and reading, when an address of A m is output from the MPU, the output of the address comparison circuit 25 does not change, and each circuit operates at the same timing as the conventional memory system shown in FIG. Operate. That is, area 21
When reading/writing data to/from, parity generation or checking is performed. Therefore, the cycle time for memory writing is as described above (T 4 + T t +
T2+T3), and the memory read cycle time is (T5+T8+T6+T7) as described above.
).

Next, a case will be described in which the MPU outputs an address of A>m when writing data. When the address becomes stable, the address comparison circuit 25 compares the set value m of the register 23 with the address (Al. In this case, A
)m, the address comparison circuit 25 outputs the logic ``'0.
” is output. This signal is input to T 018. At 'r c 18, the data strobe signal (DS)
The output timing of is switched as shown in data strobe timing 2.

That is, from TO+8, period 11 when data 0 to 7 are stable.
DS is output to memory block 2 after waiting iT2i.

When data writing is completed in the period T3, a write end signal is sent from memory block 2 to MPH.
Lower the U memory ride request signal. As a result, writing of the parity bit (P) in area 22 is ignored. In this case, the memory write cycle is (T4+
T2+T3).

Next, a case will be described in which an address of ^>m is output from the MPU when reading data. When the address becomes stable, the address comparison circuit 25 compares the set value m of the register 23 and the address (A). In this case, A)
m, the address comparison circuit 25 outputs the logic "'On".
The output will be output. This signal is input to the AND gate 26. The output of the address comparison circuit 25 is output after waiting for a period (T5+T6) in which the read data becomes stable.

This signal is output from the AND gate 26 as shown in data available 2. Upon receiving the data available signal from the MPU, and confirming that the data read from the memory block 2 is valid, the data θ to 7 are taken in. Then, when the data acquisition is completed, the MPU lowers the memory read request and ends the read cycle. The output of P O12 is ignored. Therefore, the read cycle is shortened to (T5-1-T6+T7).

As explained above, parity is added/checked for the information in the area 21, and parity is ignored for the information in the area 22, thereby increasing the speed of data reading/writing.

Note that the register 23 may be replaced with a switch or the like and a fixed value may be used. If m is a fixed value, address (m+1) ~
In the n portion, a memory element for storing the parity bit P is not required. In addition, multiple address comparison circuits are provided,
Each area may be subdivided. Furthermore, in the previous embodiment, odd-even harness was used for error detection, but other error detection codes such as a Haong code may also be used.

〔Effect of the invention〕

According to the memory system of the present invention, it is possible to ensure high reliability for memory areas that require parity bits, while speeding up memory cycles and improving processing speed for memory areas where parity is not necessarily changed. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional memory system, and FIG. 2 is a block diagram of a memory system according to an embodiment. Figure 3,
FIG. 4 shows timing control circuits for explaining the entire operation of the conventional and embodiment memory systems, respectively. 1...Memory control unit, 11...Parity generation circuit (
PG), 12... Parity check circuit (paLt8
...timing control circuit, 2...memory block,
21...First territory search, 22...Second area, 23.
...Register, 25...Address comparison circuit. Applicant's agent Kiyoshi Ino (15)

Claims (2)

[Claims] (1) A first area that stores information that makes the error detection bit of the data-only key written in each address significant, and a second area that stores information that does not use the error detection bit. based on a storage device having an area and an address for accessing this storage device, this address is the first address.
a circuit for determining whether to specify an area or a second area; and a circuit for generating error detection bit data based on this data and writing it to the storage device when writing data to the storage device. A detection bit data generation circuit, an error detection circuit that performs error detection using the read data and error detection bit data when reading data from the storage device, and the determination circuit determine whether the access address is the second 1. A memory system comprising: a circuit that speeds up the memory cycle time without waiting for the output of the bit data generation circuit for color detection or the error detection circuit when it is determined that the area is within the range of . (2) The address determination circuit is characterized by comprising a register in which a boundary value between the first area and the second area is set, and a circuit that compares this set value with the access address. A memory system according to claim no.