JPS5810142U

JPS5810142U - central processing unit

Info

Publication number: JPS5810142U
Application number: JP10256281U
Authority: JP
Inventors: 増本　大和
Original assignee: 日本電気株式会社
Priority date: 1981-07-10
Filing date: 1981-07-10
Publication date: 1983-01-22

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来の一例を示すブロック図、第２図は本考案
の一実施例を示すブロック図である。１・・・・・・アドレス部、２・・・・・・制御記憶部
、３・・・・・・保持部、４・・・・・・チェック部、
５・・・・・・論理部、６・・・・・・クロック部、７
・・・・・・アドレス保持回路、８・・・・・・保持回
路、９・・・・・・チェック回路、１１・・曲アドレス
、１２・・・・・・マイクロプログラム語、１３・・・
・・・マイクロプログラム語、１４・・・・・・アドレ
ス、１０１・・・・・・パリティエラー信号、１０２〜
１０４・・・・・・クロック信号、１０５・・・・・・
クロック停止信号、２１・・・・・・出力アドレス、２
２・・・・・・マイクロプログラム語、１０６・・・・
・・エラー信号、１０７・・曲クロック信号、２（Ｎ、
２０２・・・・・・アンド回路。FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1... Address section, 2... Control storage section, 3... Holding section, 4... Check section,
5...Logic section, 6...Clock section, 7
...Address holding circuit, 8...Holding circuit, 9...Check circuit, 11...Song address, 12...Micro program word, 13...・
... Micro program word, 14 ... Address, 101 ... Parity error signal, 102 -
104... Clock signal, 105...
Clock stop signal, 21...Output address, 2
2...Microprogram language, 106...
...Error signal, 107...Song clock signal, 2(N,
202...AND circuit.

Claims

[Scope of utility model registration request]

a control storage section that stores a microprogram composed of microprogram words to which parity pits are added; an address section that stores an address for reading out the microprogram word from the control storage section; and the control storage section. A holding unit for holding the microprogram word output from the reading and holding unit, and a check that performs a parity check on the microprogram word held in the holding unit and outputs a parity error signal when the check results in a parity error. a logic section that operates according to the microprogram word outputted from the holder and further determines the next address of the microprogram and issues a clock stop instruction signal in response to the parity error signal; the address section and the holder; a clock section that supplies clocks to the logic section and the logic section; a holding circuit that holds the microprogram word at a timing earlier than the timing at which the holding section holds the microprogram word; and a parity check for the microprogram word held in the holding circuit. 1. A central processing unit comprising: a check circuit that outputs an error signal when an error is detected as a result of a check; and an address holding circuit that holds the address when the error signal is output.