JPS5885239U - Data processing equipment that automatically collects failure information - Google Patents

Data processing equipment that automatically collects failure information

Info

Publication number
JPS5885239U
JPS5885239U JP18010181U JP18010181U JPS5885239U JP S5885239 U JPS5885239 U JP S5885239U JP 18010181 U JP18010181 U JP 18010181U JP 18010181 U JP18010181 U JP 18010181U JP S5885239 U JPS5885239 U JP S5885239U
Authority
JP
Japan
Prior art keywords
main processor
main
contents
main memory
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18010181U
Other languages
Japanese (ja)
Inventor
和男 瀧
良一 高松
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP18010181U priority Critical patent/JPS5885239U/en
Publication of JPS5885239U publication Critical patent/JPS5885239U/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のデータ処理装置の全体構成図、第2図
は本考案の停止命令の命令形式を示す図、第3図は本考
案の主プロセツサが命令実行中か停止かを示す信号線3
0の接続図である。 10・・・パスライン、20・・・信号線セット、30
・・・信号線、40・・・信号線セット、100・・・
主メモリ、110・・・主メモリの特定番地、200・
・・主プロセツサ、210・・・制御ユニット、211
・・・クロック制御フリップフロップ、220・・・命
令実行ユニット、300・・・サービスプロセッサ、3
10・・・インターフェイス回路。
Figure 1 is an overall configuration diagram of the data processing device of the present invention, Figure 2 is a diagram showing the command format of the stop command of the present invention, and Figure 3 is a signal indicating whether the main processor of the present invention is executing an instruction or has stopped. line 3
0 is a connection diagram. 10... Pass line, 20... Signal line set, 30
...Signal line, 40...Signal line set, 100...
Main memory, 110... Specific address of main memory, 200...
・・Main processor, 210 ・・Control unit, 211
... Clock control flip-flop, 220 ... Instruction execution unit, 300 ... Service processor, 3
10...Interface circuit.

Claims (1)

【実用新案登録請求の範囲】 主メモリと、主メモリに格納された命令を実行する主プ
ロセツサと、主プロセツサの命令実行を開始させる機能
と主プロセツサの障害情報を収集する機能を有するサー
ビスプロセッサとからなるデータ処理装置において、前
記サービスプロセッサに対し、 (イ)前記主プロセツサの命令実行を開始させるに先立
ち前記主メモリの特定番地あるいはデータ処理装置中の
特定レジスタの内容を初期化する手段、 (ロ)前記主プロセツサが命令実行中から命令実行停止
に移行したことを識別する手段、 (ハ)前記主プロセツサが命令実行停止に移行したこと
を識別した後に、前記主メモリの前記特定番地の内容あ
るいは前記特定レジスタの内容を読み出す手段、 に)前記(ハ)の手段により読み出した前記主メモリの
前記特定番地の内容あるいは前記特定レジスタの内容が
、前記主プロセツサの障害停止を示す値であるか否かを
判断し、障害停止を示す値と判断した場合にのみ前記主
プロセツサの障害情報を収集する手段 を配置し、さらに、前記主プロセツサに対しては、 前記主プロセツサが命令実行中から命令実行停止に移行
する前に、前記主メモリの前記特定番地あるいは前記特
定レジスタに、前記主プロセツサが正常停止するか障害
停止するかを表わす情報を書きこむ手段 を配置したことを特徴とする、障害情報の自動収集を行
なうデータ処理装置。
[Claims for Utility Model Registration] A main memory, a main processor that executes instructions stored in the main memory, and a service processor that has a function of starting execution of instructions in the main processor and a function of collecting failure information of the main processor. (a) means for initializing a specific address of the main memory or the contents of a specific register in the data processing device before causing the main processor to start executing instructions; (b) means for identifying that the main processor has transitioned from executing instructions to halting instruction execution; (c) contents of the specific address of the main memory after identifying that the main processor has transitioned to halting instruction execution; or a means for reading out the contents of the specific register; and (2) whether the contents of the specific address of the main memory or the contents of the specific register read by the means of (c) are values indicating that the main processor has stopped due to a failure. means for collecting failure information of the main processor only when the value is determined to be a value indicating failure stop; The main processor is characterized in that means is arranged for writing information indicating whether the main processor stops normally or due to a failure into the specific address of the main memory or the specific register before transitioning to execution stop. A data processing device that automatically collects information.
JP18010181U 1981-12-04 1981-12-04 Data processing equipment that automatically collects failure information Pending JPS5885239U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18010181U JPS5885239U (en) 1981-12-04 1981-12-04 Data processing equipment that automatically collects failure information

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18010181U JPS5885239U (en) 1981-12-04 1981-12-04 Data processing equipment that automatically collects failure information

Publications (1)

Publication Number Publication Date
JPS5885239U true JPS5885239U (en) 1983-06-09

Family

ID=29976392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18010181U Pending JPS5885239U (en) 1981-12-04 1981-12-04 Data processing equipment that automatically collects failure information

Country Status (1)

Country Link
JP (1) JPS5885239U (en)

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