JPS5894036U - Microcomputer abnormality warning device - Google Patents
Microcomputer abnormality warning deviceInfo
- Publication number
- JPS5894036U JPS5894036U JP18777981U JP18777981U JPS5894036U JP S5894036 U JPS5894036 U JP S5894036U JP 18777981 U JP18777981 U JP 18777981U JP 18777981 U JP18777981 U JP 18777981U JP S5894036 U JPS5894036 U JP S5894036U
- Authority
- JP
- Japan
- Prior art keywords
- abnormality warning
- warning device
- abnormality
- microcomputer abnormality
- microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のマイクロコンピュータにおけるプログラ
ムメモリの周辺回路を示す機能ブロック図、第2図はこ
の考案のマイクロコンピュータの異常警告装置の一実施
例におけるプログラムメモリの周辺回路の要部を示す機
能ブロック図、第3図はリトリガラブル・モノステーブ
ル・マルチバイブレータの動作を説明するためのタイム
チャートである。
図面において、1はcpu、 2と3はプログラムメモ
リ、5はアドレスデコーダ、8はリトリガラブル・モノ
ステーブル・マルチバイブレータ、9はインバータ、1
0は異常警告表示用素子を示す。FIG. 1 is a functional block diagram showing a peripheral circuit of a program memory in a conventional microcomputer, and FIG. 2 is a functional block diagram showing a main part of a peripheral circuit of a program memory in an embodiment of the abnormality warning device for a microcomputer of this invention. 3 are time charts for explaining the operation of the retriggerable monostable multivibrator. In the drawing, 1 is a CPU, 2 and 3 are program memories, 5 is an address decoder, 8 is a retriggerable monostable multivibrator, 9 is an inverter, 1
0 indicates an abnormality warning display element.
Claims (1)
異常の発生を知らせる異常警告手段とを設け、前記読出
し信号が所定の時間内に発生されないときは、前記異常
警告手段を動作させて異常の発生を知らせることを特徴
とするマイクロコンピュータの異常警告装置。detection means for detecting a read signal of the program memory;
An abnormality warning device for a microcomputer, characterized in that the abnormality warning means is provided to notify the occurrence of an abnormality, and when the readout signal is not generated within a predetermined time, the abnormality warning means is operated to notify the occurrence of an abnormality. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18777981U JPS5894036U (en) | 1981-12-16 | 1981-12-16 | Microcomputer abnormality warning device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18777981U JPS5894036U (en) | 1981-12-16 | 1981-12-16 | Microcomputer abnormality warning device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5894036U true JPS5894036U (en) | 1983-06-25 |
Family
ID=30102788
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18777981U Pending JPS5894036U (en) | 1981-12-16 | 1981-12-16 | Microcomputer abnormality warning device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5894036U (en) |
-
1981
- 1981-12-16 JP JP18777981U patent/JPS5894036U/en active Pending
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