JPS59161716A - Timer control system of information processor - Google Patents

Abstract

PURPOSE:To allow a processor to know timer contents immediately and to perform plural timer operations corresponding to plural processes in the processor by clocking the time by using an optional address in the storage device in the processor. CONSTITUTION:The storage device 2 of the processor holds instructions to be executed by a CPU1 or data. When the CPU1 sends a setting instruction for an objective address of clocking or a timer value, the controller 3 receives and holds the address and timer value and waits for a clocking start instruction from the CPU1. Then when the clocking start instruction is executed by the CPU1, the controller 3 receives it and performs timer operation by increasing the contents of the timer value which is already indicated at specific intervals of time to write the contents in the address of the device 2. Further, when the CPU1 executed a clocking stop instruction, the controller 3 receives it to increase the contents at specific intervals of time, and stops writing the clocked value in the specific address.

Description

[Detailed description of the invention] (1) Technical field to which the invention belongs The present invention relates to a timekeeping control method for an information processing device.

(2) Description of Prior Art Conventionally, time in an information processing device is measured at specified time intervals within a specific control device.

Therefore, if the processing device wants to check the time measurement content at any time, it reads the time measurement content from within the control device, and
After that, processing is performed.As a result, the time measurement may deviate from the actual time.

Another disadvantage is that it is not possible to measure the time specified for each process based on the time value corresponding to each process for a plurality of processes executed by the information processing apparatus.

(3) Purpose of the Invention An object of the present invention is to provide a timekeeping control method for an information processing device that eliminates the above drawbacks and allows the processing device to read a specified memory address and instantly know the timekeeping contents. There is a particular thing. Another object of the present invention is to provide a timekeeping control method for an information processing device that is compatible with each process of the information processing device.

(4) Structure of the Invention The method of the present invention includes a storage means storing instructions and information, a holding means holding address information indicating an address of the storage means specified by the instruction and a time value, and a time measurement value. and means for incrementing the contents of the value every time a predetermined time elapses, and writing the contents to an address of the storage means specified by the address information from the holding means.

(5) Embodiment of the Invention Next, the present invention will be described in detail with reference to the drawings.
The information processing system is applied to an information processing system including a storage device 2 and a timing control device 3 connected to a central processing device 1, a storage device 2, and a timing control device 3.
, a control device 4 and a bus 5.

Referring to FIG. 2, the timekeeping control device 3 includes a control circuit 11, a line 21 connecting the control circuit 11 and a common bus (5 in FIG. 1), a memory 12, and a plurality of counters 13.1.
4, and 15, a line 23 for sending a signal from the control circuit 11 to the counter 13, a line 23 for sending a signal from the counter 13 to the control circuit j!
811, an oscillation circuit 16, and a line 24 for supplying pulse signals from the oscillation circuit 16 to the counters 13-115.

Referring to FIG. 6, the control circuit 11 includes a read-only memory (ROM) 41. It has a microprogram control circuit 42, an arithmetic circuit 43, an accumulator 44, a bus activation response circuit 45, and a bus register 46. Next, the operation of this embodiment will be explained in detail.

Referring to FIG. 1, each device 1 connected to a common bus 5
In the information processing device, when a control command such as a clock start command or a clock stop command, which is executed by the central processing unit 1, is received by the clock control device 3, a specified operation is executed. Storage device 2 of the information processing device
holds instructions or data to be executed by the central processing unit 1. When the central processing bag M1 executes a command to set the address and time value to be measured on the storage device 2 to the control device 3, the control device 3 receives and holds the above address and time value, and then executes the command to set the address and time value on the storage device 2. Waits for a timing start command from device 1. When the central processing unit 1 executes a timekeeping start command, the control device 3 receives the command, increments the contents of the specified timekeeping value at regular intervals, and starts the timekeeping operation. , writes this content to the address of the storage device 2 that has already been instructed (. It is incremented every time and stops writing the clock value to the specified address.

Next, the operation of the control circuit 11 will be explained in detail with reference to FIGS. 6 and 7. The ROM 41 stores microphone b commands for microprogram control of the timekeeping control device.
2 and are sequentially accessed, the contents of which are decoded and executed by the control circuit 42 as one microinstruction. The arithmetic circuit 43 has one memory 12. Accumulator 44
(* executes an operation on data from the bus register 46 and stores the result in the memory, and an accumulator 44.* indicates that it is stored in the bus register 46. The accumulator 44 is a register that temporarily stores the result of the operation. The path register 46 also stores the function code of the instruction when receiving an instruction from the central processing unit 1, and stores the write address and write data for the storage device 2 when writing data to the storage device 2. This is a register used for such functions.As shown in Figure 7, the flow of the microprogram is to receive commands from the bus or to register the counter circuit 1.
3. Wait until an interrupt from 14.15 is detected (
・Ru. When an instruction is executed from the central processing unit 1, the bus activation response circuit 45 detects this and stores the data on the bus in the bus register 46. If the command from the central processing unit 1 is an address and clock value set command, the address and clock value, which are data in the bus register 46, are stored in a designated area of the memory 12 via the arithmetic circuit 43. If it is a timekeeping start command, the address of the storage device 2 in the memory 12 is stored in the path register 46 via the arithmetic circuit 43. Thereafter, the clock value also stored in the memory 12 is stored in the path register 46 via the arithmetic circuit 43. As a result, the path register 46 stores an address and a clock value to be written into the storage device 2. In this state, the path activation response circuit 45 is activated under microprogram control and starts a memory write operation. Therefore, the address on the path register is used to
The time value on the pass register will be written to the specified address. When the write operation is completed, the microprogram processing waits until a request is received. If it is a timekeeping stop command, stop processing is immediately started.

An interrupt from the counter circuit 13, 14 or 15 writes through the microprogram control circuit 42 to the time value present in the tap. Thereafter, the clock value is written to the storage device 2, but this operation is the same as the write operation to the storage device 2 that is executed when a clock start command is detected. When an address and clock value set command corresponding to process O is executed from the central processing unit 1, the control circuit 11 receives the address O and clock value 0, and at the same time, under the control of the control circuit 11, the clock values are set in order from the top of the memo 1J12. Store address O.

Next, when a clock start command 0 is executed by the central processing unit 1, it is received by the control circuit 1.1, and the storage device 2 is accessed under the control of the control circuit 11 using the address 0 and clock value O in the memory 12. do. That is, the operation of writing the clock value 0 to address O is executed. When the write operation is received by the storage device 2 and the write is completed, the counter 1
3 and starts the operation of the counter 13.

The counter 13 is incremented by 1 at regular intervals by the signal from the oscillation circuit 16. The counter 13 is incremented by one by the signal from the oscillation counter 16, and when it counts over, an interrupt is generated to the control circuit 11 through the line 22. When the control circuit 11 detects this, it adds 1 to the contents of the clock value 0 in the memory 12 and stores the contents of the clock value O, which has already been incremented by 1, in the address O of the storage device 2 using address 0 in the same way as described above. . In this way, time measurement operation 0 for process 0 of the information processing device is started. Once such a control operation is started, the information processing device can execute the timekeeping process for process 0 simply by reading the contents of the specified timekeeping value 0 in the storage device 2 within the information processing device. Furthermore, the same explanation can be given to processing 1 and processing n within the information processing apparatus. For processing, the time value O, address O, and counter 13 in the memory 12 are used, but for process 1, the time value 1, address l, and counter 14 in the memory 12 are used.

Thereafter, in the same manner, the current value n of the memory 12, the address n, and the counter 15 are used for processing n. At this time, presets for counters 13, 14, and 15 are specified by control circuit 11, respectively. To stop the timekeeping operation performed as described above,
This is done by executing a clock stop command from the central processing unit.

When a timing stop command is received by the control circuit 11, processing 0 is performed.
In response to a stop command O that clocks in, the clock operation using address 0 and clock value 0 is stopped under the control of the controller 11. [stop command], only the corresponding time counting operation will be stopped for n.

FIG. 5 shows an example of an application of a timekeeping control system between information processing devices. The information processing device 31 performs timekeeping control by a timekeeping operation O using a clock value 0 and an address 0. If the information processing device 32 connected to the information processing device 31 performs a timekeeping operation within its own system, the device 31
When synchronizing the timekeeping operation with the timekeeping operation of the device 32, it is necessary to perform the timekeeping operation in accordance with the device 32.

In this case, the device 31 can execute a timekeeping operation that matches the device N32 by the timekeeping operation 1 using the clock value 1 and the address 1. Further, the information processing device 33 can be similarly synchronized using the clock operation n.

(6) Effects of the Invention The present invention allows the processing device to immediately know the contents of time measurement by measuring time using an arbitrary address in the storage device of the information processing device. Executing multiple timekeeping operations for a process has an effect.

[Brief explanation of drawings]

1 and 2 are diagrams showing one embodiment of the present invention, and FIG.
4 is a diagram showing the relationship between memory and storage device, FIG. 4 is a diagram showing an example of application of the present invention, FIG. 5 is a diagram showing the control circuit of FIG. 2, and FIG. 6 is a flowchart of microprogram processing. FIG. DESCRIPTION OF SYMBOLS 1...Central processing unit, 2...Storage device, 3...Timekeeping control device, 4...Control device, 11...Control [Route, 12... Memory, 13, 1.4, 15... Counter circuit, 1
6...Oscillation circuit, 31...Information processing device 0132...Information processing device 1.33...
...Information processing device n1.41...ROM, 42
...Microprogram control circuit, 43...
... Arithmetic circuit, 44... Achimulator, 45...
...Bus start response circuit, 46...Pass register. Figure 1 5 Figure 2

Claims (1)

[Claims] storage means for storing commands and information; storage means for displaying the address of the storage means specified by the command; holding means for holding address information and a timed value; 1. A timekeeping control method for an information processing apparatus, comprising: means for incrementing the time for each time and writing the contents to an address of a storage means specified by address information of the holding means.