JPS6020250A - Program delay tracing system - Google Patents

Abstract

PURPOSE:To improve the economization and the efficiency of record information of a program tracing device, by prohibiting the recording of ineffective information until the necessary period passes based upon the judgement result of a tracing condition. CONSTITUTION:Various kinds of the information, in which a central processor 1 transfers through a memory bus 2 at the section of a main memory device 3, are accumulated in order to a buffer register 41 and are transferred to a trace conditions decision circuit 42. The trace condition decision circuit 42 analyzes the information transferred through the memory bus 2 and rejects the recording of the information to the memory 44 for program tracing until the necessary period passes, by the operation of the timing circuit 45, and recording of the ineffective information is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a program tracing device, and more particularly to a program delay tracing method that prohibits recording until a predetermined period of time has elapsed after a predetermined condition is met.

~) Background of the technology In order to verify a program used in an information processing system, the program is stored in the main memory of the information processing system and executed by the central processing unit. A program trace device is used that records various information such as addresses, data, or control signals transferred to and from a storage device.

(C) Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional program tracing method. In FIG. 1, a central processing unit 1 is connected to a main storage device 3 via a memory bus 2, and sends addresses or control signals to the main storage device 3 via the memory bus 2 to sequentially extract stored programs or data. Then execute and execute.

The results are stored in the main storage device 3 via the memory bus 2. A program trace device 4 is connected to the memory bus 2 . The program trace device 4 includes a buffer register 4 that stores various information transmitted via the memory bus 2.
1, a trace condition determination circuit 42 that determines whether a predetermined trace condition is met, such as whether or not the information is within a specific address area, or whether or not it matches a specific control condition such as writing/reading; It is provided with a trace memory control circuit 43 that records information stored in the buffer register 41 in the program trace memory 44 when notified from the determination circuit 42 that the condition is satisfied. As the trace condition currently determined by the trace condition determination circuit 42, the program traces the information transmitted via the memory bus 2 when the central processing unit 1 accesses the address A after accessing the address X of the main storage device 3. It is assumed that the device 4 records the information. The trace condition determination circuit 42 analyzes information sequentially transmitted via the memory bus 2, and transmits a first condition fulfillment signal S1 to the trace memory control circuit 43 when address X is detected.

Subsequently, the trace condition determination circuit 42 analyzes the information sequentially transmitted via the memory bus 2, and when address A is detected, the trace condition determination circuit 42 transmits the second condition fulfillment signal s2 to the trace memory control circuit 4.
3. The trace memory control circuit 43 records the information stored in the buffer register 41 in the program trace memory 44 every time the second condition fulfillment signal S2 is transmitted after the first condition fulfillment signal S1 is transmitted.

As is clear from the above explanation, in the conventional program delay trace method, the trace condition determination circuit 4
2 detects the address X from the information transmitted via the memory bus 2, all the information for which the address A is detected is recorded. However, depending on the situation, it may be necessary to record information such that address A is detected after a predetermined period of time has elapsed from the time when address X was detected. It is impossible to prohibit recording until then, and there is a drawback that a large amount of invalid information must be recorded during that time.

(dl) OBJECT OF THE INVENTION The object of the present invention is to eliminate the drawbacks of the conventional program tracing method as described above and to realize a means for prohibiting recording of invalid information until a required period has elapsed.

(Q) Structure of the Invention This object is to analyze the information transmitted via the memory bus in a program tracing device that records information transferred between a central processing unit and a main storage device via a memory bus. A trace condition determining circuit is provided to measure the passage of a predetermined period of time, and a time limit circuit is provided to measure the passage of a predetermined period of time. This is accomplished by prohibiting the recording of the information until the lapse of a period is detected.

(f) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a program delay tracing method according to an embodiment of the present invention, and FIG. 3 is a diagram showing the recording process in FIG. 2. In FIG. 2, a time limit circuit 45 for measuring the passage of a predetermined period T is provided in a program tracing device 41. In FIGS. 2 and 3, the various types of information transferred between the central processing unit 1 and the main storage device 3 via the memory bus 2 are sequentially stored in a buffer register 41, and are also stored in a trace condition determination circuit 4.
2. The trace condition determination circuit 42 analyzes information sequentially transmitted via the memory bus 2, and transmits a first condition fulfillment signal S1 to the time limit circuit 45 when address X is detected at time t1. The timer circuit 45, which has received the first condition fulfillment signal sl, starts counting time and transmits the first condition fulfillment signal sl to the trace memory control circuit 43 at time t2 when it detects that the predetermined period T has elapsed. After time t1, the trace condition determination circuit 42 analyzes the information sequentially transmitted via the memory bus 2, and when address A is detected, transmits the second condition fulfillment signal S2 to the trace memory control circuit 43. The control circuit 43 does not record information in the program trace memory 44 unless the first condition fulfillment signal sl is transmitted from the time limit circuit 45. When the trace memory control circuit 43 receives the first condition fulfillment signal sl at time t2, the trace memory control circuit 43 updates the information stored in the buffer register 41 every time it receives the second condition fulfillment signal S2 from the trace condition determination circuit 42. is stored in the program trace memory 44.

As is clear from the above description, according to the present embodiment, the program trace device 4' performs a predetermined period T after the time t1 when the trace condition determination circuit 42 detects the address X from the information transmitted via the memory bus 2. Since recording of information is prohibited until time t2, invalid information is prevented from being recorded in the program trace memory 44.

Note that FIGS. 2 and 3 are only one embodiment of the present invention, and for example, the trace conditions given to the trace condition determination circuit 42 are not limited to those exemplified; Many modifications may be considered, such as recording the information stored in the buffer register 41 unconditionally after the lapse of time, but the effects of the present invention remain the same in any case. Furthermore, the configuration of the program tracing device 4' is not limited to that shown in the figure, and many other modifications may be considered.
In either case, the effects of the present invention remain the same.

tg> Effects of the Invention As described above, according to the present invention, in the program tracing device, recording of invalid information is prohibited until a required period of time has elapsed, making the program tracing device economical and improving the effectiveness of recorded information.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a conventional program 1-race method, FIG. 2 is a diagram showing a program delay trace method according to an embodiment of the present invention, and FIG. 3 is a diagram showing the recording process in FIG. be. In the figure, 1 is a central processing unit, 2 is a memory bus, 3 is a main memory, 4 and 4° are program trace devices,
41 is a buffer register, 42 is a trace condition determination circuit, 43 is a trace memory control circuit, 44 is a program trace memory, and 45 is a time limit circuit. Figure 2 Quick diagram

Claims (1)

[Claims] In a program tracing device that records information transferred between a central processing unit and a main storage device via a memory bus, a trace condition determination circuit that analyzes the information transferred via the memory bus; a time limit circuit for measuring the elapsed time; the trace condition determining circuit detects the establishment of a predetermined condition as a result of the analysis and activates the time limit circuit until the time limit circuit detects the elapse of the predetermined period;
A program delay trace method characterized in that recording of the information is prohibited.