JPS605534U

JPS605534U - program analyzer

Info

Publication number: JPS605534U
Application number: JP9619383U
Authority: JP
Inventors: 高木　治夫
Original assignee: オムロン株式会社
Priority date: 1983-06-22
Filing date: 1983-06-22
Publication date: 1985-01-16

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案によるプログラムアナライザを検査の対
象となるコンピュータシステムに接続した状態を示すブ
ロック図、第２図はアドレス比較回路の構成を示すブロ
ック図、第３図ａはオブジェクトプログラムが記述され
たメモリ３のメモリマツプ、第３図すはそのフローチャ
ート、第４図はプログラムアナライザの各部の波形を示
す波形図、第５図はヒストリメモリ２５の記憶内容を示
す図、第６図はヒストリメモリ２５のアドレスデータに
基づいて処理を行う場合のＣＰＵ１ｌの動作を示すフロ
ーチャート、第７図はメモリ１２のチェックポイントア
ドレステーブルを示す図である。１・・・・・・コンピュータシステム、２．１１・・・
・・・ＣＰＵ、３．１２・・・・・・メモリ、１８・・
・・・・デコーダ、２０・・・・・・アドレス比較回路
、２１・・・・・・Ｄ型フリップフロップ、２２・・・
・・・オア回路、２３・・・・・・タイミングコントロ
ール回路、２５・・・・・・ヒストリメモリ、３１．３
２・・・・・・レジスタ、３３．３４・・・・・・比較
回路、３７　・−−−−−フリップフロップ。FIG. 1 is a block diagram showing the state in which the program analyzer according to the present invention is connected to a computer system to be inspected, FIG. 2 is a block diagram showing the configuration of an address comparison circuit, and FIG. 3 is a flowchart of the memory 3, FIG. 4 is a waveform diagram showing the waveforms of each part of the program analyzer, FIG. 5 is a diagram showing the stored contents of the history memory 25, and FIG. FIG. 7 is a flowchart showing the operation of the CPU 11 when processing is performed based on the address data of . FIG. 7 is a diagram showing the checkpoint address table of the memory 12. 1... Computer system, 2.11...
...CPU, 3.12...Memory, 18...
... Decoder, 20 ... Address comparison circuit, 21 ... D-type flip-flop, 22 ...
... OR circuit, 23 ... Timing control circuit, 25 ... History memory, 31.3
2...Register, 33.34...Comparison circuit, 37 -------Flip-flop.

Claims

[Scope of utility model registration request]

(1) A program analyzer for analyzing a program of a computer system having a central processing unit and a memory connected to the central processing unit via a path line and storing a program, the program analyzer having a data bus of the system under test. an instruction decoder that is connected to detect the branch instruction; a timing control circuit that detects a timing signal when an address storing an operation code is accessed in the system under test; read signal generating means for delaying the output of a predetermined ending address from when the tested system accesses a predetermined starting address; address comparison means for operating the read signal generation means until accessing the read signal generation means; and a history memory connected to the address bus of the system under test for storing addresses accessed based on the output of the read signal generation means. A program analyzer comprising: branch determining means for determining whether or not a branch occurs due to a branch instruction based on the address data stored in the history memory.

(2) The address comparison means includes first and second setters that respectively set the test start address and end address, and first and second setters that compare the set values of the setters and the addresses accessed by the system under test. 2 comparators, and a flip-flop that is set by the output of the first comparator and reset by the output of the second comparator. The program analyzer described in the scope of item 1.