JPS6075945A - Program control type data processor provided with trigger timing function - Google Patents

Abstract

PURPOSE:To prevent the generation of undesired trigger timing by generating the trigger timing in response to the detection of a specific instruction address while monitoring the program control information and the data transferred to or from a peripheral device. CONSTITUTION:A program control type data processor is provided with a trigger timing circuit 1, a central processor 3, a memory 5, peripheral controllers 6-8, and peripheral devices 9-11 connected to the controllers 6-8. The circuit 1 produces the trigger timing in response to the detection of a specific instruction address while monitoring the program control information in the memory 5 and the transfer data stored in the memory 5 to or from devices 9-11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a program-controlled data processing device with a timing function.

[Prior art]

Generally, in a program-controlled data processing device, when analyzing a program being executed and checking the logic design, it is necessary to check whether or not an instruction at a specific instruction address of the program is being executed, or to It is necessary to check the status of various registers and G devices at the time of execution. To do this, the program monitors the execution instruction address of the block diagram and generates a trigger timing when a specific instruction address is reached.

The methods used are to interrupt the running program to start the analysis program, or to stop the program execution depending on timing, and to check the contents of various registers and storage devices in the stopped state using external measuring equipment. There is. However, although such conventional method θ is an effective means for shortening the time for program design evaluation, it is difficult to use the θ method in a block [1 program] simply to generate trigger timing by detecting a specific instruction address. During execution, if the instruction address is executed on a daily basis, a trigger timing outside the original January will occur. As a result, the design i1 evaluation efficiency decreased (unnecessary trigger timing was generated).
1E disturbs the execution time of the program being executed, making it impossible to set the correct iN'iPF value.

[Purpose of the invention]

An object of the present invention is to save write data at a specific address in a storage device in a data register, and to provide a means for detecting a match with a specific conversion condition (matching of all bits, on/off of a specific hit, etc.), Information in the storage device used for program control.

The above conventional drawbacks are eliminated by monitoring internal data in the device, which stores data exchanged with peripheral devices, and detecting the 4:f constant instruction address. An object of the present invention is to provide a program-controlled data processing device equipped with a trigger timing function that can regulate the execution time of a program and accurately evaluate the design of a program.

[Structure of the invention]

A program-controlled data processing device equipped with a trigger timing function according to the present invention includes a central processing unit controlled by a program processor, a plurality of peripheral control devices, a plurality of peripheral devices, and exchange between the program and the peripheral devices. In a data processing device having a storage device for storing data, a comparison instruction address setting means for accommodating a comparison instruction address to be compared with an execution instruction address of a program, and an address stored in the comparison instruction address setting means and an execution an address-number construction circuit for comparing the instruction address and detecting a matching state; a comparison access address setting means for accommodating a comparison access address to be compared with the memory access address; A memory access detection circuit that detects that the same memory access address as the memory access address is output to the address bus and that memory writing is being executed, and an output signal from the memory access detection circuit to accommodate data on the data bus. a data register, a comparison data setting means for accommodating comparison data with the data register, and a data comparison detection for comparing the data register and the data stored in the comparison data setting means and detecting the comparison state. a circuit, mode 1 setting means for accommodating mode data specifying an operation mode of the data comparison and detection circuit, an output signal from the address-number configuration circuit and an output signal from the data comparison and detection circuit; and a means for generating timing based on the logical product of .

[Embodiments of the invention]

Next, a program control type data processing device according to the present invention will be described in detail by giving examples and referring to the drawings.

FIG. 1 is a block diagram (not shown) of the configuration of an embodiment according to the present invention. In this figure, the program control type data processing device according to the present invention (2) includes a trigger timing circuit 1,
and a central processing unit 6.

Note 'l> + reversing device 5, A peripheral control device 6, third peripheral control device 7, C peripheral control device 8, and eight peripheral control device (4'
10 and a peripheral device (CRT display device) 11 connected to the C peripheral control device 8. Then, the trigger timing circuit 1, the central processing unit 6, f, . . .:i device i', c5, peripheral 1
The lilJ control device 6 is connected to a 16-bit address bus 12 and an 8-bit data bus 13, and each of the three peripheral control devices 7 and the C peripheral control device 8 is connected to a data bus 13. It is connected to the. The instruction address register 3-1 of 16 bits in the central processing unit B outputs an instruction address to the address bus 12, and with this address information as input, the instruction read from the storage device 5 is sent to the data bus 16. Ru. The central processing unit receives an instruction sent to the data bus 1 and executes the instruction. , the peripheral control device 6, the peripheral control device 7, and the peripheral control device 8 are the central processing unit 6.
The peripheral device 91, the peripheral device 10, and the peripheral device 11 are controlled based on the control of the block diagram executed by the peripheral device 91, the peripheral device 10, and the peripheral device 11, respectively.

In addition, because the data transfer speed is high, the peripheral control device 6 can directly transfer data without going through the program of the central processing unit B.
Note 1.・A circuit that can output a memory access address to the Atrunuhas 12 is built-in so that data φ can be sent to and from the reverse device 5.

The details of the operation except for timing circuit 1 are as follows.

Since this is carried out by a conventionally known method, the explanation will be omitted.

21st part 1 is the trigger timing circuit 1 in FIG.
This is a block diagram showing the concrete 4:s, r, configuration. As seen in the figure, this circuit.

16-bit comparison instruction address registers 1-1.1 . connected to data bus 13, respectively. 8-bit comparison access address register 1-2, 8-bit data register 1-3. 8-bit comparison data register 1-4, 8-bit mode register 1-5, and storage address of comparison instruction address buster 1-1 Address-number construction circuits 1 to 6 output an address match signal a in response to signals from the address bus 12 and addresses accommodated in the comparison access address registers 1-2 and receive signals from the address bus 12. hand.

Memory access detection circuit 1 that outputs a data accommodation signal
-7 and the data stored in the data register 1-3 retrieved by data storage A>4b.

A data comparison is performed in which the data stored in the comparison data registers 1-4 and the data stored in the mode registers 1-5 are used as a mode designation signal to perform a data comparison, and a signal C indicating the result is output. 41"1 from a detection circuit 1-8 and an AND gate 1-9 which takes this data comparison result signal C and the address match signal a as input signals and outputs a trigger timing signal d to the signal line 2 and external terminal 4. ′)
has been completed.

Table 1 shows details M+1 of the mode data stored in the mode register 1-5 for specifying the operation mode of the data comparison detection circuit 1-8 in FIG. Hereinafter, the method 1111''i of generating the trigger timing will be explained with reference to Table 1. First, the mode register 1-5 should be set as the initial J41J value to avoid setting the trigger timing to 4 unnecessarily. Then, the progera l executed by the central processing unit 6 reads +'+'r:, the notation i, . . .
The memory addresses in the three devices 5 are stored in the ratio access address registers 1-2 via the data bus 16.

The detected ratio data is similarly stored in the ratio data register 1-4 via the data bus 16.

Data registers 1-6 (second is the data for which the data comparison result signal C is not output in the first period).

Similarly, the specific instruction address to be detected is stored in the comparison instruction address register 1-1 via the data bus 13. Finally, mode data specifying the comparison operation mode of the data comparison detection circuit 1-8 is similarly stored in the mode register 1-5 via the data bus 13. As described above, preparation for trigger timing generation is completed by storing data in each register.

When the same address as the comparison access address register 1-2 is output to the address bus 12 and a memory write operation is performed using that address, the operation is detected by the memory access detection circuit 1-7 and the data register 1-2 is output.
A data accommodating signal is output toward 6. When the data register 1-6 receives this data accommodation signal, it accommodates the data from the data bus 13. Through this series of operations, r 1+:i Notes 1. The same data as the data at the memory address in the device 5 is always stored in the data registers 1-6. Here, it is assumed that 80X6 is stored in the mode register 1-5 and 5516 is stored in the comparison data register 1-4.

Until the data stored in the data register 1-6 reaches 5516, the data comparison detection circuit 1-8 does not output the data ratio (the result signal C).

Every time the data storage signal is output, the data register 1
-3 accommodates the data from the data bus 16, and when the data stored in the data register 1-6 reaches 5516, the data comparison detection circuit 1-8 detects a matching condition and outputs the data comparison result signal C. .

While the above data ratio 1 result A15C is being output, the comparison command address register 1 is sent to the address bus 12.
When the same instruction address as the instruction address stored in -1 is output, the address-number construction circuit 1-6 detects an address match and outputs an address match signal a. The AND gate 1-9 receives two inputs, the data comparison result signal c and the address match 1 word a, and when both are in the output state at j, the gate outputs the timing signal d.

Upon receiving this trigger timing signal d, the central processing unit 6 starts an interrupt operation, a program analysis routine vi is activated, and various registers and the storage device 5 are analyzed. Further, the trigger timing signal d is also supplied to the external terminal 4.

A signal to an external measuring device can be used as a signal. It should be noted that in the above example, in order to avoid unnecessary error signals in the data change section, a gate signal that is valid only for the necessary time can be created, and this can be multiplied by the timing signal. Sorry.

Table 1 [Effects of the Invention 1b] As is clear from the above description, one aspect of the present invention (''') is to safely specify assumed data at a specific address in a device in a data register. A means for detecting a match with the ratio 1 pattern condition is provided, and the program control within the device (iIi information and data exchanged with peripheral devices accommodated in the device) is implemented. while monitoring.

By generating trigger timing in conjunction with the detection of a specific instruction address, it is possible to prevent unnecessary trigger timing from occurring.

This regulates the program execution time.

Program design evaluation can be performed correctly.

The benefits of improving efficiency are significant.

[Brief explanation of drawings]

FIG. 1 shows 111. of one embodiment according to the present invention. FIG. 2 is a block diagram showing a specific configuration of the trigger timing circuit in the embodiment of FIG. 1. In the figure, 1 is a trigger timing circuit, 6 is a central processing unit, 5 is a storage device, 6 is a peripheral control device, 7 is a peripheral control device 8, 8 is a C peripheral control device, 9 to 11 are peripheral control devices. Peripheral devices, 1-1 is a comparison instruction address register, 1-2 is a comparison access address register, 1-6 is a data register, 1-4 is a comparison data register, 1-5 is a mode register, 1-6 is an address register. Several output circuits, 1=7 is a memory access detection circuit, 1-8 is a data comparison detection circuit, 1-
9 is an AND gate, and 6-1 is an instruction address register.

Claims (1)

[Claims] 1. A central processing unit controlled by a program, a plurality of peripheral control devices, and a plurality of peripheral devices. In a data processing device having a storage device for accommodating the program and data exchanged with the plurality of peripheral devices, a comparison instruction address setting means for accommodating a comparison instruction address to be compared with an execution instruction address of the program;
an address match detection circuit that compares the address stored in the comparison instruction address setting means with an execution instruction address and detects a matching state; and a comparison access address setting means for accommodating a comparison access address to be compared with the memory access address. a memory access detection circuit for detecting that a memory address identical to the memory access address stored in the comparison access address setting means is output to an address bus and that memory writing is being executed; and the memory access detection circuit. a data register for accommodating data on the data bus according to an output signal from the data register, a comparison data setting means for accommodating comparison data with the data register, and data stored in the data register and the comparison data setting means. A data comparison detection circuit that compares and detects the comparison state, and mode data that specifies the operation mode of the data comparison detection circuit? mode setting means for accommodating, an output signal from the address match detection circuit, and [)I
A megagram control type data processing device (+iii) having a trigger timing function, characterized in that it is provided with means for generating a trigger timing by logical product with an output signal from a data comparison and detection circuit.