JP2743889B2 - Method and apparatus for program evaluation - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function for step-executing only one machine language instruction of a program evaluation device, and more particularly to a procedure step execution for executing a subprogram to be called at a time.

When developing a program, one large program is usually divided into many small subprograms (or subroutines) for development. Most of the subprograms often call other subprograms for processing, and create multiple nesting relationships. Debugging such a program does not debug the entire large program from the beginning, but rather from the subprograms underneath the nesting of subprograms,
In many cases, debugging is performed sequentially toward the upper subprogram. In this case, since there is no defect in the lower subprogram after the completion of the debugging, there is no problem if the upper subprogram is treated as a black box when debugging the upper subprogram.

[0002] A program is often debugged by executing a program one instruction at a time and examining changes in registers and memory. In this case, a subprogram for which debugging has been completed is not included in the subprogram. Does not need to be executed step by step to check the change, and the change may be checked after executing the subprogram at once. For this reason, most program evaluation devices that perform program debugging work have a function called procedure step execution that executes the subprogram at once if the instruction to be stepped is a subprogram call instruction. Have.

[0003]

2. Description of the Related Art In order to execute at once a subprogram that has been debugged by a conventional procedure step execution function, the number of executions of a subprogram call instruction (hereinafter referred to as a CALL instruction) and the The number of executions of a return instruction (hereinafter, referred to as a RET instruction) from the server was counted, and when the respective values matched, it was determined that the execution of the subprogram was terminated. That is,
In FIG. 9, the instruction to be executed in (1) is a CALL instruction or a RE instruction.
It is determined whether the instruction is a T instruction or another instruction. If the instruction is a CALL instruction, for example, the CALL instruction is executed in (2) and the process proceeds to (3) to count the number of times the CALL instruction is executed.
Similarly, if it is determined that the instruction is a RET instruction in (1), (5)
At (6), the RET instruction is executed and the number of times is counted. If it is determined in (1) that the instruction is not the CALL or RET instruction, the instruction is executed in (4), and the process returns to (1) for executing the next instruction. Further, if the executed instruction is CA
If the instruction is an LL or RET instruction, the CAL is executed in (7).
The number of executions of the L instruction and the RET instruction are compared. If the number of executions matches, it is determined that the execution of the first subprogram called has been completed. Is not finished yet, and the process returns to (1) to execute the next instruction.

Next, an example of a conventional subprogram end determination method will be described in detail with reference to a program shown in FIG. The subprogram end determination method described below
Slightly different from the end determination method of FIG.
The execution count of the instruction is assigned to a variable called COUNT.
The COUNT variable is incremented by the execution of the CALL instruction, the COUNT variable is decremented by the execution of the RET instruction, and when the COUNT variable becomes 0, the subprogram termination judgment is performed. FIG. 10 shows that the subprograms SUB1 and SUB are included in the MAIN program.
FIG. 1 shows an example of a program that calls and performs processing.
FIG. 1 shows a schematic diagram of this process and changes in the COUNT variable. In FIG. 11, the CALL and RET instructions of (1) to (5) correspond to (1) to (5) of FIG. 10, but first, when the CALL instruction of (A) is executed,
The T variable is incremented to 1 and the CAL in (B)
COUNT variable = 2 by L instruction, C by RET instruction of (C)
COUNT variable = 1, COUNT by CALL instruction of (D)
Variable = 2, COUNT variable = 1 by RET instruction in (E),
Then, by the RET instruction in (F), the COUNT variable = 0, and the end of the subprogram is determined.

FIG. 12 shows a circuit for executing the above-described subprogram end determination method for changing the COUNT variable.
Here, FIG. 2 shows an overall view of the program evaluation apparatus, and FIG. 12 is located at 201 in FIG. Figure 2 below
A conventional example will be described with reference to FIG. In FIG. 2, reference numeral 200 denotes a program evaluation device, 201 denotes a subprogram end determination circuit, 202 denotes a central processing unit that executes a control program for controlling each unit of the program evaluation device,
203 and 204 are RAMs and ROs for control programs.
M and 205 are evaluation processors for executing a debugged program and a supervisor program for controlling execution of the debugged program, and 206 and 207 are RAM and ROM for the supervisor program, and 208 and 209.
Are RAM and ROM for the program to be debugged, 21
Reference numerals 0 to 212 denote various buses such as an address bus, a data bus, and a control bus for connecting each unit. 213, a reset signal for resetting a flip-flop in the subprogram end determination circuit 201; Control signals 215 are various control signals between the evaluation processor 205 and the sub-program end determination circuit 201, 216 is a target system controlled by the program to be debugged, and 217 is a various system between the evaluation processor 205 and the target system 216. bus,
218 is a host computer that controls the program evaluation device 200, and 219 to 222 are I / O ports. Hereinafter, when the debugged program is executed in the evaluation processor 205, it is called a user mode, and when the supervisor program is executed, it is called a supervisor mode. Next, in FIG. 12, 1 is a flip-flop circuit,
2 is an OR circuit, 9 is a supervisor interrupt request terminal (hereinafter S
VIRQ terminal), 10 is a step execution control terminal, 11 is a CALL strobe terminal, 12 is a RET strobe terminal, 14 is an 8-input OR circuit, 15 is an inverter, 16 is an up / down counter, and those corresponding to FIG. Numbered.

In evaluating the program, the host computer 218 stores the control program in the ROM 204
Then, the supervisor program is stored in the ROM 207 and the program to be debugged is stored in the ROM 209 in advance. In this case, without using the ROM, the RAM 203, 2
06, 208 may store each program. next,
The control program causes the evaluation processor 205 to start the supervisor program and prepare for the program evaluation. When the evaluation processor 205 is in the supervisor mode, the ROM 209 storing the program to be debugged is stored.
And the value of the internal register of the evaluation processor 205 based on the execution result of the debugged program, the RAM 208, and the state of the target system 216 as the case may be. However, in the case of this conventional example, the target system 21
6 is assumed to be a single-chip microcomputer, and the target system 216 does not particularly have a memory or the like.

When the evaluation of the program is started, the evaluation processor 205 generates a reset signal 213 to the central processing unit 202 in the supervisor mode to initialize the flip-flop 1 and the up / down counter 16. Then, referring to the ROM 209, it is determined whether the instruction to be executed by the debug target program is the CALL instruction or another instruction. If the instruction is other than the CALL instruction, the central processing unit 202 activates the step execution control signal 214. When the step execution control terminal 10 becomes active, the evaluation processor 205 executes one instruction of the program to be debugged in the user mode, and returns to the supervisor mode again. However, since the step execution control signal 214 is latched at the I / O port 222, the evaluation processor 205 causes the central processing unit 202 to make the step execution control signal 214 inactive when returning to the supervisor mode. Next, when the program to be debugged is a CALL instruction, the step execution control signal 214 is not activated, and the CALL instruction is executed in the user mode. In this case, the debugged program is continuously executed even after the execution of the CALL instruction. The evaluation processor 205 normally has the CALL strobe terminal 1
1 and 1 level are output to the RET strobe terminal 12, but when the instruction to be executed is a CALL or RET instruction, a 0 level is output to the CALL strobe terminal 11 when the CALL instruction is executed, and RET is executed when the RET instruction is executed.
It outputs 0 level to the strobe terminal 12. This is performed by processing incorporated in the microprogram of the CALL and RET instructions built in the evaluation processor 205 in advance. Here, the CALL strobe, RET in FIG.
The strobe and SVIRQ signals correspond to the control signal 215 in FIG. Since the flip-flop 1 has been reset in advance as described above, it outputs 1 level to the SVIRQ terminal 9. The up / down counter 16 counts up at the rising edge of the CALL strobe and counts down at the rising edge of the RET strobe. That is, it counts up when the execution of the CALL instruction is completed and counts down when the execution of the RET instruction is completed. The inverter circuit 15 includes an up-down counter 16
Is inverted. 8-input OR circuit 14
When the output of the inverter circuit 15 and the output of the D1 to D7 bits of the up / down counter 16 are all 0, that is, when the value of the up / down counter 16 is 1, S1
Output 0 level to the line. When the RET strobe goes to the 0 level when the S1 line is at the 0 level, the OR circuit 2 outputs the 0 level to the S2 line. The flip-flop 1 is set when the S2 line becomes 0 level,
Thereafter, 0 level is output to the SVIRQ terminal 9. When the SVIRQ terminal 9 becomes 0 level, the evaluation processor 205 stops executing the debugged program and returns to the supervisor mode.

In summary, when the RET instruction is executed when the count value of the up / down counter 16 becomes 1, it is determined that the execution of the subprogram has been completed.

FIG. 13 is a timing chart showing the operation of the subprogram end determination circuit of FIG. FIG.
In the figure, each symbol is common to FIG. At time t1 in FIG.
CALL strobe at t5 and t13 and time t9 and t1
7, the RET strobe at t21 is (A) in FIG.
(B), (D) CALL instruction, (C), (E),
(F) corresponds to the RET instruction. The outputs D0 and D1 of the up / down counter 16 are counted up at the rise of the CALL strobe and down counted at the rise of the RET strobe. The count value of the up / down counter 16 is set between time t2 and time t2.
5, it becomes 1 at t10 to t13 and t18 to t21, and S1
The line goes to the 0 level. Further, at time t21, the count value of the up / down counter 16 is 1 and RE
Since the T strobe is generated, the S1 line and the S2 line are simultaneously at the 0 level, and the subsequent SVIRQ is at the 0 level.

The program evaluation apparatus using the above-described subprogram termination determination method has no problem if the OS of the program to be debugged is an OS in which a plurality of programs do not operate in parallel as in the prior art. When a real-time OS is used, it may not operate normally.

[0011]

The following describes problems when a conventional subprogram end determination method is performed on a real-time OS. The real-time OS is an OS that operates while switching a plurality of programs divided into units called tasks according to circumstances, and issues a system call to the OS or generates an event due to an interrupt, and the task being executed is switched. Therefore, the real-time OS may be used when it is necessary to perform some parallel processing or processing involving management of the passage of time due to its characteristics. Also,
A task is developed by being divided into several subprograms as in a normal program.

In the real-time OS, the number of executions of the CALL instruction and the RET instruction may not match due to the task switching. Hereinafter, the number of executions of the CALL instruction and the RET instruction when the real-time OS is used will be described using the program shown in FIG. 14 as an example. The program in FIG. 14 includes MAIN_A, SUB1
_A and SUB2_A are TASK_A programs, and MAIN_B and SUB1_B are TASK_B programs. This TASK_A and TASK_B
Are a group of programs independent of each other, and TASK_A does not call TASK_B. FIG.
"CALL SYS_CALL" in the real-time O
This is where a system call is issued to S.
FIG. 15 is a schematic diagram of the processing when the program of FIG. 14 is executed.
It shows a state of switching to SK_A, TASK_B, and real-time OS. In this case, TIME3 to TIM
From E4, the task to be executed has been switched to TASK_B. FIG. 16 shows TASK_A, and FIG. 17 shows TAS.
A detailed process flow of K_B will be shown. The CALL and RET instructions in (2) to (11) in FIGS. 16 and 17 correspond to the instructions in (2) to (11) in FIG. Although FIGS. 16 and 17 are denoted by reference numerals (A) to (M) in accordance with the flow of the processing, FIGS.
(E) and (H) are RET instructions when the real-time OS returns to TASK_A, and (K) in FIG. 17 are RET instructions when the real-time OS returns to TASK_B. The operation to return to the task from the real-time OS is
It is managed by the OS itself. FIG. 18 and FIG.
CALL and R corresponding to (A) to (M) of FIG.
These are the address value of the stack pointer and the contents of the stack after the execution of the ET instruction. In the real-time OS, a separate stack area is assigned to each task, and when a task is switched, the stack area is switched together. In this example, the stack area of TASK_A is 0F7
40H to 0F77FH and the stack area of TASK_B is 0F700H to 0F73FH.
In FIG. 9, only the stack in the changing range is shown. In the real-time OS, since the return address of the subprogram can be managed for each task as shown in FIGS. 18 and 19, the subprogram can be independently called for each task.

The number of times the CALL instruction and the RET instruction are executed with respect to the subprogram call instruction (4) in FIG. 14 will be described. The execution of the subprogram SUB2_A called by the subprogram SUB1_A is completed in (8) ), That is, when the RET instruction of FIG. 16F is executed. During this time, TIM
Since TASK_B is executed from E3 to TIME4, TASK_A indicates C in FIGS. 16C and 16D.
ALL instruction and RET instruction of (E) and (F) are TASK
In _B, the CALL instruction in (L) and (M) of FIG. 17 and the RET instruction in (K) are executed. In other words, a total of four CALL instructions and three RET instructions are executed,
The number of times the CALL instruction and the RET instruction are executed is different. Therefore, when the conventional subprogram end determination method is used, there is a problem that it is determined that the subprogram has not ended even after the execution of the RET instruction of FIG.

[0014]

SUMMARY OF THE INVENTION In contrast to the real-time OS as described above, the present invention uses a stack pointer address value that changes when the processing of a program branches from a main program to a subprogram. This is for determining the end of the execution of the program. Specifically, when an instruction for calling a subprogram is present in the debugged program, the address value of the stack pointer when the instruction for calling the subprogram is first executed in the debugged program is held. The address value of the pointer and the current address value of the stack pointer changed during execution of the subprogram are compared, and when they match, it is detected that the execution of the subprogram called from the debugged program has ended.

[0015]

Embodiments of the present invention will be described below. FIG. 1 is an explanatory diagram of a basic process of the present invention as a first embodiment. In FIG. 1, reference numeral 100 denotes a program to be debugged; 101, a subprogram called by the program to be debugged in its processing; 102, a subprogram called by the subprogram 101;
Is a stack pointer address value holding means, 104 is a stack pointer address value comparing means, 105 is a stack pointer address value output signal, 106 is a match signal,
107 is a CALL instruction of the debugged program 100;
108 is an instruction of the subprograms 101 and 102, 1
09 is CALL and R of the program to be debugged 100.
Instructions other than the ET instruction, 110 is an evaluation processor, 11
1 is step execution control means, 112 is instruction execution processing, 1
13 is a process for checking the flag state of the step execution control means 111, and 114 is a process for checking the state of the instruction execution result of the debugged program 100 (program evaluation).
In the present embodiment, it is assumed that debugging of the subprograms 101 and 102 has already been completed.

When the evaluation of the program is started and an instruction other than the CALL and RET instructions in the debugged program 100 is executed, the step execution control means 111 sets a flag for executing the execution of the instruction.
2 is executed. Then, since it is determined that the flag is set in the process of checking the flag state of 113,
A process of checking the instruction execution result at 114 is executed. That is, the execution result is checked every time one instruction is executed.

As described above, the program to be debugged 100
If the instruction to be executed is a CALL instruction in the process of executing
When the CALL instruction is executed, the address value holding means 10
3 holds the address value of the stack pointer and outputs it to the address value comparing means 104. Then, the CALL instruction is executed without setting the flag of the step execution control means 111,
Call the subprogram 101. After the CALL instruction is executed, in the processing for checking the flag state of 113, it is determined that the flag is not set, so that the subprogram 101 is continuously executed. If there is a CALL instruction in the subprogram 101 as shown in (2), the address value of the stack pointer at the time of execution is compared with the address value comparing means 1.
04. Similarly, when the RET instruction is executed,
Address value comparing means 1 for comparing the address value of the stack pointer
04, and is sequentially compared with the address value of the stack pointer at the time of execution of the CALL instruction (1) output from the address value holding means 103. As the execution of the subprogram is continued, the RET instruction of (4) of the subprogram 101 is executed.
1 is an instruction to return to the program to be debugged 100. Therefore, in the address value comparing means 104, (1) CALL
A match with the address value of the stack pointer at the time of execution of the instruction is determined, and the match signal
And the step execution control flag is set.
Then, it is determined that the flag has been set in the flag state check processing in step 113, so that it is determined that the execution of the subprogram has been completed, and the processing proceeds to step 114 in which the instruction execution result is checked.

In summary, the address value of the stack pointer at the time of execution of the CALL instruction to be executed first in the execution of the program, that is, the address value of the stack pointer at which the return address of the program is held in the execution of the CALL instruction And proceed to execution of the subprogram. However, when the CALL instruction is included in the subprogram, the address value of the stack pointer is not held, and
The address value of the stack pointer changed by the CALL and RET instructions is compared with the address value of the stack pointer held first, and when they match, it is considered that the execution of the subprogram has been completed.

FIG. 1 shows a stack pointer in the process of executing the program of the real-time OS shown in FIG.
8, the comparison of the address value of the stack pointer will be described with reference to FIG. In MAIN_A which is the main program of TASK_A in FIG. 14, (1) "CALL
“SYS_CALL” simply branches back to the real-time OS and returns, so “(2) CALL SUB”
1_A ”will be described. In FIG. 18, since (2) in FIG. 14 corresponds to (B), “0F780H” is held in the holding unit for the address value of the stack pointer. Thereafter, the CALL instructions (B) to (D) are executed, and the address value of the stack pointer changes,
Its value is not retained. In the flow of time, TIME
Although the process has shifted to TASK_B in steps 3 and 4, the stack area is switched to the stack area for each task as described above.
_A, the address value of the stack pointer is T
This is the value before shifting to ASK_B. The following processing is executed,
After all, when the RET instruction of (I) is executed, the address value of the stack pointer becomes “0F780H”, so that it becomes equal to the held address value, and the execution of the subprogram called in (2) of FIG. 14 ends. Thus, the termination of the subprogram is correctly determined, and this method can cope with a subprogram branching process called a recursive call in which a certain program calls itself.

FIG. 3 shows a second embodiment in which the present invention is realized by a circuit (hardware). Here, the overall configuration of the program evaluation device is the same as that of FIG. 2 described in the conventional example. In FIG. 3, 1, 6, and 8 are flip-flop circuits, 2 is an OR circuit, and 3 is 1
6-input NAND circuit, 4 are 16 EXNOR circuits, 5
Is a 16-bit latch circuit, 7 is a NOR circuit, 9 is a supervisor interrupt request terminal, 10 is a step execution control terminal, 1
1 is a CALL strobe terminal, 12 is a RET strobe terminal, 13 is a stack pointer output terminal, and those corresponding to FIG. 2 and FIG. However, the various control signals 215 in FIG.
In addition to the L strobe, RET strobe, and SVIRQ, it also indicates a stack pointer output signal. FIG. 4 is FIG.
FIG. 4 is a detailed connection diagram of the 16-input NAND circuit 3 and the EXNOR circuit 4 of FIG. 3, where the corresponding bit lines of the 16 bit lines L1 and L2 in FIG.
When six EXNOR circuits compare, and all EXNOR circuits determine a match and output one level, a 16-input NA
The ND circuit 3 outputs 0 level.

The operation of the circuit shown in FIG. 3 will be described below. Second
In the embodiment, the evaluation processor 205 outputs the address value of the stack pointer to the stack pointer output terminal 13 and operates in the same manner as the conventional example in the supervisor mode and the user mode except that the OS is a real-time OS. Since the same operation is performed, operations other than the subprogram end determination are omitted. The flip-flops 1, 6, and 8 are reset by a reset signal 213 in advance as in the conventional example. The flip-flop 8, the NAND circuit 7, and the flip-flop 6 change the F3 line from the 0 level to the 1 level at the end of the execution of the first CALL instruction (the first rising of the CALL strobe), and thereafter, the CALL strobe is generated. Even so, the F3 line is kept at one level. The 16-bit latch 5 latches the value of the L2 line at the rise of the F3 line and outputs the value to the L1 line. That is, the 16-bit latch 5 latches the address value of the stack pointer at the end of the execution of the first CALL instruction, and holds the value thereafter. EXN
The OR circuit 4 and the 16-input NAND circuit 3 compare the output of the 16-bit latch 5 with the output of the stack pointer output terminal 13, and output a 0 level to the S1 line when the values match. When the RET strobe goes to the 0 level when the S1 line is at the 0 level, the OR circuit 2 outputs the 0 level to the S2 line. And flip-flop 1
Is set by the 0 level of the S2 line, and thereafter the 0 level is output to the SVIRQ terminal 9, and the evaluation processor 205 shifts to the supervisor mode.

FIG. 5 is a timing chart showing the operation of the subprogram end determination circuit of FIG. In FIG. 5, each reference numeral is common to FIG. Further, it is assumed that there is a task switching or the like between time t8 and t21. Note that, in the case of the present embodiment, the evaluation processor 205 subtracts 2 from the address value of the stack pointer by executing the CALL instruction, and adds 2 by executing the RET instruction. That is, 2 is subtracted from the address value SP of the stack pointer at the fall of the CALL strobe, and 2 is added at the rise of the RET strobe. Assuming that the address value SP of the stack pointer is a before execution of the first CALL instruction, a- at the start of the first CALL instruction at time t1.
It becomes 2. Then, in response to the end of the CALL instruction at time t1, the F2 line goes to the 0 level, and the F3 line goes to the 1 level. The 16-bit latch 5 stores the address value SP of the stack pointer corresponding to one level of the F3 line.
At the end of time t1, the L1 line becomes a-2. Thereafter, at the start of the CALL instruction at time t5, the F2 line becomes 1 level due to the CALL strobe, but the F3 line does not change, so the L1 line does not change either. However, the address value SP of the stack pointer is a-
It becomes 4. At time t25, at the end of the RET instruction, the address value SP of the stack pointer returns to a-2. That is, from time t26 to t29, the stack pointer address value S
Since the value of P returns to the value at the end of the execution of the first CALL instruction, the S1 line goes to the 0 level. Further, at time t29, the S1 line and the RET strobe go to the 0 level at the same time, and the S2 line goes to the 0 level.
Thereafter, SVIRQ goes to the 0 level, and the evaluation chip 20
5 shifts to the supervisor mode.

As described above, according to the second embodiment of the present invention, the address value after the stack pointer is changed during the execution of the first CALL instruction is stored, and the address value of the stack pointer that changes after that is successively compared. Do
By comparing with the address value before the stack pointer changes in the execution process of the RET instruction returning to the main program, it is possible to correctly determine the end of the subprogram.

As a third embodiment, the present invention realized by software is shown in FIGS. In the case of the present embodiment, unlike the second embodiment, the reset signal 213, various control signals and the stack pointer output signal 215, and the subprogram end determination circuit 201 are eliminated from the overall view of the program evaluation device of FIG. . Instead, software that realizes the end determination of the subprogram is stored in the ROM 207 as a part of the supervisor program.
Is stored in

The preparation up to the start of the evaluation of the program is the same as in the conventional example and the second embodiment, so that the description is omitted. When the evaluation of the program is started, the evaluation processor 205 activates the step execution control signal 214 by the central processing unit 202 in the supervisor mode. Then, the flowchart shown in FIG. 6 is started. That is, unlike the conventional example and the second embodiment, the step execution control signal 214 is activated irrespective of the type of instruction. Although not shown in the flowcharts of FIGS. 6 and 7, when executing the instruction of the program to be debugged, the supervisor program issues a supervisor return instruction (RETSVI instruction). This RETSVI
The instruction shifts the evaluation processor 205 to the user mode, executes one instruction of the debugged program, and then executes
This is a command to return to the supervisor mode again, and is valid only when the step execution control signal 214 is active.
The flowcharts of FIGS. 6 to 8 are described below. First, in (1), the instruction code of the instruction to be executed by the program to be debugged is checked with reference to the ROM 209 and stored in a variable called DATA secured in the RAM 206. In (2), it is determined whether the instruction code is a CALL instruction or another instruction. In the case of the present embodiment, the first byte of the instruction code representing the CALL instruction is “01H”, and the first byte of the instruction code representing the RET instruction is “02H”. Therefore, the instruction code is determined by examining the first byte of the instruction code. This can be performed by analyzing the instruction code in any information processing apparatus. If the instruction is an instruction other than the CALL instruction in (2), branch to (3), execute one instruction, and proceed to (11).
If the instruction is a CALL instruction in (2),
The flow branches to a flowchart for determining the end of the subprogram shown in FIG. Next, in (4) of FIG. 7, the address value of the stack pointer is stored in a variable called VALUE secured in the RAM 206. Then, the evaluation processor 205 shifts to the user mode, executes the CALL instruction of (5), returns to the supervisor mode again, and proceeds to (6) of FIG. In (6) and (7), the same processing as in (1) and (2) is performed, and the instruction in the subprogram called by the CALL instruction in (5) is a RET instruction or a CAL instruction.
It is determined whether the instruction is another instruction including the L instruction. RE at (7)
If the instruction is other than the T instruction, the process branches to (10) in FIG. 7 to execute one instruction and returns to (6). If the instruction is a RET instruction in (7), the process branches to (8), executes the RET instruction, and proceeds to (9). In (9), the VALUE variable which is the address value of the stack pointer held in (4) is compared with the current address value of the stack pointer.
If they do not match, the procedure returns to (6). If they match, it is determined that the execution of the subprogram has been completed, and the process proceeds to (11) in FIG. (11) is similar to the supervisor mode of the conventional example or the second embodiment, in which the step execution control signal 214 is made inactive, and the process of monitoring the execution result of the program to be debugged is started.

As described above, the third embodiment of the present invention stores the address value before the stack pointer changes during the execution of the first CALL instruction, and successively compares the address value with the changing stack pointer address value. Do
By comparing with the address value after the change of the stack pointer in the process of executing the RET instruction returning to the main program, it is possible to correctly determine the end of the subprogram.

[0027]

According to the present invention, in the procedure step execution of the program evaluation apparatus using the real-time OS, the conventional method for counting the number of executions of the call instruction and the return instruction of the subprogram correctly judges the execution end of the subprogram. What could not be done is executed using the stack pointer, which is generally changed by execution of a subprogram call instruction and return instruction provided in the information processing device, and observing a change in the address value of the subprogram. This has the effect of correctly determining the end.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a first embodiment.

FIG. 2 is an overall view of an evaluation device.

FIG. 3 is a circuit diagram of a subprogram end determination circuit according to a second embodiment;

FIG. 4 is a supplementary diagram of FIG. 3;

FIG. 5 is a timing chart of the circuit of FIG. 3;

FIG. 6 is an overall flowchart of a third embodiment.

FIG. 7 is a flowchart of a subprogram end determination according to the third embodiment;

FIG. 8 is a flowchart for determining a RET instruction according to the third embodiment;

FIG. 9 is an explanatory diagram of basic processing of a conventional technique.

FIG. 10 shows a program example when a real-time OS is not used.

11 is a schematic diagram of a subprogram calling process by the program of FIG.

And FIG. 12 is a circuit diagram of a sub-program end determination circuit according to the related art.

13 is a timing chart of the circuit in FIG.

FIG. 14 shows an example of a program when a real-time OS is used.

FIG. 15 is a schematic diagram of task switching by the program of FIG. 14;

FIG. 16 is a flowchart of TASK_A processing of the program in FIG. 14;

FIG. 17 is a flowchart of TASK_B processing of the program in FIG. 14;

FIG. 18 shows a change in the stack of TASK_A in the program of FIG.

FIG. 19 shows a change in the stack of TASK_B in the program of FIG.

[Explanation of symbols]

1, 6, 8, flip-flop circuit 2, OR circuit 3, 16-input NAND circuit 4, EXNOR circuit 5, 16-bit latch circuit 7, NOR circuit 9, supervisor interrupt request terminal 10, step execution control terminal 11, CALL strobe Terminal 12, RET strobe terminal 13, stack pointer output terminal 14, 8-input OR circuit 15, inverter 16, up / down counter 100, debugged programs 101, 102, subprogram 103, stack pointer address value holding means 104, stack pointer Value comparison means 105, stack pointer address value output signal 106, match signal 107, CALL instruction 108 of the program to be debugged, instruction 109 of the subprogram, CALL and RET of the program to be debugged
Non-instruction instruction 110, evaluation processor 111, step execution control means 112, instruction execution processing 113, processing of checking flag state of step execution control means 114, processing of checking instruction execution result state 200, program evaluation device 201, sub Program end determination circuit 202, central processing unit, 203, control program RAM 204, control program ROM 205, evaluation processor 206, supervisor program RAM 207, supervisor program ROM 208, debug program RAM 209, debug program Program ROM 210-212, various buses 213, reset signal 214, step execution control signal 215, various control signals 216, target system 217, evaluation processor and target system Of various bus 218, host computer 219~222, I / O port

Claims (5)

(57) [Claims] 1. An evaluation method of a program in which a second program is inserted in an instruction processing flow by a first program, wherein an address value of a stack pointer when an instruction for calling the second program is executed. A program evaluation method for comparing the stored address value of the stack pointer with the address value of the stack pointer in subsequent instruction execution, and detecting the end of the execution of the second program when the two match. . 2. A method for evaluating a program having first and second programs, wherein the first program has a call instruction for calling the second program, wherein the call in the first program is performed. When the instruction is detected, the address value of the stack pointer at that time is held in the execution process of the call instruction, and when executing the instruction to call the third program further in the execution of the second program, the stack pointer And comparing the address value of the stack pointer with the address value of the held stack pointer in executing the instructions of the second and third programs including the call instruction of the third program, A program evaluation for judging the end of the execution of the second program when both match. Method. 3. A program comprising a plurality of programs, wherein a first program has a process for calling a second program, and an address value for outputting an address value of a stack pointer which is changed by execution of the program. An output unit, an address value holding unit that holds an address value of a stack pointer output from the address value output unit, and an address value of the stack pointer held by the address value holding unit and the execution of the second program. An address value comparing means for comparing the changed address value of the stack pointer with an address value of the changed stack pointer, wherein the address value holding means stores a stack pointer at the time of calling the second program in the first program. Address value is retained,
A program evaluation device for detecting the end of execution of the second program when the address value of the stored stack pointer matches the address value of the changed stack pointer in the address value comparing means. 4. A program evaluation apparatus comprising: a debugged program to be evaluated; storage means for storing the debugged program; and an evaluation processor for executing the debugged program. The evaluation processor comprises a plurality of subprograms, wherein the evaluation processor includes a control signal indicating execution of a subprogram call instruction of the debugged program, and address value information indicating an address value of a stack pointer that changes when the debugged program instruction is executed. A flip-flop set by the control signal; an address value holding circuit for holding and outputting the address value information when the flip-flop set signal is first generated; The changing address value information and the address Compares the output of less value holding circuit, an address value comparison circuit for generating a No. one match signal when they match, said the generation of said coincidence signal
A program evaluation device for detecting the end of execution of a subprogram. 5. The flip-flop according to claim 1, wherein the address value holding circuit comprises a flip-flop.
If the flop is a first flip-flop, the control
Between signal and set signal of the first flip-flop
A first logical product circuit for calculating logical product, and the first logical product circuit
A second flip-flop set by the output of
According to the set signal of the second flip-flop,
Consists of a latch circuit that latches and outputs address value information
The address value comparison circuit is configured to store the address value information
And the corresponding bit between the output of the latch circuit and
The number of bits of the address value of the stack pointer
EXCLUSIVE-OR circuit and output of said exclusive-OR circuit
And a second AND circuit that takes the logical product of
5. The program evaluation device according to claim 4, wherein: