JPH0342734A - Automatic debugging system for hardware - Google Patents

Abstract

PURPOSE:To read correct data from a correct value storage area, to automatically refer answer data, and to reduce manhour and the cost of a list by outputting a correct value read signal from a pseudo control part. CONSTITUTION:The correct value is read from the correct value storage area 14 by the correct value reading signal 18 included in control data consisting of control information, address information and data information, and the correct value is accumulated in register 8 in a reference circuit 7. Here, a tested circuit 17 returns a signal informing a pseudo controller 1 of the reception of control data, namely, the answer signal 19, and simultaneously returns answer data. Then, the reference circuit 7 refers correct value data accumulated in the register 8 and answer data by setting the answer signal 19 as a trigger. When they are correct, subsequent control data are sequentially executed. When they are dissident, an error is reported and a system is terminated.

Description

[Detailed description of the invention] [Field of use in sedentary work] The present invention relates to a hardware automatic debugging method.

[Conventional technology]

Traditionally, the hardware test method outputs test results in a list and checks the correct answer values against the list in order according to the test items. Therefore, as the number of test items increases, the number of children on the list increases, it takes time to output the list, and the cost of the list increases. At the same time, it also has the disadvantage of requiring a large amount of man-hours to perform analysis according to the test items.

[Problem that the invention seeks to solve]

The problem to be solved by the present invention, in other words, the purpose of the present invention is to provide a complete hardware automatic testing system that improves the above drawbacks by automatically comparing the test result data with the correct value. .

[Means to solve all problems]

The automatic hardware debugging method of the present invention creates a software model of the circuit whose block has been stolen by a processor, main memory, control circuit, and input/output circuit and the circuit under test on a computer, and controls the olfactory circuit under test by the processor. Hardware automatic Tebag Manshiki LIc'J? Then, the circuit under test is operated on the computer according to the contents of the control program storage memory that stores the control program of the processor, and the memory contents are read from the correct value storage memory area in response to the correct value read signal.
This is realized by automatically comparing the execution result of the first circuit under test with the correct value.

〔Example〕

Next, the present invention will be explained with reference to four aspects.

FIG. 1 is a block diagram showing an embodiment of the present invention functionally representing the contents described in software. In the figure, the pseudo control unit @1 has a control unit 2, a timing control unit 3, a control program storage memory unit 4, a bus interface unit 5, and a collation circuit 7, and a main memory device 10 has a storage unit 11.
It has a control unit 15 and a bus interface @16.

What is the storage part 11? d light data area 12 - 1 data area 13 and positive! Ili direct data area 14. The enclosed circuit under test 17 is connected to the pseudo control device 1 and the main memory device 10 via the processor bus 9.

The control unit 2 is immediately activated by the activation signal 6, and the control unit 2 is activated immediately. i11 part 2
By outputting a control signal from the timing controller 3 to the control program storage memory section 4, the control data stored in the control program storage memory section 4 is output. This control data is divided into each part of control information, address information, and data information, and is applied to the bus interface section 5, the V processor bus 9, the test circuit 17, and the saving circuit 17. The circuit under test 17 executes a functional test using this control data. In addition, the correct value is read out from the correct value storage area 14 by the correct value readout signal 18 included in this control data, and stored in the register 8 in the verification circuit 7 (c, , 1.).

Here, a signal to be sent to the business pseudo control device 1 that has received the control data of the circuit under test 17, ie, θ, is also an answer signal 1.
Since the answer data is sent at the same time as 9 is returned, this un-'j"-Gjl
Register 8 in g457 is checked using t9 as a trigger.
Correct value data stored in and answer Boolean k matching circuit 71
If the answer is correct, the next control data is sequentially executed. If there is a mismatch, an error is reported and the process ends.

〔Effect of the invention〕

As explained above, according to the present invention, a circuit and a correct value storage area are set up on a computer, and by outputting a correct value readout signal from the pseudo control section, correct answer data is read from the correct value storage area and answer data is automatically generated. This has the effect of eliminating the need for manual checking and reducing the total cost of man-hour buttons and lists.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Pseudo control device, 2...Control unit,
4... Control program storage memory section, 5...
. . . Bus interface section, 7 . . . Verification circuit, 9 . . . Processor 5-bus, 10 .
...Storage unit, 14...Correct value data area, 1
7...Circuit under test, 18...Correct value read signal, 19...Answer signal.

Claims (1)

[Claims] In a hardware debugging method in which a circuit configured as a block consisting of a processor, a main memory, a control circuit, and an input/output circuit and a circuit under test are made into a software model on a computer and the processor controls/controls the circuit under test, a control program for the processor is provided. operating the circuit under test on the computer according to the contents of a control program storage memory storing the above, and reading the memory contents from the correct value storage memory area in response to a correct value read signal;
An automatic hardware debugging method characterized in that the execution result of the circuit under test is automatically compared with the correct value.