JP2525393B2 - Logic simulation test coverage method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a logic simulation, and particularly to a logic simulation test coverage suitable for efficiently performing re-verification of each signal accompanying a logic change of a logic circuit. Regarding the scheme.

[Conventional technology]

Generally, in the development of an information processing device, the logic verification of the information processing device is performed using a test program by a logic simulation, and when a logic defect is extracted, the logic is changed and the verification is performed again using the test program. . On the other hand, as the information processing apparatus (logic circuit) becomes larger in scale, the computer time required for the logic simulation is also increasing, and there is a demand for a test coverage method for efficiently performing reverification due to logic changes and the like.

Conventionally, as a test coverage method for logic simulation, as described in, for example, Japanese Patent Laid-Open No. 61-127042, a change in signal state is extracted from the execution result of logic simulation, and each signal identification name of a logic circuit and its operation count It is known that a correspondence table of (1) is created to grasp the operation range and the logic simulation of an untested portion etc. is efficiently performed.

[Problems to be solved by the invention]

In the above-mentioned conventional technology, in the re-verification using the test program accompanying the logic change at the time of logic simulation, no consideration is given to what kind of test program identification name is implemented, and the re-verification accompanying the logic change can be performed efficiently. There was a problem that it was not possible to easily understand what was the minimum test program identification name for execution.

An object of the present invention is to provide a test coverage method of logic simulation which can easily grasp a minimum test program identification name to be re-verified due to a logic change and efficiently perform re-verification using a test program. Especially.

[Means for solving problems]

The above-mentioned objects are storage means for storing information indicating the signal identification name of each logic circuit and the number of times the signal has been operated, as well as information about the test program identification name that operated the signal, and the signal identification output as a result of the logic simulation. A means for updating the information indicating the number of operations in the storage means based on the information indicating the signal change for each name, and a means for storing the information indicating the test program identification name output as a result of the logic simulation in the storage means. It is achieved by providing and.

[Work]

As the result of the logic simulation, the name of the test program used for the simulation and the signal name information operated by the test program are output. As a result, the coverage system stores the test program identification name in signal name units based on the operated signal name information. As a result, the number of test programs executed during reverification can be minimized, and efficient reverification can be performed.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a general flow chart of an embodiment of a test coverage system according to the present invention. In the logic simulation 11, the gate logic file 9 and the test program file 10 are input, and the simulation result file 12 is output. In FIG. 1, a part surrounded by a dotted line is a range relevant to the present invention, and will be described below.

In the coverage check information creation processing 1, the coverage check information file 16 is created from the signal information file 8. In the optimum test program information creation processing 2, the optimum test program information file is output from the signal information file 8.
Create 15. In the simulation result information analysis processing 3, the simulation result file 12 which is the output of the logic simulation 11 is input, and the trace information file 13 is created. In the test program information analysis processing 4, the simulation execution test program information file 14 is created by using the simulation result file 12 as an input. In the coverage check information update processing 5, the trace information file 13 and the coverage check information file 16 are matched, and if there is an operation in the matching signal name, the value 1 is added to the number of operations of the corresponding item in the coverage check information file 16. And store. In the optimum test program information update processing 6, the information of the optimum test program information file 15 and the coverage check information file 16
The update test information and the test program name in the simulation execution test program information file 14 are used to update the optimum test program name at the time of reverification. In the coverage check information / optimum test program information display output processing 7, the data of the coverage check information file 16 and the optimum test program information file 15 is displayed and output to the terminal device 17 and the printing device 18.

Every time the logic simulation 11 is performed, the coverage check information file 16 is updated, the simulation execution test program information file 14 is created, and the optimum test program information file 15 is updated.

FIG. 2 shows the order of each process in FIG.

FIG. 3 is a diagram for explaining the coverage check information creation processing 1. Signal name table 30 in signal information file 8
1 is stored, and in the coverage check information creation processing 1, the coverage check information file 16 is created from the signal name table 301 as follows. Each signal name 302 attached to the logic circuit is extracted from the signal name table 301 of the signal information file 8 and numbered to the signal name 302 of the coverage table 303 in the coverage check information file 16.
Store in order of 304. The number of operations 305 is such that 1 is sequentially added when the signal value of the signal name 302 changes from 0 → 1, 1 → 0, but 0 is stored as an initial value. Also, update information
306 is "1" when the number of operations 305 is updated, but 0 is stored before being updated.

FIG. 4 is a diagram for explaining the optimum test program information creation processing 2. That is, the signal name table 301 input to the signal information file 8 is input, and signal name / test program name tables for the number of signal names are created in the optimum test program information file 15. The optimum test program information file 15 will be described later.

FIG. 5 is a diagram for explaining the simulation result information analysis processing 3 and the coverage check information update processing 5.

In the simulation result information analysis processing 3, the cycle 502 of each signal name 302 is read from the simulation result table 501 stored in the simulation result file 12.
A change 0 → 1,1 → 0 in the signal value is searched for, and the signal name 302 and the presence / absence 504 of the signal name 1 are stored in the trace table 503 of the trace information file 13 for the signal name in which the change is recognized. Next, in the coverage check information update processing 5, the coverage check information file 16 is searched for the value 1 of the operation presence / absence 504 of the trace table 503 of the trace information file 13 by the signal name 302, and the coverage table 30 is searched.
The value 1 is added to the number of operations 305 of the matching signal name 302 in 3 and the update information 306 is updated to the value 1.

From the data of the coverage check information file 16 updated by the above processing, the signal having the signal name update information of 0 indicates that it is not operating, and the signal having the value of 1 indicates that it is operating.

FIG. 6 is a diagram for explaining the test program information analysis processing 4. The simulation result table 12 is the fifth
In addition to the simulation result table 501 shown in the figure, information on the test program for which the logical simulation has been performed is held, and one of them is a test program name table 601. The test program name 602 is input to the test program name table 601, and in the test program information analysis process 4, the test program name is stored in the simulation execution test program information file 14. The simulation execution test program information file 14 is the same as the test program table 601. The test program name for this verification is "TEST1".

FIG. 7 is a diagram for explaining the optimum test program information update processing 6.

Simulation execution test program information file
The test program name 602 of the test program name table 601 is stored in 14. Further, the coverage table 303 is input to the coverage check information file 16. In the optimum test program information updating process 6, the optimum test program name is extracted from the stored information of the simulation execution test program information file 14, the coverage check information file 16 and the optimum test program information file 15.

Specifically, referring to FIGS. 8 and 9, the stored information “TEST
The optimum test program information updating process 6 will be described with the test program name traced as "1" and "TEST2" as "TEST3".

First, the test program name 602 in the test program table 601 of the simulation execution test program information file 14 is set to the optimum test program name information file 6
Signal name / test program name table 701 in the space of test program name 704 (step 90).
1). Next, the number corresponding to the value 1 of the update information 306 of the coverage table 303 of the coverage check information file 16.
304 to signal name of optimum test program information file 6 / test program name 7 of test program table 701
The value 1 is stored in each of the numbers 304 corresponding to the signal "TEST3" of 04 (step 902). Next, the number of test program names is stored in the total number of test program names 705 corresponding to each number 304 (step 903). Next, the number number is stored in the total signal number 702 corresponding to each test program name 704 (step 904). Next, the value 0 is stored in the optimum information 703 corresponding to each test program name 704 (step 905). Next, the total of the total number of signals 702 corresponding to each test program name 704 is stored (step 906).

Total number of signals corresponding to each test program name 702
It is determined whether or not the total of 0 is 0 (step 907), and if not 0, the following processing is performed.

First, the maximum value of the total number of signals 702 corresponding to each test program name 704 is searched and determined among the test program names 704 (step 908). Next, the value 1 is stored in the optimum information 703 corresponding to the test program name 704 having the maximum value of the total number of signals 702 (step 909). Next, the value 0 is stored in the total number 705 of test program names corresponding to the number 304 of each signal related to the test program name 704 having the maximum value in the total number 702 of signals corresponding to each test program name 704 (step 910). Next, the maximum number of total signals 702
The value 0 is stored in. Next, except for the test program name 704 having the maximum total number of signals 702, each test program name 704 is added to the total number of signals 702 of each test program name 704.
The number of common numbers of the number 304 of the test program name 704 and the number 304 of the respective test program names 704 of the maximum number of signals 702 is subtracted from the total number of signals 702 of 4 and stored (step 911). Next, the maximum number of total signals 702 is set to 0.
Is stored (step 912). Next, the total number of signals 702 is added to the total number of signals 702 and stored (step 913).

As a result, when re-verifying at the stage of FIG. 8, the optimum test program names are “TEST1” and “TEST2”.

The information of the coverage table 303 and the signal name / test program name table 701 is displayed and output by the coverage check information / optimum test program information display output processing 7 so that the optimum test program name at the time of reverifying the logic circuit can be grasped. It is possible to revalidate efficiently based on this information.

Further, by comparing the signal operation of the optimum test program name used in the re-verification with the signal operation of the same test program name in the optimum test program information, it is possible to automatically verify the signal operation of the logic circuit.

〔The invention's effect〕

As described above, according to the present invention, the minimum optimum test program name for operating the logic circuit can be grasped in the coverage check performed at the time of logic simulation. The simulation can be eliminated, the re-logic simulation time can be reduced, and an effective test can be effectively performed.

[Brief description of drawings]

FIG. 1 is a general flow chart of a test coverage system according to the present invention, FIG. 2 is a flow chart showing a processing procedure in FIG. 1, FIG. 3 is a view for explaining a coverage check information creating process, and FIG. FIG. 5 is a diagram for explaining the optimum test program information creation process, FIG. 5 is a diagram for explaining the simulation result information analysis process and coverage check information update process, and FIG. 6 is a diagram for explaining the test program information analysis process. FIG. 7 is a diagram for explaining the optimum test program information updating process, FIG. 8 is a diagram showing a transition of the process from FIG. 7, and FIG. 9 is a flowchart of the optimum test program information updating process. 1 ... Coverage check information creation process, 2 ... Optimal test program information creation process, 3 ... Simulation result information analysis process, 4 ... Test program information analysis process, 5 ... Coverage check information update process, 6 ... Optimal Test program information update processing, 7 ... Coverage check information / optimal test program information display output processing, 8 ... Signal information file, 9 ... Gate logic file,
10 …… Test program file, 11 …… Logical simulation, 12 …… Simulation result file, 13 …… Trace information file, 14 …… Simulation execution test program information, 15
…… Optimal test program information file, 16 …… Coverage check information file, 17 …… Terminal device, 18 …… Printing device.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-63-39051 (JP, A) JP-A-63-30941 (JP, A)

Claims (1)

(57) [Claims] 1. An identification name of each signal of a logic circuit (signal identification name)
And a storage means for storing the number of times of operation and the identification name of the test program that operates each signal (test program identification name), and the information indicating the signal change for each signal identification name output as a result of the logic simulation. Means for updating the information representing the number of operations stored in the storage means, the test program identification name output as a result of the logic simulation, and the test program identification in the storage means based on the number of operations of each signal identification name. Of the logic simulation having means for updating the name and means for activating each signal at the time of reverification and determining an optimum test program identification name corresponding to the minimum number of test programs for operating all signals. Test coverage method.