JPH07306881A - Analysis support device for logical siomulation - Google Patents

Abstract

PURPOSE:To enable anybody to easily analyze the operation of a logic circuit by retrieving and displaying all signal propagation paths from a start point to an end point once the start point and end point of a signal line of the logic circuit to be analyzed are specified, and displaying signal variation of the logical simulation result of the displayed signal line. CONSTITUTION:Start point information 102 and end point information 103 are specified respectively. The specified information 102 and information 103 are registered in a start point table 1081 and an end point table 1082. To retrieve a logic circuit having the registered end point information 103, logical circuit information 104 for each circuit is read out of a logic circuit file 109 to a table A1084-1, and an output signal line name and the registered end point information 103 are compared with each other. A logic circuit which is present at the circuit position where the output signal line name and the registered end point information 103 match each other is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation result analysis support device, and more particularly to a large scale integrated circuit (Large Scale Integrated Circuit).
Scale integration: hereinafter referred to as LSI), which is related to a logic simulation result analysis support device required for development.

[0002]

2. Description of the Related Art Conventionally, as a logic simulation result analysis method, for example, a technique disclosed in Japanese Patent Application Laid-Open No. 3-78087 (Title of Invention: Logic Simulation Result Observation Device) is known.

In the logic simulation result observing device disclosed in the above-mentioned Japanese Patent Laid-Open No. 3-78087, when observing the logic simulation execution result, the observer first observes in the logic circuit to be observed on the graphic display. It specifies the position.

Based on the specified observation position information,
A logic circuit diagram including a signal waveform and a signal line of a logic simulation execution result prepared in advance at the designated observation position is displayed on the same screen.

At this time, the logic circuit diagram is obliquely displayed, and the logic circuit diagram at the designated observation position and the signal waveform of the logic simulation execution result are displayed in correspondence with each other by a dotted line. It has become.

Therefore, a technician carrying out the analysis work observes the displayed logic circuit diagram and signal waveform and examines whether or not each logic circuit is operating properly.

[0007]

However, in the above-mentioned conventional technique, the positions to be observed in the logic circuit have to be manually specified one by one, and the failure analysis cannot be efficiently performed. There was a problem.

In particular, the analysis work in the LSI development stage is often carried out by a person other than the logic circuit designer who is not familiar with the operation of the logic circuit, and whether or not the displayed signal waveform is correct is determined. There is a problem that it takes a lot of time to make a determination.

An object of the present invention is to provide a logic simulation result analysis support device that enables anyone to easily and efficiently perform analysis work.

[0010]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, first storage means for storing configuration information of a signal propagation path composed of a plurality of logic circuits and all signal lines connecting the plurality of logic circuits, and logic of the signal propagation path. Second storage means for storing a simulation execution result as a signal change of the signal propagation path, designating means for designating a start point and an end point of a signal line of the logic circuit, and the designating means designated by the designating means. Search means for searching all signal propagation paths from the start point to the end point,
First display means for displaying a signal propagation path including all signal line names searched by the search means, and a signal change of a logic simulation execution result in a plurality of signal lines displayed by the first display means. The second display means for displaying is provided.

Further, the logic simulation result analysis support device is provided with a duplicate display prohibiting means that does not duplicately display the signal line names already displayed when displaying the plurality of signal line names searched by the searching means. It was done like this.

[0013]

According to the above means, when the logic simulation execution result is analyzed, when the start point and the end point of the signal line of the analysis target logic circuit are designated, the logic simulation result analysis support device causes the designated start. All signal propagation paths from the point to the end point are searched, the signal propagation paths including all the searched signal line names are displayed, and the signal change of the logic simulation execution result in the displayed plurality of signal lines Is displayed on the same screen, anyone can easily analyze the operation of the logic circuit.

Further, since the duplicated display prohibiting means does not duplicately display the already displayed signal line names, it is possible to efficiently analyze the logic simulation execution result.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of an embodiment of a logic simulation execution result analysis support apparatus according to the present invention.

In FIG. 1, 101 is a console display for inputting / outputting user data, and 102 and 103 are
It is start point information and end point information necessary for displaying the signal propagation path of the analysis target logic circuit, and is designated by the user.

Reference numeral 104 is logic circuit information existing in the searched signal propagation path, 105 is signal line name information indicating the signal line name of the searched signal propagation path, and 106 is signal waveform information for the signal line of the searched signal propagation path. is there.

As can be seen from the arrows shown in FIG. 1, the start point information 102 and the end point information 1
03 is information that the user inputs using the console display 101, and the logic circuit information 10
4, the signal line name information 105 and the signal waveform information 106 are
This is information output (displayed) on the console display 101.

Reference numeral 107 denotes an input / output device for controlling input / output of the various information (102 to 106) from the console display 101, and 108 denotes signals from the start point information 102 and end point information 103 read by the input / output device 107. It is a signal line name search device for searching a signal line of a propagation path.

In the signal line name search device 108, a start point table 1081, an end point table 1082, a search signal storage table 1083, a read table A1084-1 and a read table B10.
84-2 is provided.

Reference numeral 109 is a logic circuit file storing the logic circuit information 104, and 110 is a signal line name search device 108.
A signal line name storage device for registering the signal line name retrieved in 1.
Reference numeral 11 is a system control device for checking the duplication of the retrieved signal line name and reading the logic simulation execution result information for the retrieved signal line name.

Reference numeral 112 is a simulation result file storing logic simulation execution result information, which stores signal line name information 105 and signal waveform information 106.

FIG. 2 is a circuit diagram showing an example of a logic circuit to be subjected to logic simulation.

In FIG. 2, reference numeral 200 denotes a display screen A of the console display 101, on which a logic circuit to be subjected to logic simulation is displayed.

On this display screen A200, a logic circuit to be simulated is displayed, and 201 and 205 are ANs.
D gates, 202 and 206 are OR gates, 203 and 20
Reference numeral 4 is a flip-flop circuit element.

Further, 207 to 210 are AND gates 20.
1, the input signal line of the OR gate 202 (S0, S1, S
2, S3), and 211 is the input timing signal line S4 of the flip-flop circuit elements 203 and 204.

Reference numerals 212 and 213 denote AND gates 201 and O, respectively.
The output signal lines (S5, S6) of the R gate 202 and the input signal lines of the flip-flop circuit elements 203 and 204 are simultaneously formed. Similarly, the output signal lines 214 and 215 of the flip-flop circuit elements 203 and 204 (S7, S8)
At the same time, AND gate 205 and OR gate 206
Is also the input signal line of.

Further, 216 and 217 are AND gates 20.
5, output signal lines (S9, S10) of the OR gate 206.

Symbols (G1) of various logic circuits shown in FIG.
To G6) show the circuit positions of various logic circuits in the circuit diagram.

FIG. 3 is a diagram showing an example of a display screen of the simulation result analysis support device for displaying the simulation execution result of the logic circuit to be executed in the logic simulation shown in FIG.

In FIG. 3, reference numeral 300 denotes a display screen B of the console display 101, on which the simulation execution result of the logic circuit targeted for logic simulation shown in FIG. 2 is displayed as a signal waveform.

In the display screen B300, the input data value 302 of the signal line corresponding to the execution time 301 of the logic simulation, the expected output value 303 of the signal propagation path for the input data value 302, and the signal propagation path for the input data value 302 are displayed. The output value 304 of the logic simulation execution result and the output value 305 of the failure analysis result are displayed as a signal waveform.

Since the display screen A200 and the display screen B300 shown in FIGS. 2 and 3 are displayed on the same screen, the user should observe the analysis target logic circuit and the simulation execution result corresponding thereto. Thus, the operation analysis of the logic circuit can be easily performed.

The operation of the logic simulation execution result support apparatus of this embodiment will be described below with reference to FIGS.

As shown in FIG. 3, first, the expected output value 30
3 is compared with the output value 304 of the execution result, in the logic simulation execution time 301 in the output signal line name S10 (217), the time 3 between 100 and 120 ns
06 (the hatched portion surrounded by the broken line in FIG. 3), the expected output value 303 and the output value 304 of the execution result do not match, indicating that there is a logic circuit that does not operate as designed.

Therefore, for failure analysis, the input signal line S2 (209) shown in FIG.
By designating the output signal line S10 (217) shown in FIG. 3, which is the end point of the analysis, all the signal propagation paths of the signal line are automatically searched, and the searched signal propagation path and the signal propagation The signal waveform, which is the result of the simulation of the path, is displayed on the same screen.

Similarly, by designating the input signal line S3 (210) shown in FIG. 3 as the start point and the same output signal line S10 (217) as the end point, all signal propagation paths of the signal line are searched. The searched signal propagation path and the signal waveform which is the simulation execution result of the signal propagation path are displayed on the same screen.

At this time, if the searched signal line overlaps with the signal line already searched and displayed, only the signal lines that do not overlap are displayed.

The result of the failure analysis is shown as 30.
5 and the start point of the failure analysis is the broken line portion 307.
(S2 and S3 shown in FIGS. 2 and 3), the end point is shown by a broken line portion 309 (S10 shown in FIGS. 2 and 3), and the searched output signal line is shown by a broken line portion 308 (S6 and S8 shown in FIGS. 2 and 3). ).

In this way, by designating the start point and end point of the signal line in the logic circuit, the signal waveform of the simulation execution result in all the propagation paths of the signal line is automatically displayed. Even a person other than the designer can easily grasp the quality of the propagation path of the signal line, so that an efficient failure analysis can be performed.

FIG. 4 is an explanatory diagram for explaining the automatic search processing of the signal propagation path of the present embodiment.

In FIG. 4, 109 is a logic circuit file in which logic circuit information 104 is stored.

Reference numeral 1084-1 is a read table A,
As the logic circuit information 104 read from the logic circuit file 109, the circuit position 4011 and the circuit name 4012
And input signal line name 4013 and output signal line name 4014
Is described.

Reference numeral 1082 is an end point table in which the end point information 103 input by the user is registered.

Reference numerals 402, 403, 404 and 405 are comparison circuits.

Reference numeral 1083 is a search signal storage table for storing the logic circuit information 104 of the searched signal propagation path, and 108.
4-2 is a read table B.

Reference numeral 1081 is a start point table in which the start point information 102 input by the user is registered.

A signal line name storage device 110 stores the logic circuit information 104 including the searched signal line.

An outline of the automatic search processing and automatic registration processing of the signal propagation path will be described below with reference to FIG.

As shown in FIG. 4, first, the logic circuit information 104 stored in the logic circuit file 109 is read into the read table A 1084-1 for each circuit.

Next, the output signal line name 4014 in the read logic circuit information 104 and the end point table 1
The comparison circuit 403 compares the end point information 103 registered in 082 with the comparison circuit 403. If the results do not match, the logic circuit information 104 for the next one circuit is read from the logic circuit file 109.

When the results match, the logic circuit information 104 of the read table A 1084-1 is stored in the search signal storage table 1083, and at the same time, the input signal line name 4 of the read table A 1084-1 is searched for the next search.
013 is stored in the end point table 1082, and then the start point information 102 designated by the user and this input signal line name 4013 are compared by the comparison circuit 402,
If the results do not match, the reading of the logic circuit information 104 is continued, but if the results match, the logic circuit information 104
Ends reading.

When the reading of the logic circuit information 104 is completed, next, the logic circuit information 104 of the search result stored in the search signal storage table 1083 is read into the read table B 1084-2 for each circuit.

Then, the read table B1084-2
Input signal line name 4013 of the logic circuit information 104 for one circuit read out to the start point table 1081
The comparison circuit 404 compares the start point information 102 registered in No. 1 with the result, and if the results do not match, the logic circuit information 104 for the next one circuit is retrieved signal storage table 1083.
From the read table B1084-2.

If the results match, the logic circuit information 104 of the read table B1084-2 is stored in the signal line name storage device 110, and at the same time, the next search is performed.
Output signal line name 401 of read table B1084-2
4 is registered in the start point table 1081 as a new input signal line, and then the end point information 103 designated by the user and this output signal line name 4014 are compared by the comparison circuit 405, and if the results do not match. The logic circuit information 104 is continuously read, but when the results match, the logic circuit information 104 is read and the signal propagation path automatic search processing and automatic registration processing are ended.

FIG. 5 is a diagram showing the result of executing the automatic search processing and the automatic registration processing of the signal propagation path according to the procedure of FIG. 4 by taking the circuit diagram of FIG. 2 as an example.

FIG. 6 is a flow chart showing the procedure of the automatic search processing of the signal propagation path of this embodiment.

FIG. 7 is a flow chart showing the procedure of the automatic registration processing of the signal propagation path of this embodiment.

The automatic search processing and automatic registration processing of the signal propagation path according to the present embodiment will be specifically described below with reference to FIGS. 5, 6 and 7.

In the automatic search processing of the signal propagation path, as shown in FIG.
“S2” is designated as “”, and “S10” is designated as the endpoint information 103 (step 601).

The designated "S2" and "S10" are
It is registered in the start point table 1081 and the end point table 1082, respectively (step 6).
02).

Then, the registered endpoint information 1
In order to search for the logic circuit having "S10" which is 03, the logic circuit information 104 for each circuit is read from the logic circuit file 109 to the read table A1084-1 (step 603) and registered as the output signal line name 4014. The end point information 103 ("S10") is compared (step 604).

As a result of the comparison, as shown in FIG. 5, the output signal line name 4014 and the registered endpoint information 103 are displayed.
The logic circuit G6 existing in the circuit position 4011 where ((S10)) matches is obtained.

Next, input signal line name 4 of this logic circuit G6
013 (S7 and S8 shown in FIG. 5) and start point information 1 registered in the start point table 1081.
02 ("S2") is compared (step 605).

In this case, there is a mismatch (step 6
05: No match), this input signal line name 4013 (S7 and S8 shown in FIG. 5) is registered in the endpoint table 1082 as a new output signal line name 4014 (step 6).
07).

The input signal line name 4013 (see FIG.
The logic circuit information 104 including S7 and S8 shown in FIG. 10 is stored in the search signal storage table 1083 (step 60).
8).

Then, the logic circuit information 10 for the next one circuit
4 is read from the logic circuit file 109 (step 6)
09).

Then, the input signal line name 4013 (S7, S8 shown in FIG. 5) newly registered in step 607 is compared with the output signal line name 4014 of the read logic circuit information 104 (step 610).

In FIG. 5, the logic circuit G3 whose output signal line name 4014 is "S7" whose comparison results are the same, and "S8".
The two logic circuits of the logic circuit G4 having the output signal line name 4014 are searched (step 610: coincidence).

Then, returning to step 605, the start point information 102 ("S2") registered in the start point table 1081 and the input signal line name 4013 of the logic circuits G3 and G4 (S4 in FIG. 5, S4, S
5, S6).

In this case, since they do not match (step 605: mismatch), the input signal line names 4013 (S4, S5, S6 shown in FIG. 5) of the logic circuits G3 and G4 are
The new output signal line name 4014 is registered in the endpoint table 1082 (step 607).

Then, this mismatched input signal line name 401
3 (S4, S5, S6 shown in FIG. 5) is stored in the search signal storage table 1083 (step 608).

Then, the logic circuit information 10 for the next one circuit
4 is read from the logic circuit file 109 (step 609), and the output signal line name 4014 of the read logic circuit information 104 and the end point table 1082 as a new output signal line name 4014 in step 607.
The input signal line name 4013 registered in (S4 shown in FIG. 5,
S5 and S6) are compared (step 610).

Here, "S4" is output signal line name 4014.
Since there is no logic circuit that corresponds to “S5”, which is “not applicable” and the comparison result matches, the output signal line name 401
4 and output signal line name 40
The logic circuit G2 to be set to 14 is searched (step 61).
0: match).

Then, returning to step 605, the input signal line name 4013 of the logic circuit G1 (S0, S1 shown in FIG. 5).
And the input signal line name 4013 (S2, S3 shown in FIG. 5) of the logic circuit G2 is compared with the start point information 102 (“S2”) designated by the user (step 60).
5).

Here, the input signal line name 40 of the logic circuit G2
13 (S2, S3 shown in FIG. 5) matches the start point information 102 designated by the user, “S2” (step 605: match), the series of comparison results indicates that
The logic circuit G2 in which the input signal line name 4013 and the output signal line name 4014 match is stored in the search signal storage table 1083 (step 606), and the automatic search process of the signal propagation circuit is ended.

Next, the automatic registration process of the logic circuit information stored in the search signal storage table after the automatic search process is completed will be described.

As shown in FIG. 7, first, the logic circuit information 104 for one circuit of the logic circuit information 104 stored in the search signal storage table 1083 is read out from the table B1.
084-2 is read (step 701), and the start point information 102 (“S2” shown in FIG. 5) registered in the start point table 1081 is compared with the input signal line name 4013 of the read logic circuit information 104. (Step 702).

If they do not match (step 702: mismatch), the process returns to step 701 to read the logic circuit information 104 for the next one circuit and compare it with the input signal line name 4013.

If they match (step 702: match), the output signal line name 4014 (in this case, "S6") of the logic circuit having the matched input signal line name 4013 and the end point information 103 (specified by the user) "S10") is compared (step 703).

In this case, they do not match (step 70).
3: The output signal line names 4014 (“S6” shown in FIG. 5) that do not match) are newly registered as the input signal line name 4013 in the start point table 1081 (step 705).

Then, this disagreement output signal line name 401
4 (“S6” shown in FIG. 5) having logic circuit information 104
Is stored in the signal line name storage device 506 (step 70).
6).

Next, the logic circuit information 104 for the next one circuit is read from the search signal storage table 1083 (step 707).

Then, in step 705, the output signal line name 4014 ("S" shown in FIG. 5 is newly registered as the input signal line name 4013 in the start point table 1081.
6 ") is compared with the input signal line name 4013 (" S6, S4 "in this case) of the read logic circuit information 104 (step 708).

In this case, they match each other (step 70
8: Matching), and then returning to step 703, the output signal line name 4 of the logic circuit having the matching input signal line name 4013
014 (in this case, "S8") is compared with the endpoint information 103 ("S10") specified by the user (step 703).

This is a mismatch (step 70).
3: No match), the output signal line name 4014 (“S8” in this case) of this mismatch is newly added to the input signal line name 4013.
Is registered in the start point table 1081 (step 705).

Then, the output signal line name 401 of this disagreement
4 (“S8” shown in FIG. 5) having logic circuit information 104
Is stored in the signal line name storage device 506 (step 70).
6).

Next, the logic circuit information 104 for the next one circuit is read from the search signal storage table 1083 (step 707).

Then, in step 705, the output signal line name 4014 newly registered as the input signal line name 4013 in the start point table 1081 (see "S" in FIG. 5).
8 ") is compared with the input signal line name 4013 (in this case," S7 "," S8 ") of the read logic circuit information 104 (step 708).

In this case, since they match (step 708: match), the process returns to step 703, and the output signal line name 4014 of the logic circuit having the matched input signal line name 4013 (in this case, " S10 ") is compared with the end point information 103 (" S10 ") designated by the user (step 703).

This also matches (step 70).
3: Matching), the logic circuit information 104 having the input signal line name 4013 and the output signal line name 4014 is stored in the signal line name storage device 110 (step 704), and the automatic registration process ends.

Through the series of processes described above, all the signal propagation paths between them are searched by simply designating the start point and end point of the logic circuit to be analyzed.

FIG. 8 is a flowchart showing the overall processing procedure of this embodiment.

The overall processing flow of this embodiment will be described below with reference to FIG.

First, as shown in FIG. 8, first, start point information 102 and end point information 103 for searching a signal propagation path of a logic circuit are input from a console display (not shown) (step 8).
01).

Next, the input start point information 1
02 and the end point information 103 are searched for a signal line name from the logic circuit file 109 (step 802), and the logic circuit information 104 including the searched signal line name is registered in the signal line name storage device 110. (Step 803).

After the search is completed, it is determined whether or not there is a signal line name that duplicates the previously searched signal line name (step 804). If there is no duplicate signal line name (step 804: Yes),
The process moves to the next step.

If there is an overlapping signal line name (step 804: No), the overlapping signal line name is deleted from the signal line name storage device 110 (step 805), and the process proceeds to the next step.

Next, for the signal line name newly registered in the signal line name storage device 110, the logic circuit information 109 from the logic circuit file 109 and the signal line name information 105 and the signal waveform information 10 from the simulation result file 112.
6 is read (step 806).

Then, various information read in step 806 is displayed on the console display (step 807), and the result of the logic simulation execution is analyzed (step 808).

Then, it is judged whether or not the analysis of the logic simulation execution result needs to be ended (step 809), and if the result analysis is completed (step 809: Yes), the process is ended.

When the information for the result analysis is insufficient (step 809: No), the step 8 is executed again.
The process is repeated from 01.

As can be seen from the description of this embodiment,
By specifying the start point and end point of the analysis target logic circuit, all the signal propagation paths between them and the signal waveform of the logic simulation execution result are displayed on the same screen, so anyone can easily execute the logic simulation execution result. Can be analyzed.

Although the present invention has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor.

[0106]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

When the analysis result of the logical simulation is analyzed, the range to be analyzed is simply designated as the start point and the end point, and all the signal propagation paths in the designated range are automatically searched, and the searched signal propagation path is searched. Since the signal waveform of the simulation execution result of the signal propagation path is displayed on the same screen, anyone can analyze the operation of the logic circuit easily and efficiently.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of a logic simulation execution result analysis support device according to the present invention.

FIG. 2 is a circuit diagram showing a simulation target logic circuit used in this embodiment.

FIG. 3 is a diagram showing a signal change of a logic circuit to be simulated in this embodiment.

FIG. 4 is an explanatory diagram for explaining an outline of automatic search processing of a signal propagation path according to the present embodiment.

FIG. 5 is an explanatory diagram for specifically explaining a result of executing automatic search processing and automatic registration processing of a signal propagation path according to the present embodiment.

FIG. 6 is a flowchart showing a procedure of automatic search processing according to the present embodiment.

FIG. 7 is a flowchart showing a procedure of automatic registration processing according to the present embodiment.

FIG. 8 is a flowchart showing the overall processing procedure of this embodiment.

[Explanation of symbols]

101 ... Console display, 102 ... Start point information, 103 ... End point information, 104 ... Logic circuit information, 105 ... Signal line name information, 106 Signal waveform information, 107 ... Input / output device, 108 ... Signal line name searching device,
109 ... Logic circuit file, 110 ... Signal line name storage device, 111 ... System control device, 112 ... Simulation result file.

Claims (2)

[Claims] 1. A first storage means for storing configuration information of a signal propagation path composed of a plurality of logic circuits and all signal lines connecting the plurality of logic circuits, and a logic of the signal propagation path. Second storage means for storing a simulation execution result as a signal change of the signal propagation path;
Designating means for designating a start point and an end point of a signal line of the logic circuit, a searching means for searching all signal propagation paths from the start point to the end point designated by the designating means, and the searching means. A first display means for displaying a signal propagation path including all the signal line names retrieved by the first display means, and a first display means for displaying the signal change of the logic simulation execution result on the plurality of signal lines displayed by the first display means. 2. A logic simulation result analysis support device, comprising: 2 display means. 2. The logic simulation result analysis support device includes a duplicate display prohibiting means that does not duplicately display the signal line names already displayed when displaying the plurality of signal line names searched by the searching means. The logic simulation result analysis support apparatus according to claim 1, wherein