JP2000148805A - System and method for analyzing vhdl simulator and program recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce such a burden on a user that the user must rearrange VHDL(very high-speed IC hardware design language) sources by programming the arranging procedure of the sources. SOLUTION: The hierarchical order of VHDLs which are manually arranged in the conventional example is automatically analyzed 11 by making a VHDL simulator analyze the order. Since the VHDL simulator is provided with a function of basically checking syntaxes, in this case, the simulator is made to make rearranging processing 10 for rearranging VHDL sources in the hierarchical order in such a way that the simulator checks the names of individual VHDL sources and the names of the children VHDL sources (sources of lower hierarchies) of the individual VHDL sources by utilizing the function and rearranging the sources from those having no children.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VHDL simulator analyzing system, method, and program recording medium, and more particularly to a system for rearranging and analyzing VHDL sources, a method thereof, and a recording medium on which the program is recorded.

[0002]

2. Description of the Related Art Generally, VHDL is used for designing an integrated circuit.
(VHSIC Hardware Design La
nguage) is used. VHSIC is Very
High Speed Integrated Ci
Abbreviation for rcuits.

[0003] VHDL is a language for describing the operation of an integrated circuit. Analyzing whether this VHDL is correctly described in accordance with the standards of the Institute of Electrical and Electronics Engineers (IEEE) is called "analyze". This VH
The DL can have a hierarchical structure, and a plurality of VHDL sources can be connected to one module. The analyze can also check that it is connected correctly.

Conventionally, in this analysis, the user has to know the hierarchical structure of a plurality of VHDL sources and start the analysis from the lowest layer of the hierarchy. If the analysis order is wrong, an error occurs.

[0005] Originally, the user is familiar with the VHDL source created by the user. However, recently, a general-purpose VHDL source has been sold, and it is necessary to analyze a ready-made VHDL. lost. Users using off-the-shelf VHDL sources will:
It is in a state where it is necessary to read the contents of this source and check the hierarchy.

FIG. 13 shows a conventional technical design flow. As shown in the figure, conventionally, an investigation of a VHDL source A (step S121), a VHDL source B
(Step S122), the VHDL source C (step S123), and the VHDL source D (step S124), the contents of each source are read, and then the sources are rearranged (step S125) and analyzed (step S126). ) Are performed.

[0007] The VHDL can describe the movement of the LSI programmatically.
It is used for describing the function itself of I, and for logic verification for verifying how the LSI behaves.

The VHDL of the LSI is read and the L
What simulates the operation of SI is a VHDL simulator. Waveforms and logic values output from the VHDL simulator are mainly used for logic verification.

To perform a VHDL simulation, at least the following three processes are required. The first is called analysis, which checks the grammar of the written VHDL description and creates an object that can be read by the simulator. The second is to import objects created by analysis into the simulator, although the names vary depending on the simulator. The third is called a simulation, in which a simulation is performed using the data acquired in the second procedure, and the result is output as a logical value or a waveform.

In this case, of the above three operations, analysis is a problem. Here, an analysis configuration of the VHDL simulator will be described. The analysis target of the VHDL simulator here is a V
HDL source. The VHDL description can have a hierarchical structure like other programming languages.

For example, a plurality of VHDL sources A, B,
If there are C, D, E, and F, VHDL source A is VH
Utilizing DL source B and VHDL source C, VHDL source B is VHDL source D, VHDL source E, VHD
Assume that L source C wants to use VHDL source F. In this case, the VHDL source A, B, C
If it is described whether or not to use L, a hierarchical structure is established, and the VHDL source A is hierarchically located at the highest level,
There is a hierarchy in which the VHDL source B and the VHDL source C are located below the lower layer, and the VHDL source D, the VHDL source E, and the VHDL source F are located in the lowermost layer.

The analysis is performed by using a VHDL simulator, VHDL sources A, B, C, D, E, and F mentioned above.
To read the VHDL source. The point to keep in mind when reading this is that when reading the VHDL source,
The point is that you must adhere to the rule that you must read from the lower hierarchy.

[0013]

As described above, conventionally, when performing this analysis, a person who uses a VHDL simulator knows in advance the hierarchy of a plurality of VHDL sources and can read the hierarchy in any order. The VHDL source is input to the VHDL simulator while conscious of whether to do so. If the VHDL source is not the one created by yourself, a human observes the contents of the source, understands the order, and inputs the source to the VHDL simulator. In the prior art, if the person performing the simulation and the person creating the VHDL are separate and the information of the hierarchy is not available to the person performing the simulation, the VHDL
There is a disadvantage that it takes time because the person who simulates the contents of the source must investigate and understand the contents in advance. Further, at this time, there is a drawback that the person who performs the simulation necessarily needs knowledge of the HDL description in order to understand the contents of the VHDL source.

In addition, if the number of VHDL sources is as small as about 10, it can still be managed manually. However, there are disadvantages in that there are both 60 and 70 VHDL sources, and if these are rearranged by hand, considerable work time is required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has as its object to program a procedure for arranging VHDL sources so that VH can be programmed.
An object of the present invention is to provide a VHDL simulator analyzing system, an analyzing method, and a recording medium on which an analyzing program is recorded, which can reduce the burden on the user that the DL sources must be rearranged.

[0016]

An analysis system for a VHDL simulator according to the present invention is provided for inputting a plurality of VHDL sources to a simulator in an order according to a hierarchical structure thereof and analyzing whether or not the sources are correctly described. An analyzing system, comprising: a hierarchical structure analyzing means for analyzing a hierarchical structure of the VHDL source; and a rearranging means for rearranging the VHDL source according to a result of the analysis. Is input.

An analysis method of a VHDL simulator according to the present invention is an analysis method for inputting a plurality of VHDL sources to a simulator in an order according to a hierarchical structure thereof and analyzing whether or not the sources are correctly described. A hierarchical structure analyzing step of analyzing a hierarchical structure of the VHDL source;
And rearranging the DL source. The rearranged VHDL source is input to the simulator.

The recording medium on which the analyze program of the VHDL simulator according to the present invention is recorded includes a plurality of VHDs.
A recording medium storing an analyze program for inputting an L source to a simulator in an order according to its hierarchical structure and analyzing whether or not the source is correctly described, wherein the program has a hierarchical structure of the VHDL source. And a rearranging step of rearranging the VHDL sources according to the analysis result, wherein the rearranged VHDL sources are input to the simulator.

In short, in the present system, the VHDL simulator analyzes the order of the VHDL hierarchy, which has been manually arranged in the past, and performs the analysis automatically. VHD
The L simulator basically has a function to check the syntax.
Checking what kind of name the DL source has and what kind of VHDL source it has as a child (lower hierarchy source) Is performed by the simulator.

That is, this system is different from the conventional system in that VHDL sources which have been input to the VHDL simulator one by one can be input collectively one by one, and according to the hierarchy of the VHDL source. Since the rearrangement is performed automatically, the contents of the VHDL source do not need to be seen by a person.

[0021]

Next, an embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same parts as those in the other drawings are denoted by the same reference numerals.

FIG. 2 shows, by way of example, six VHDL sources A, B, C, D, E, and F, and how these layers are arranged. In FIG.
The HDL source A captures the VHDL source B and the VHDL source C, the VHDL source B stores the VHDL source D and the VHDL source E, and the VHDL source C stores the VHDL source C.
DL sources F are taken in respectively. This hierarchy is
By looking at the contents of each VHDL source A, B, C, D, E, F, the hierarchy can be checked. Therefore,
In analyzing these five sources, a human must look at all the sources in advance and understand the hierarchical structure.

The procedure in that case is shown in FIG. First, VHDL source A to VHDL source F are shown in FIG.
As shown in FIG. 9A, the order in which the sources must be inserted into the VHDL simulator is examined by the human eyes. In this case, the analysis of VHDL is
VHD must be performed from the lower hierarchy.
VHDL source B and VHDL source C before L source A, VHDL source D and VHDL before VHDL source B
HDL source E is added to VHDL source C before VHDL source C
Source F must be analyzed.

Therefore, it is necessary to input to the VHDL simulator at least in the order of J1, J2, and J3 as shown in FIG. 3B. The input order for the VHDL sources of the same order shown by the broken lines may be arbitrary. In this case, of course, the person who performs this work needs to have detailed knowledge of the syntax of VHDL because the user is looking at the VHDL source. This reordering is time-consuming and requires an understanding of the VHDL syntax. Therefore, the present system eliminates these troubles by causing the VHDL simulator to perform rearrangement.

FIG. 1 shows the rearrangement procedure. As shown in the figure, by simultaneously inputting the six VHDL sources A to F to the VHDL simulator 100, the hierarchical analysis function of the VHDL simulator 100 is used to check even the hierarchy, and the simulator 1
00, the rearrangement process 10 is automatically performed, and the analysis 11 is performed. As a result, the work performed by a person is performed by the VHDL simulator 100 with the VHDL sources A to
F only, the sorting process is also VHDL
No knowledge of the syntax is necessary.

FIG. 4 is a flowchart in the case where the rearrangement is performed manually, and FIG. 5 is a flowchart in the case where the VHDL simulator 100 performs the rearrangement.

Referring to FIG. 4, first, a plurality of VHs are manually set.
After performing the hierarchy analysis processing on the DL source (step S41), the rearrangement processing is performed (step S42). This rearranged VHDL source is processed by the VHDL simulator (step S43), and the result is obtained.

On the other hand, referring to FIG.
When the source is input to the VHDL simulator (step S50), the internal hierarchy search and rearrangement processing is automatically performed (step S51), and the result is output. That is, as shown in FIG. 6, the automatic rearrangement program is started (step S131), and then the analysis is performed (step S132).

The processing shown in FIG. 5 is specifically performed as follows. First, it is assumed that there is a VHDL source having a hierarchy as shown in FIG. In the figure, VHDL source A includes VHDL source B, and VHDL source B includes VHDL source C and VHDL
Source D is included. VHD with such a hierarchy
The L source must be reordered as shown in FIG. That is, when analyzing these sources, there are two possible analysis orders,
The order is HDL source D, VHDL source C, VHDL source B, and VHDL source A, or the order is VHDL source C, VHDL source D, VHDL source B, and VHDL source A.

For these, VHDL sources A to D
By looking at the contents of the above, the hierarchical structure can be understood, and a simulation of causing a computer to perform this is performed. In this case, it is checked what the name of each VHDL model (the object written by the VHDL source, that is, the VHDL source itself) and what kind of child it has. The model without children at that time is the lowest level model, so the order of analysis is
Be the first.

Next, in a state where the model having no child is removed, what kind of model each model has is examined again. Here, the model without children will be the next lowest model after the previous model,
This is the second analysis order.

FIG. 9 is a diagram showing an example of rearrangement of the hierarchical relation in the case of FIG. In the processing of level 1 in the drawing, the models C and D are models having no children (broken line portions in the drawing), and thus are models in the lowest layer. In the level 2 processing, the models C and D having no children at the level 1 are extracted, and a model having no children is searched. Here, since the model B is selected (the broken line portion in the figure), the model B is the next lowest model after the models C and D. Similarly, in the level 3 processing, the model that is next to the model B is the model A
(A broken line portion in the figure). Since there is no model at level 4, it is understood that model A is the highest layer.

That is, this rearrangement is performed as follows.

First, the contents of each VHDL source are searched to find out what name the VHDL source is (the name of the circuit, not the file name).

Second, the VHDL source is examined to determine what name the VHDL source has for the child.

Third, each VHDL source is provided with a level, and each VHDL source is compared with another VHDL source.
The HDL source raises the level.

Fourth, after discarding the lowest level source, return to the third task. By repeating this as many times as the number of sources, the level of each source is determined. By rearranging the sources based on this, the VHDL sources can be arranged in an appropriate order.

As described above, if there are a large number of VHDL sources, they are automatically rearranged by the computer even if the user does not look at all of them, eliminating the burden of analyzing the user's VHDL sources.

More specifically, processing as shown in the flowchart of FIG. 10 is performed. That is, first, all the VHDL sources are checked, and only the sources having a hierarchy under the VHDL source are extracted and removed from the source list (step A1). Then, a score of 1 is given to the source having no hierarchy (step S1).

Next, only the source having only the VHDL source extracted at the time point A1 in the lower hierarchy is extracted and removed from the source list (step A2). Then, a score of 2 is given to the source having no hierarchy (step S2).

Similarly, the V extracted at the time of A (n-1)
Only the source having only the HDL source in the lower hierarchy is extracted and removed from the source list (step An). Then, a score n is assigned to the source having no hierarchy (step S3).

This process is continued until there is no more source (step S4 → An...). Then, when all the sources have disappeared, all the sources should have scores, so the processing is performed in order from the source with the smallest score (step S5). In this case, the sources having the same score are out of order, so that the order may be arbitrary.

Here, in order to find out what kind of children the VHDL model has, a configuration part in the VHDL source is used. FIG. 11 shows an example. FIG. 11 shows that the configuration name is “AAA” (portion surrounded by a solid line) and “DD”.
It is a figure which shows the part of the configuration of the source which makes the model which has the configuration name to which the name "D" and "CCC" (the part enclosed with the broken line) was given a child.

In the same figure, "BBB" is e of VHDL.
This is called the entity name, and is also the name of the circuit. “ARC” is VHDL architecture
This is called the name of the operating part of the circuit. For example, as in “ARC” of “BBB”, ent
It is used in a pair with the "ity". And "CONFI
"GRATION" is an instruction to combine these "BBB" and "ARC" into one, for example, CONFIGRAT.
ION “AAA” is entity “BBB” and arc
height "ARC".

In this system, the "CONFI"
It is assumed that "GRATION" is described.
Therefore, here the entity name and architec
The name of the cure has no special meaning.

Note that "u1" and "u2" are the respective instance names, which are the names given to the circuits. "R
“RR” is called a component name of VHDL, and is information indicating how the lower layer is used.
The same applies to “TTT”. “LLL” is a library name.

Finally, the applicable range of the present system will be described. This system is applicable only to the scope of one library declaration. That is, “LL” in FIG.
This system can be applied to a range where L "is the same.

When the VHDL analyzes a source, it must specify what library the source will analyze (this is called a library name), but the scope of one library declaration is Means that the library names are the same.
This is shown in FIG. That is, the ranges surrounded by the broken lines in the drawing are the library a (VHDL source M), the library b (VHDL source A to F), and the library c (VHDL source G to L). Analyze.

As described above, according to the present system, when analyzing a plurality of VHDL sources having a hierarchical structure, a VHDL simulator having a sorting function is used. You don't have to worry about watching. Therefore, even a person who does not understand VHDL can perform a simulation.

By preparing a recording medium on which a program for realizing the processing of FIG. 10 described above is recorded and controlling the computer with the program, the same sort and analyze processing as described above can be performed. What you can do is obvious. As this recording medium, various recording media can be used in addition to a semiconductor memory and a magnetic disk device not shown in each drawing.

As described above, according to the present system, VH
By programming the procedure for arranging the DL sources, the burden on the user of having to rearrange the VHDL sources can be reduced. This eliminates the need for the user to reorder the VHDL sources, and allows the VHD source to be
The analysis of L can be performed.

Although the system for analyzing the VHDL source has been described above, it is apparent that the analysis of the hierarchical structure and the rearrangement of the sources can be similarly performed on a source having a hierarchical structure. .

[0053]

As described above, according to the present invention, when analyzing a plurality of VHDL sources having a hierarchical structure, a VHDL simulator having a reordering function is used. There is an effect that the trouble of viewing the source can be omitted and the burden on the user can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing processing when a simulator performs rearrangement according to the present system.

FIG. 2 is a diagram illustrating an example of a hierarchical VHDL.

FIG. 3 is a diagram showing a process in a case where rearrangement is performed manually.

FIG. 4 is a diagram illustrating a processing flowchart when rearrangement is performed manually.

FIG. 5 is a diagram illustrating a processing flowchart when rearrangement is performed by a simulator.

FIG. 6 is a diagram showing a processing flow for activating an automatic rearrangement program and performing analysis.

FIG. 7 is a diagram illustrating an example of a model having a hierarchy.

FIG. 8 is a diagram showing an example of rearrangement for the model of FIG. 7;

FIG. 9 is a diagram showing a processing procedure for rearranging the model of FIG. 7;

FIG. 10 is a flowchart showing the operation of the present system.

FIG. 11 is a diagram showing a search portion for rearranging VHDL sources.

FIG. 12 is a diagram showing an applicable range of the present system.

FIG. 13 is a diagram showing a conventional technical design flowchart.

[Explanation of symbols]

 10 Rearrangement processing 11 Analyze 100 VHDL simulator A to F VHDL source

Claims (6)

[Claims] 1. An analyzing system for inputting a plurality of VHDL sources to a simulator in an order according to a hierarchical structure thereof and analyzing whether or not the sources are correctly described, wherein the analyzing unit analyzes the hierarchical structure of the VHDL source. Means for analyzing the hierarchical structure and the VH according to the analysis result.
And a rearranging means for rearranging the DL sources, wherein the rearranged VHDL sources are input to the simulator. 2. The reordering means searches the contents of each VHDL source, finds out what name the VHDL source is, and finds what VHDL source the VHDL source is. Check if you have as a child that is a lower layer source, and check each VHD
Levels are provided in the L source to compare each other's VHDL sources, the VHDL source with children raises the level, and the operation of discarding the lowest level source is repeated by the number of sources, thereby determining the level of each source. 2. The analyzing system according to claim 1, wherein the sources are rearranged based on this. 3. An analyzing method for inputting a plurality of VHDL sources to a simulator in an order according to a hierarchical structure thereof and analyzing whether or not the sources are correctly described, comprising analyzing the hierarchical structure of the VHDL source. A hierarchical structure analysis step to be performed, and the VH
A rearranging step of rearranging the DL sources, and inputting the rearranged VHDL sources to the simulator. 4. In the rearranging step, each V
The contents of the HDL source are searched to find out what name the VHDL source is, and what kind of VHDL source the VHDL source has as a child that is a lower hierarchical source. Check, set the level for each VHDL source, and
By comparing the sources, the VHDL source with children raises the level, and the process of discarding the lowest level source is repeated by the number of sources, so that the level of each source is determined, and the source is rearranged based on this. The analyzing method according to claim 3, wherein 5. A recording medium storing an analyze program for inputting a plurality of VHDL sources to a simulator in an order according to the hierarchical structure and analyzing whether or not the sources are correctly described. ,
A hierarchical structure analyzing step of analyzing a hierarchical structure of the VHDL source; and a rearranging step of rearranging the VHDL source according to the analysis result, wherein the rearranged VHDL source is input to the simulator. An analysis program recording medium characterized by the above-mentioned. 6. In the rearranging step, each V
The contents of the HDL source are searched to find out what name the VHDL source is, and what kind of VHDL source the VHDL source has as a child that is a lower hierarchical source. Check, set the level for each VHDL source, and
By comparing the sources, the VHDL source with children raises the level, and the process of discarding the lowest level source is repeated by the number of sources, so that the level of each source is determined, and the source is rearranged based on this. An analysis program recording medium according to claim 5, wherein: