JPH029370B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to logic simulation, and more particularly to a test coverage method for efficiently testing logic circuits and microprograms.

[Background of the invention]

As information processing devices become larger in scale, the amount of computer time required for logic simulation also increases. Therefore, there is a need for an appropriate test coverage method to evaluate whether sufficient tests have been performed as a result of logic simulation.

Conventionally, test coverage methods in logic simulation have been discussed, for example, by I.E.
It is discussed in the paper entitled "Design Verification System for Large-Scale LSI Design" by Mitsushiel Monakino at the 19th EE Design Automation Conference (1982).

According to this, test coverage of logic functions and microprograms becomes possible, and efficient logic simulation can be realized.

However, since this method is a method of creating a flowchart and designing logic, it cannot be directly applied to a method of designing logic without creating a flowchart.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a test coverage method for eliminating the above-mentioned conventional problems and efficiently performing logic simulation of logic circuits and microprograms.

[Summary of the invention]

The present invention makes it possible to understand the operating range of logic circuits and microprograms by extracting changes in signal states from the execution results of logic simulation and storing them in the relevant storage device. This allows simulations to be carried out efficiently.

That is, the configuration of the present invention includes a storage means for storing a correspondence table between each signal identification name of a logic circuit and the number of operations thereof, and a storage means for storing a correspondence table between path identification between steps of a microprogram and the number of times the path has passed. Then, the number of operations and the number of passes in both storage means are updated based on information indicating signal changes for each signal identification name output as a result of logic simulation and passing information for each path identification between steps of the microprogram. This is a logic simulation test coverage method having means for

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below based on the drawings.

FIG. 1 is a flowchart showing the procedure of a logic simulation test coverage method.

First, coverage check information creation processing is performed (step 1), then simulation result information analysis processing is performed (step 2), coverage check information update processing is performed (step 3), and coverage check information display output processing is performed. (Step 4).

FIG. 2 is a general flowchart showing the relationship between the above steps, and the area surrounded by dotted lines is the scope of the present invention. In the coverage check information creation process 1, a coverage check information file 8 is created from the microprogram source code file 5 and the signal information file 6. In the simulation result information analysis process 2, a trace information file 9 is created using the simulation result file 7, which is the output of the logic simulation 12, as input. Furthermore, logic simulation 12
is a step in which the gate logic file 13 and the simulation data file 14 are input, and the simulation result file 7 is output.

In the coverage check information update process 3, the trace information file 9 and the coverage check information file 8 are matched, and the number of operations of the corresponding item in the coverage check information file 8 is added.

In coverage check information display output processing 4,
The data in the coverage check information file 8 is displayed and output to the terminal device 10 or the printing device 11.

Each time the logic simulation 12 is performed,
The simulation result information analysis device 2 performs a coverage check information update process 3 to update the coverage check information file 8. Third
The figure is a diagram illustrating coverage check information creation processing 1.

The microprogram source code file 5 has a microprogram table 15 that has one entry corresponding to each step of the microprogram, and each microprogram step has its own microprogram address 16 and the next execution option. The next microprogram address (NEXT) 17 and the next microprogram address (NEXTS) 18 with the same characteristics are stored. A microprogram coverage table 21 of a microprogram coverage check information file 19 is created by the coverage check information creation process 1 from this own microprogram address 16 and microprogram addresses NEXT 17 and NEXTS 18 that are likely to be executed next. Micro program table 1
5 to micro program coverage table 2
1 is specifically created as follows. When the microprogram address 16 of the microprogram table 15 has 0 address as its own microprogram address 16, the microprogram address that may be executed next is
These are 1 address and 2 addresses from NEXT17 and NEXTS18, respectively. Assuming that the combination of the next microprogram address from the own microprogram address is 0-1, 0-2, these are stored as the microprogram path 22, and the number of times this microprogram path 22 has been passed, that is, the number of passes 23, is calculated. Store as initial value 0. A signal name table 19 is stored in the signal information file 6, and this signal name table 19 is stored in the logical coverage check information file 2.
Create it as 0. Specifically, it is created as follows. The coverage check information creation process 1 extracts the signal name 20 assigned to the logic circuit from the signal name table 19 of the signal information file 6, stores it in the signal name 20 of the logic circuit coverage table 24 of the logic circuit coverage check information file 20,
The number of times the signal value of signal name 20 changes from 0 to 1, 1 to 0 is stored as the operation count 25, but the initial value is 0.
shall be.

FIG. 4 is a diagram illustrating the simulation result information analysis process 2 and the coverage check information update process 3. From the simulation result table 26 stored in the simulation result file 7, the number of times the signal value changes from 0 to 1 and 1 to 0 for the cycle 28 of the signal name 20 is counted, and the logical coverage table 26 of the trace information file 9 is counted. The signal name 20 and the number of operations 25 are stored in . Furthermore, CSAR27 of the simulation result table 26 of the simulation result file 7 indicates the address where the microprogram was executed.
From cycle 28, the address of the microprogram is known, and it is assigned to the microprogram path 0-1, 1-3, 3-, respectively, in the microprogram coverage table 21 of the trace information file 9.
Store 4. Next, the coverage check information file 8 is searched by the signal name of the operation count 25 of the signal in the logical coverage table 24 of this trace information file 9, and the operation count 2 of the signal that matches is searched.
Add to 5. Further, the microprogram path 22 of the microprogram coverage table 21 of the microprogram coverage check information file 19 searches for the microprogram path 22 of the microprogram coverage table 21 of the trace information file 9, and the number of passages 23 of the matched microprogram path 22 is calculated. Add 1 to . From the data in the coverage check information file 8 updated through the above processing, the signal name 2 of the logic circuit is
According to the operation count 25 of 0, a signal having a value of 0 indicates that the signal did not operate, and a signal having a value of 1 or more indicates that it operated. In addition, the microprogram has the number of times each microprogram path 22 passes 2
Microprogram path 22 where 3 has a value of 0
indicates that the microprogram path 22 was not passed, and a microprogram path 22 having a value of 1 or more indicates that it was passed. By displaying and outputting these by the coverage check information display output processing 4, the operating range of the logic circuit and microprogram by the logic simulation 12 can be known, and the logic circuit and microprogram that are not yet operating can be operated from now on. A simulation data tough aisle 14 can be created for this purpose.
In this manner, by performing a coverage check based on the signal state of the logic simulation, the operating range of the logic circuit and microprogram can be more accurately grasped.

〔Effect of the invention〕

As explained above, the present invention performs a coverage check during logic simulation to grasp the operating range of logic circuits and microprograms, so it is possible to eliminate redundant logic simulation tests, reduce logic simulation time, It has excellent effects on conducting valid tests.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing the procedure of the logic simulation test coverage method according to the present invention, FIG. 2 is a general flowchart showing the relationship between the procedures shown in FIG. 1, and FIG. FIG. 4 is a diagram for explaining the information creation process, and FIG. 4 is a diagram for explaining the simulation result information analysis process and the coverage check information update process according to the present invention. 1...Coverage check information creation processing, 2...
... Simulation result information analysis processing, 3 ... Coverage check information update processing, 4 ... Coverage check information display output processing, 5 ... Micro program source code file, 6 ... Signal information file, 7 ... Simulation result file, 8 ...Coverage check information file, 9
...Trace information file, 10...Terminal device,
11...Printing device, 12...Logic simulation, 13...Gate logic file, 14...Simulation data file, 15...Microprogram table, 16...Microprogram address, 17...Next microprogram address , 18...Next microprogram address,
19...Signal name table, 20...Signal name, 21
...Micro program coverage table, 2
2... Micro program path, 23... Number of passes, 24... Logic circuit coverage table, 25
...Number of operations, 26...Simulation result table.

Claims (1)

[Claims] 1 A logic circuit and a microprogram are operated in a simulated manner using simulation data such as a test program, and as a result, information indicating signal changes for each signal identification name of the logic circuit and execution step information of the microprogram are output. A method for determining test coverage based on a logic simulation in which the test coverage is calculated based on a logic simulation, comprising: a first storage means for storing the number of operations for each signal identification name of the logic circuit; a second storage means for updating the number of operations in the first storage means based on information indicating a signal change in the microprogram, and storing the number of passes for each pass between steps of the microprogram; A logic simulation test characterized in that passing path information is created based on execution step information output as a result of the logic simulation, and the number of passes in the second storage means is updated from the passing path information. Coverage method.