JP2982418B2 - Functional simulation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function simulation apparatus for verifying the operation of a designed logic device in designing the logic device.

[0002]

2. Description of the Related Art In recent years, in order to efficiently develop a large-scale and complicated logic device, particularly an LSI, etc., it has become important to design a function at a register transfer level and to perform early verification by a function simulation device. I have.

In the function design at the register transfer level, registers, latches, buses, adders, and the like are used as functional elements constituting a logic device. A function description language is a language that describes the operation of a circuit using the above functional elements,
It consists of an assignment statement for assigning the signal value of the functional element to the functional element. The assignment statement indicating the flow of these signals is accompanied by a description having a function of selecting a functional element holding a signal value to be substituted and designation of a synchronization signal of a register to be substituted. Each assignment statement in the description means the assignment of signal values parallel to each other, and the function description indicates a parallel operation of the circuit at an arbitrary time.

As a method of simulating a design result described by a register transfer level function description language, there are mainly an event driving method and a compiling method.

In the event driving method, at each time of a simulation, only an assignment statement for assigning a changed signal value is selected and evaluated. If there is a new signal value change in the assigned functional element, this functional element Is stored as if there was a change in the signal value. The functional element having a changed signal value and the changed signal value are called an event. At the next time, the signal value of the functional element is updated based on the stored event, and an assignment statement is selected and evaluated. Events are stored in a buffer called a time wheel, and are retrieved when a specified propagation delay time has elapsed. To evaluate an assignment statement,
The reverse Polish style evaluation code generated in the preprocessing is used.

In addition, there is a method in which each assignment statement is developed into a description of connection between functional elements and the event driving method is applied in the same manner as in normal logic simulation.

The event-driven method is a method of selecting and evaluating only a necessary assignment statement based on an event. However, the processing of an event or an assignment statement that needs to be evaluated is selected, and the assignment statement is converted into a reverse Polish form. Because it takes time to evaluate the code, the processing speed is slow.

On the other hand, there is a compiling method as a method for speeding up the simulation by lowering the simulation accuracy to some extent. The compilation method deals only with designs that are modeled as complete synchronous circuits that operate on the same synchronous signal. That is, assuming that all signal changes occur only at the synchronization signal change points, the assignment statement is evaluated only at the synchronization signal change points. The evaluation of the assignment statement is performed collectively by a computer program generated from the function description.

A function simulation apparatus to which the conventional event driving method is applied can simulate an asynchronous circuit operation, that is, evaluate signal value substitution and delay time at an asynchronous timing. And the processing speed is slow. On the other hand, the compile method is fast in processing, but cannot handle asynchronous circuit operation and delay time. Therefore, in order to realize a simulation device that handles asynchronous circuit operation and delay time, it is basically necessary to apply the event driving method.

[0010]

When the event driving method is applied, the processing speed is slow because the overhead of event processing is large because evaluation control using an event is performed for each assignment statement. From a plurality of signal values assigned by a plurality of assignment statements as in the case of performing a bus conflict simulation in which a signal value is assigned to the same functional element, for example, a signal bus controlled by a three-state element, by a plurality of assignment statements. It is necessary to calculate the collision signal value on the final functional element. Conventionally, such a calculation of a collision signal value has been performed using an evaluation program for obtaining a new collision value, separately from an evaluation program for evaluating an assignment statement. In this simulation, when one of the assignment statements assigned to the same functional element is evaluated, an event is generated, and the event drives a signal collision evaluation program to evaluate a bus conflict.

Since the above-described evaluation of substitution of signal values and calculation of signal values at the time of signal collision are always performed in conjunction with each other, control by events is useless in processing.

The present invention has been made in view of the above problems, and provides a functional simulation apparatus for performing a functional simulation at a high speed by applying an event driving method.

[0013]

According to the present invention, there is provided a function simulation apparatus for simulating the operation of a logic device described using a function description language using an event driving method. A function description in a language is parsed, an assignment statement for assigning a signal value to a functional element constituting a logic device to be simulated is extracted, and a signal value is assigned to the same functional element in the extracted assignment statement. Simulation data generating means for generating an evaluation program for selecting an assignment statement, evaluating the assignment statement for assigning a signal value to the same functional element at a time, and calculating a signal value when the assigned signal value collides; An evaluation program group generated by a simulation data generating means, and the evaluation program generated by an event driving method The activated, provides a functional simulation apparatus characterized by evaluating an assignment statement in the function description.

[0014]

According to the function simulation apparatus of the present invention, the processing for evaluating a plurality of assignment statements to be assigned to the same functional element and calculating the final collision signal value on the functional element from the plurality of signal values to be assigned is a single operation. Is performed collectively by generating the evaluation program of the above. As a result, the overhead of event processing for evaluating signal collision can be reduced.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a functional simulation apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a function simulation apparatus according to the present embodiment. In FIG. 1, reference numeral 11 denotes simulation data generation means for generating simulation data by inputting a function description. In order to perform a function simulation by the event driving method, the simulation data generating means 11 generates a function element list used in the function description, an evaluation program which is a computer program for evaluating each assignment statement in the function description, and a drive destination list. I do. The drive destination list is a list indicating a correspondence between an event indicating a functional element whose signal value has been updated and an evaluation program driven by the event, and is a list of evaluation program identifiers using the event as a key.

Next, an implementation example of the simulation data generation means 11 for generating simulation data using the function description of FIG. 1 as an input will be described with reference to FIG.

In FIG. 2, reference numeral 21 denotes a syntax analysis means for performing syntax analysis of an input function description. The syntax analysis unit 21 analyzes the text file described by the circuit designer, and lists a list of functional elements in the function description, an assignment statement list indicating an assignment statement configuration in the description, and a function statement for each functional element in the function description. Then, a drive destination list that lists substitution statements to be substituted, that is, input signals, with reference to the signal value of the functional element is generated. The structure of the assignment statement list will be described with reference to FIG.

The assignment statement list is data in which the assignment statement data 111 indicating the structure and content of each assignment statement in the function description is in a searchable list format. Each assignment statement data 111 is
Synchronization signal data 1111 indicating a synchronization signal of substitution, an assignment condition expression 1112 indicating a condition for executing the assignment, an assignment expression 1113 indicating an operation expression between the signals to be assigned, and an assignment destination functional element indicating the assignment destination functional element. 1114.

The above syntax analysis means 21 can be realized by a computer and syntax analysis software.

Reference numeral 22 denotes an assignment statement list storage unit that stores a list of assignment statements generated by the syntax analysis unit 21. The assignment statement list storage unit 22 is realized using a computer memory.

Reference numeral 23 denotes a competitive assignment statement selecting means for selecting an assignment statement to be assigned to the same functional element from the assignment statement list stored in the assignment statement list storage means 22 and generating a combined assignment statement list. The composite assignment statement list generated by the conflict assignment statement selection means 23 will be described with reference to FIG.

The composite assignment statement list is data in which the assignment destination functional elements 131 described in the function description can be searched. Further, it has a pointer that points to all assignment statement data lists 132 for assigning signal values from each assignment destination functional element 131 to the functional element. The substitution statement data to be searched is composed of the synchronization signal 1111, the substitution condition expression 1112 and the substitution expression 1113 described in FIG.

The synchronous assignment statement selecting means 23 can be realized on a computer. This processing procedure will be described with reference to FIG. First, the assignment statements stored in the assignment statement list storage unit 22 are searched in the order of the list, and an unprocessed assignment statement is input. It is assumed that the retrieved assignment statement has been processed (step S
1). An assignment destination functional element of the searched assignment statement is obtained (step S2). A list of the combined assignment statements already generated based on the synchronization signal is searched (step S3), and whether or not the assignment destination functional element of each combined assignment statement is the same as the assignment destination functional element of the assignment statement input in step S1. Is determined (step S4). If there is a combined assignment statement having the same assignment destination functional element, the data of the synchronization signal, the assignment condition expression, and the assignment expression of the assignment statement input in step S1 are added as the assignment data of the combined assignment statement (step S5). ). If a composite assignment statement list has not been generated in the initial state or if there is no composite assignment statement having the same assignment destination functional element, composite assignment statement data is generated from the assignment statement data input in step S1, and a composite assignment statement is generated. Add to the list (step S6). The above is performed for all the assignment statements stored in the assignment statement list storage unit 22 (step S7).

Reference numeral 24 denotes a composite assignment statement list storage unit that stores the composite assignment statement list synthesized by the synchronous assignment statement selection unit 23. The composite assignment statement list storage means 24
This is realized using a computer memory.

Reference numeral 25 denotes an evaluation program generation means for inputting the assignment statements stored in the combined assignment statement list storage means 24 and generating an evaluation program for evaluating each assignment statement. The evaluation program is a program written in a language that can be compiled into a machine language executed on a general computer. The evaluation program includes an input / output circuit control routine for inputting functional element signal values and outputting update data, a routine for evaluating arithmetic expressions of signal values, a routine for detecting changes in functional element signal values, and updating signal values. A routine indicating the delay value of the functional element and a routine for generating update data are included.

Reference numeral 26 denotes a drive destination list indicating correspondence between an event indicating a functional element whose signal value has been updated and an evaluation program driven by the event, based on the composite assignment statement list output from the synchronous assignment statement selection means 23. This is a drive destination list generating means for generating.

Next, the structure of the drive destination list will be described with reference to FIG. The drive destination list 161 is data in a list format in which functional elements described in the function description can be searched.
Further, each of the functional elements has a pointer to an assignment statement ID list 162 that enables searching for all the combined assignment statements to be assigned by referring to the signal value of the functional element. The assignment statement ID 162 retrieved from the drive destination list indicates the position of the corresponding assignment statement on the combined assignment statement list synthesized by the synchronous assignment statement selection unit 23.

The drive destination list generating means 26 searches a computer for each composite assignment statement in the composite assignment statement list, and extracts and lists functional elements from a synchronizing signal, a conditional expression, and an assignment expression of the composite assignment statement data. It is realized by.

Reference numeral 12 denotes test data input means for inputting test data used during simulation. The circuit designer sets a signal input to the circuit to be simulated using the test data input means 12 in the simulation device. The test data is electronic file data created using an editor or the like on a computer, and can be input using the same input means as a general-purpose computer. The input data indicates a signal value that changes at a specific simulation time of each functional element of the circuit to be simulated. The signal value is stored in the test data input means 12 every time the time changes, and the signal value changes when the simulation time reaches the change time.

Numeral 13 denotes simulation executing means for controlling the event and executing a functional simulation.
FIG. 7 shows the configuration of the simulation execution means 13.

Reference numeral 31 denotes an evaluation program storage unit that stores the evaluation program generated by the simulation data generation unit 11. Evaluation program storage means 3
1 is realized using a computer memory, and each computer program is sequentially stored on the memory. The evaluation program storage means 31 outputs the evaluation program data 311 at the address designated to be requested.

Reference numeral 32 denotes a drive destination list storage unit for storing the drive destination list generated by the simulation data generation unit 11. The drive destination list storage means 32
A key is a functional element identifier whose signal value has been updated, that is, an event, and a table having a list of identifiers of evaluation programs corresponding to the event and an evaluation program identifier are keyed.
And has a table having evaluation program load information. When the event 351 or the event 322 output from the simulation data input unit 12 is input, the driving destination list storage unit 32 first searches the first table for the identifier of the evaluation program to be executed, and searches the identifier of the searched evaluation program. Load information 321 is obtained from the second table and output. The load information 321 includes an address where the evaluation program stored in the evaluation program storage unit 31 is stored and a data size. The drive destination list storage means 32 is realized using a computer memory.

Reference numeral 33 denotes signal value storage means for storing the signal value of each functional element in the circuit to be simulated. The signal value storage unit 33 stores the signal values of the respective functional elements at the simulation time during the execution of the simulation, and retains the previous signal values until the time when a new signal value change occurs in the functional element. The signal value storage unit 33 updates the signal value changed inside the circuit as a result of the simulation, and updates the signal value by inputting the signal value data 331 of the functional element input from the test data input unit 12. When there is a request for a signal value with the functional element name as a key, the signal value at the current simulation time is output. The signal value storage means 33 is realized using a computer memory, and includes a search table for associating functional element identifiers with a memory area for storing signal values, and a signal value table for holding signal values.

Numeral 34 denotes an evaluation program executing means.
The evaluation program executing means 34 loads the selected evaluation program 311 and inputs a necessary function element signal value 333 as evaluation data, and executes the program to evaluate the function description. As an evaluation result, update data 341 is output for a functional element having a signal value different from the signal value at the simulation time. The output update data 341 includes a functional element identifier whose signal value changes, its signal value, and a delay value of the functional element. The evaluation program executing means 34 is realized by using a general computer and an input / output circuit. The evaluation program to be loaded includes an input / output circuit control routine for inputting a functional element signal value and outputting update data, a signal value The routine includes a routine for evaluating an arithmetic expression, a routine for detecting a change in a functional element signal value, a routine indicating a delay value of a functional element for updating a signal value, and a routine for generating update data.

Reference numeral 35 denotes an input of the update data 341, and when the simulation time elapses from the simulation time by the delay value of the update data 341, an event 351 as a functional element identifier whose signal value has been updated and the update signal value data 352. And a time wheel that outputs
The time wheel 35 is implemented on a computer memory, and includes a counter for counting the elapsed simulation time and a list of functional element information updated at each simulation time.

Reference numeral 36 denotes the execution timing of the processing of the evaluation program storage unit 31, the drive destination list storage unit 32, the signal value storage unit 33, the evaluation program execution unit 34, and the time wheel 35 within the same time as the update of the simulation time. It is a simulation time and processing timing control means for controlling. The simulation time and processing timing control means 36 detects the presence or absence of the event 321 or 351, searches the drive list for each event at the time, selects an evaluation program and loads it into the evaluation program execution means, A series of controls such as execution and registration of the functional element signal value in the time wheel 35 are sequentially performed. The simulation time and processing timing control means 36 can be realized by a general sequential circuit.

Numeral 14 denotes simulation result display means for verifying, evaluating and analyzing the simulation result. The simulation result display means can be realized on a general-purpose computer using a display monitor and display software.

The functional simulation device comprises the above-described simulation data generation means 11, simulation execution means 12, test data input means 13, and simulation result display means 14. In the simulation apparatus according to the embodiment of the present invention, the simulation data is input by the simulation data generating means 11 and the test data input means 13 as preprocessing. The function simulation executes a circuit operation for a finite time by applying an event driving method with an input signal set by the test data input unit 13 as an external event. The designer operates the simulation result display means 1
4 to obtain a simulation result.

[0040]

According to the functional simulation apparatus of the present invention, a process for evaluating a plurality of assignment statements to be assigned to the same functional element and calculating a final collision signal value on the functional element from the plurality of signal values to be assigned is performed. This is done collectively by generating a single evaluation program. As a result, the overhead of event processing for evaluating signal collision can be reduced, and simulation can be speeded up.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a function simulation apparatus according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a simulation data generation unit that executes the functional simulation device of the embodiment.

FIG. 3 is a diagram showing a data configuration of an assignment statement list generated by parsing the function description in the embodiment.

FIG. 4 is a view showing a data configuration of a combined assignment statement list synthesized based on the assignment destination functional element in the embodiment.

FIG. 5 is a flowchart showing a procedure of a program on a computer for generating a composite assignment statement list in the embodiment.

FIG. 6 is a diagram showing a data configuration of a drive destination list in the embodiment.

FIG. 7 is a configuration diagram of simulation execution means in the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Simulation data generation means 12 Test data input means 13 Simulation execution means 14 Simulation result display means 21 Syntax analysis means 22 Assignment sentence list storage means 23 Competitive assignment sentence selection means 24 Synthetic assignment sentence list storage means 25 Evaluation program generation means 26 Driving destination List generation means

Claims (1)

(57) [Claims] 1. A function simulation apparatus for simulating the operation of a logic device described using a function description language using an event driving method, wherein the function description in the function description language is parsed, and a logic device to be simulated is analyzed. Extract an assignment statement for assigning a signal value to a functional element constituting, select an assignment statement for assigning a signal value to the same functional element from among the extracted assignment statements, and assign a signal value to the same functional element. Simulation data generating means for generating an evaluation program for evaluating the assignment statements to be performed collectively and calculating the signal value when the substituted signal values collide, generating an evaluation program group by the simulation data generating means, The method is characterized in that the evaluation program group generated by the driving method is started and the assignment statement in the function description is evaluated. Functional simulation device.