JP2990882B2 - Functional simulation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function simulation apparatus for verifying the operation of a designed logic device in designing the logic device.

[0002]

2. Description of the Related Art In recent years, in order to efficiently develop a large-scale and complicated logic device, particularly an LSI, etc., it has become important to design a function at a register transfer level and to perform early verification by a function simulation device. I have.

In the function design at the register transfer level, registers, latches, buses, adders, and the like are used as functional elements constituting a logic device. A function description language is a language that describes the operation of a circuit using the above functional elements,
It consists of an assignment statement for assigning the signal value of the functional element to the functional element. The assignment statement indicating the flow of these signals is accompanied by a description having a function of selecting a functional element holding a signal value to be substituted and designation of a synchronization signal of a register to be substituted. Each assignment statement in the description means the assignment of signal values parallel to each other, and the function description indicates a parallel operation of the circuit at an arbitrary time.

As a method of simulating a design result described by a register transfer level function description language, there are mainly an event driving method and a compiling method.

In the event driving method, at each time of a simulation, only an assignment statement for assigning a changed signal value is selected and evaluated. If there is a new signal value change in the assigned functional element, this functional element Is stored as if there was a change in the signal value. The functional element having a changed signal value and the changed signal value are called an event. At the next time, the signal value of the functional element is updated based on the stored event, and an assignment statement is selected and evaluated. Events are stored in a buffer called a time wheel, and are retrieved when a specified propagation delay time has elapsed. To evaluate an assignment statement,
The reverse Polish style evaluation code generated in the preprocessing is used.

In addition, there is a method in which each assignment statement is developed into a description of connection between functional elements and the event driving method is applied in the same manner as in normal logic simulation.

The event-driven method is a method of selecting and evaluating only a necessary assignment statement based on an event. However, the processing of an event or an assignment statement that needs to be evaluated is selected, and the assignment statement is converted into a reverse Polish form. Because it takes time to evaluate the code, the processing speed is slow.

On the other hand, there is a compiling method as a method for speeding up the simulation by lowering the simulation accuracy to some extent. The compilation method deals only with designs that are modeled as complete synchronous circuits that operate on the same synchronous signal. That is, assuming that all signal changes occur only at the synchronization signal change points, the assignment statement is evaluated only at the synchronization signal change points. The evaluation of the assignment statement is performed collectively by a computer program generated from the function description.

[0009]

The function simulation apparatus to which the conventional event driving method is applied can simulate asynchronous circuit operation, that is, evaluate signal value substitution and delay time at asynchronous timing. However, the processing speed is slower than the compiling method. On the other hand, the compile method is fast in processing, but cannot handle asynchronous circuit operation and delay time. Therefore, to realize a simulation device that handles asynchronous circuit operation and delay time,
Basically, it is necessary to apply the event driven method.

When the conventional event driving method is applied, the processing speed is considered to be reduced due to the following reasons.

A first cause is that the overhead of event processing is large because control of evaluation using an event is performed for each assignment statement. If the scale of the partial circuit whose evaluation is controlled by the event is large relative to the ratio of the portion where the signal value actually changes in the circuit, the overhead of event processing increases. In a synchronous circuit, most parts of the circuit operate at the change points of the synchronous signal. If the evaluation is controlled by an event for each assignment statement, the overhead of event processing becomes extremely large as compared with the compile method. In a normal circuit design, a partial circuit operating synchronously has two
It is said to be more than 0%.

A second cause is that the process of evaluating each assignment statement is not efficient. The increase in the simulation processing time due to the above two points may be difficult to improve in order to simulate an asynchronous circuit operation. However, there are some improvements in the event-driven method that make the processing faster.

First, it is necessary to evaluate the assignment of a signal value at an asynchronous timing based on an event for each assignment statement. However, the evaluation of an assignment statement in which assignment is performed by the same synchronous signal is performed for each assignment statement. It is not necessary to evaluate each sentence using an event. Event processing for individually evaluating the assignment statements based on such a synchronization signal is useless in processing.

Next, the evaluation of each assignment statement, particularly the evaluation of an arithmetic expression, etc., was performed by sequentially reading and evaluating a code in a reverse Polish format or the like. The processing of reading and translating such a code is slower than the processing of directly executing a compiled machine language.

Further, an assignment statement for performing assignment in accordance with a synchronization signal describes an operation of assigning a signal value only when a signal value of a functional element corresponding to the synchronization signal changes. Therefore, if the signal value to be substituted has changed but the synchronization signal has not changed, it is not necessary to evaluate the substitution statement. Therefore, processing of an event other than the synchronization signal for the above assignment statement and execution of the evaluation program by this event are useless.

The problem of the processing speed described above also depends on how to describe functions. This has led to the problem that, in order to perform higher-speed simulations, circuit designers must describe functions in terms of speedup in consideration of simulation processing in addition to modeling circuits. Was.

The conventional function simulation apparatus has a number of problems as described above. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a function simulation apparatus that performs a function simulation at high speed by applying an event driving method.

[0018]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention analyzes the syntax of a functional description in a functional description language and substitutes a signal value for a functional element constituting a logic device to be simulated. Simulation data generating means for extracting a sentence, selecting an assignment statement to be assigned by the same synchronization signal from the extracted assignment statements, and generating an evaluation program for collectively evaluating assignment statements having the same synchronization signal the provided, by the simulation data generating means to generate an evaluation program group, start the evaluation program group generated by event-driven method,
Provided is a function simulation device that evaluates an assignment statement in a function description.

Furthermore, among the events that drive the evaluation program generated by the prior Symbol evaluation program generating means, and a event selection means for selecting only the synchronizing signal events of the evaluation program, the syntax analysis unit from the functional description It used to extract the assignment statement, select the assignment statement for each synchronization signal used in the function described by the assignment statement selecting means to generate an evaluation program group by the evaluation program generating means, evaluated by the prior SL event selection section program And a function simulation device for selecting an event that drives the, and executing an evaluation program for an assignment statement having a synchronization signal at the time of simulation execution only by an event in which the corresponding synchronization signal has changed.

[0020]

According to the first functional simulation apparatus of the present invention, the evaluation of assignment statements by the same synchronization signal is collectively evaluated by a single computer program. As a result, it is possible to reduce the overhead of processing the event of the same synchronization signal redundantly, and to speed up the processing. Further, since this computer program is compiled and executed up to the machine language level in advance, it is more efficient than a method of sequentially reading and evaluating codes.

Further, in the case of an assignment statement that performs an assignment in accordance with a synchronization signal during execution of a simulation, the assignment statement is evaluated only by an event of the synchronization signal. Therefore, the process of evaluating an assignment statement having a synchronization signal by an event other than the synchronization signal is reduced.

With the above operation, the function simulation apparatus of the present invention enables a function simulation for performing high-speed processing.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a functional simulation apparatus according to a first embodiment of the present invention will be described with reference to the drawings.

An object of the present embodiment is to reduce the overhead of processing the event of the same synchronization signal redundantly and to speed up the function simulation.

FIG. 1 is a configuration diagram of a function simulation apparatus according to the present embodiment. In FIG. 1, reference numeral 11 denotes simulation data generation means for generating simulation data by inputting a function description. In order to perform a function simulation by the event driving method, the simulation data generating means 11 generates a function element list used in the function description, an evaluation program which is a computer program for evaluating each assignment statement in the function description, and a drive destination list. I do. The drive destination list is a list indicating a correspondence between an event indicating a functional element whose signal value has been updated and an evaluation program driven by the event, and is a list of evaluation program identifiers using the event as a key.

Next, an implementation example of the simulation data generation means 11 for generating simulation data using the function description of FIG. 1 as an input will be described with reference to FIG.

In FIG. 2, reference numeral 21 denotes a syntax analysis means for performing syntax analysis of an input function description. The syntax analysis unit 21 analyzes the text file described by the circuit designer, and lists a list of functional elements in the function description, an assignment statement list indicating an assignment statement configuration in the description, and a function statement for each functional element in the function description. Then, a drive destination list that lists substitution statements to be substituted, that is, input signals, with reference to the signal value of the functional element is generated. The structure of the assignment statement list will be described with reference to FIG.

The assignment statement list is data in which the assignment statement data 111 indicating the structure and contents of each assignment statement in the function description is in a searchable list format. Each assignment statement data 111 is
Synchronization signal data 1111 indicating a synchronization signal of substitution, an assignment condition expression 1112 indicating a condition for executing the assignment, an assignment expression 1113 indicating an operation expression between the signals to be assigned, and an assignment destination functional element indicating the assignment destination functional element. 1114.

The above-mentioned parsing means 21 can be realized by a computer and parsing software.

Reference numeral 22 denotes an assignment statement list storage means for storing a list of assignment statements generated by the syntax analysis means 21. The assignment statement list storage unit 22 is realized using a computer memory.

A synthesizing unit 23 selects an assignment statement to be assigned by the same synchronization signal from the assignment statement list stored in the assignment statement list storage unit 22, and lists a plurality of assignment statement data under one synchronization signal. Synchronous assignment statement selection means for generating an assignment statement list. Synchronous assignment statement selection means 23
Will be described with reference to FIG.

The composite assignment statement list is data in which the synchronization signal 131 described in the function description is in a searchable list format. Further, it has pointers to all assignment statement data lists 132 for assigning signal values in synchronization with the synchronization signals from the respective synchronization signals 131. The substitution statement data retrieved from the synchronization signal is the substitution condition expression 11 described in FIG.
12, an assignment expression 1113, and an assignment destination functional element.

The synchronous assignment statement selecting means 23 can be realized on a computer. This processing procedure will be described with reference to FIG. First, the assignment statements stored in the assignment statement list storage unit 22 are searched in the order of the list, and an unprocessed assignment statement is input. It is assumed that the retrieved assignment statement has been processed (step S
1). Find the synchronization signal of the searched assignment statement (step S
2). A composite assignment statement list that has already been generated based on this synchronization signal is searched (step S3), and it is determined whether or not the synchronization signal of each composite assignment statement is the same as the synchronization signal of the assignment statement input in step S1. (Step S4). If there is a composite assignment statement having the same synchronization signal, the data of the assignment condition expression, the assignment expression, and the assignment destination functional element of the assignment statement input in step S1 are added as the assignment data of this composite assignment statement (step
S5). If the composite assignment statement list is not generated in the initial state or if there is no composite assignment statement with the same synchronization signal,
Generate composite assignment statement data from the assignment statement data input in step S1, and add it to the composite assignment statement list (step S1).
6). The above is performed for all the assignment statements stored in the assignment statement list storage unit 22 (step S7).

Reference numeral 24 denotes a combined assignment statement list storage unit that stores the combined assignment statement list combined by the synchronous assignment statement selection unit 23. The composite assignment statement list storage means 24
This is realized using a computer memory.

Numeral 25 denotes an evaluation program generating means for inputting the assignment statements stored in the composite assignment statement list storage means 24 and generating an evaluation program for evaluating each assignment statement. The evaluation program is a program written in a language that can be compiled into a machine language executed on a general computer. The evaluation program includes an input / output circuit control routine for inputting functional element signal values and outputting update data, a routine for evaluating arithmetic expressions of signal values, a routine for detecting changes in functional element signal values, and updating signal values. A routine indicating the delay value of the functional element and a routine for generating update data are included.

Reference numeral 26 denotes a drive destination list indicating correspondence between an event indicating a functional element whose signal value has been updated and an evaluation program driven by the event, based on the composite assignment statement list output from the synchronous assignment statement selection means 23. This is a drive destination list generating means for generating.

Next, the structure of the drive destination list will be described with reference to FIG. The drive destination list 161 is data in the form of a searchable list of functional elements described in the function description. Further, each of the functional elements has a pointer to an assignment statement ID list 162 that enables searching for all the combined assignment statements to be assigned by referring to the signal value of the functional element. The assignment statement ID 162 retrieved from the drive destination list indicates the position of the corresponding assignment statement on the combined assignment statement list synthesized by the synchronous assignment statement selection unit 23.

The drive destination list generating means 26 searches a computer for each composite assignment statement in the composite assignment statement list, and extracts and lists functional elements from a synchronizing signal, a conditional expression, and an assignment expression of the composite assignment statement data. It is realized by.

Reference numeral 12 denotes test data input means for inputting test data used at the time of simulation. The circuit designer sets a signal input to the circuit to be simulated using the test data input means 12 in the simulation device. The test data is electronic file data created using an editor or the like on a computer, and can be input using the same input means as a general-purpose computer. The input data indicates a signal value that changes at a specific simulation time of each functional element of the circuit to be simulated. The signal value is stored in the test data input means 12 every time the time changes, and the signal value changes when the simulation time reaches the change time.

Numeral 13 denotes simulation execution means for executing a function simulation by controlling an event.
FIG. 7 shows the configuration of the simulation execution means 13.

Reference numeral 31 denotes an evaluation program storage for storing the evaluation program generated by the simulation data generator 11. Evaluation program storage means 3
1 is realized using a computer memory, and each computer program is sequentially stored on the memory. The evaluation program storage means 31 outputs the evaluation program data 331 at the address designated to be requested.

Reference numeral 32 denotes a drive destination list storing means for storing the drive destination list generated by the simulation data generating means 1. The drive destination list storage means 32 has a function element identifier having an updated signal value, that is, an event as a key, a table having a list of evaluation program identifiers corresponding to the event as a key, and an evaluation program identifier as a key, and has evaluation program load information. Have a table.
When the event 351 or the event 322 output from the simulation data input unit 2 is input, the drive destination list storage unit 32 first searches the first table for the identifier of the evaluation program to be executed, and searches the identifier of the searched evaluation program. Load information 321 is obtained from the second table and output. The load information 321 includes an address where the evaluation program stored in the evaluation program storage unit 31 is stored and a data size. The drive destination list storage means 32 is realized using a computer memory.

Reference numeral 33 denotes signal value storage means for storing a signal value of each functional element in the circuit to be simulated. The signal value storage unit 33 stores the signal values of the respective functional elements at the simulation time during the execution of the simulation, and retains the previous signal values until the time when a new signal value change occurs in the functional element. The signal value storage unit 33 updates the signal value changed inside the circuit as a result of the simulation, and updates the signal value by inputting the signal value data 331 of the functional element input from the test data input unit 2.
When there is a request for a signal value with the functional element name as a key, the signal value at the current simulation time is output. The signal value storage means 33 is realized using a computer memory,
It comprises a search table for associating functional element identifiers with memory areas for storing signal values, and a signal value table for holding signal values.

Reference numeral 34 denotes an evaluation program executing means.
The evaluation program executing means 34 loads the selected evaluation program 311 and inputs a necessary function element signal value 333 as evaluation data, and executes the program to evaluate the function description. As an evaluation result, update data 341 is output for a functional element having a signal value different from the signal value at the simulation time. The output update data 341 includes a functional element identifier whose signal value changes, its signal value, and a delay value of the functional element. The evaluation program executing means 34 is realized by using a general computer and an input / output circuit. The evaluation program to be loaded includes an input / output circuit control routine for inputting a functional element signal value and outputting update data, a signal value The routine includes a routine for evaluating an arithmetic expression, a routine for detecting a change in a functional element signal value, a routine indicating a delay value of a functional element for updating a signal value, and a routine for generating update data.

Reference numeral 35 denotes an input of the update data 341, and when the simulation time elapses from the simulation time by the delay value of the update data 341, an event 351 as a functional element identifier whose signal value has been updated and the update signal value data 352. And a time wheel that outputs
The time wheel 35 is implemented on a computer memory, and includes a counter for counting the elapsed simulation time and a list of functional element information updated at each simulation time.

Reference numeral 36 denotes the execution timing of the processing of the evaluation program storage means 31, the drive destination list storage means 32, the signal value storage means 33, the evaluation program execution means 34, and the time wheel 35 within the same time as the update of the simulation time. It is a simulation time and processing timing control means for controlling. The simulation time and processing timing control means 36 detects the presence or absence of the event 321 or 351, searches the drive list for each event at the time, selects an evaluation program and loads it into the evaluation program execution means, A series of controls such as execution and registration of the functional element signal value in the time wheel 35 are sequentially performed. The simulation time and processing timing control means 36 can be realized by a general sequential circuit.

Numeral 14 denotes simulation result display means for verifying, evaluating and analyzing the simulation result. The simulation result display means can be realized on a general-purpose computer using a display monitor and display software.

The functional simulation device comprises the above-described simulation data generation means 11, simulation execution means 12, test data input means 13, and simulation result display means 14. In the simulation apparatus according to the embodiment of the present invention, the simulation data is input by the simulation data generating means 11 and the test data input means 13 as preprocessing. The function simulation executes a circuit operation for a finite time by applying an event driving method with an input signal set by the test data input unit 13 as an external event. The designer sets the simulation result display means 4
Is used to obtain simulation results.

In the functional simulation apparatus of the embodiment having the above-described configuration, the evaluation program is basically executed by the event drive for each assignment statement in the function description, so that the assignment to the functional element executed asynchronously can be simulated. In addition, since the assignment to the functional element by the same synchronization signal is collectively executed by the same evaluation program that is automatically generated, the overhead of executing a plurality of evaluation programs is reduced and the simulation is speeded up. Can be.

Next, a function simulation apparatus according to a second embodiment of the present invention will be described with reference to the drawings. In the function simulation apparatus according to the first embodiment described above, as can be seen from the configuration of the embodiment, FIG.
In the drive destination list generated by the drive destination list generating means 26, the composite assignment statement ID is listed for all functional elements referenced by the composite assignment statement. For this reason, the assignment to the functional element by the synchronization signal is collectively executed by the same evaluation program that is automatically generated, and the overhead of executing a plurality of evaluation programs is reduced, but the corresponding composite assignment statement refers to. Each time the signal value of the functional element changes, the corresponding evaluation program is loaded and executed one by one even if the synchronization signal does not change. The purpose of this embodiment is to solve the above.
FIG. 1 of the function simulation apparatus according to the first embodiment.
Of the simulation data generating means 11 of FIG. An example of the configuration of the simulation data generating means of this embodiment will be described with reference to FIG.

In FIG. 8, the syntax analysis means 21, the assignment statement list storage means 22, the synchronous assignment statement selection means 23, the combined assignment statement storage means 24, the evaluation program generation means 25, and the drive destination list generation means 26 are the same as those in FIG. Same as described.

Reference numeral 27 denotes a composite assignment statement storage unit 2 based on the drive destination list generated by the drive destination list generation unit 26.
Event means for setting an evaluation program to be driven only for a synchronization signal event based on the composite assignment statement list stored in No. 4.

The event selection drive destination list generating means 27 searches the computer for each composite assignment statement in the composite assignment statement list, extracts a synchronizing signal of the composite assignment statement data, and converts the synchronizing signal into a functional element event which becomes the extracted synchronizing signal. This is realized only by a program that generates a drive destination list that lists the composite assignment statement ID. At this time, for an assignment having no synchronization signal, the composite assignment statement ID is listed in all functional elements in the conditional expression and the assignment expression.

In the functional simulation apparatus according to the present embodiment, by using the drive destination list generated by the event selection drive destination list generation means 27, the combination substitution is performed only when the signal value of the functional element corresponding to the synchronization signal changes. An evaluation program that evaluates the statement is loaded and executed. This means that overhead related to events other than the synchronization signal can be reduced, and the function simulation can be speeded up.

[0055]

As is apparent from the above description, according to the functional simulation apparatus of the first aspect, the evaluation program is basically executed in an event-driven manner for each assignment statement of the function description, so that the evaluation program is executed asynchronously. Substitution to functional elements can be simulated, and assignment to functional elements by the same synchronization signal is executed collectively by the same evaluation program that is automatically generated, reducing the overhead of executing multiple evaluation programs Thus, the speed of the simulation can be increased.

Further, according to the function simulation apparatus of the second aspect, it is possible to reduce the overhead related to events other than the synchronization signal, and to speed up the function simulation.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a function simulation apparatus according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a simulation data generation unit that executes the simulation apparatus according to the embodiment;

FIG. 3 is a diagram showing a data configuration of an assignment statement list generated by parsing the function description in the embodiment.

FIG. 4 is a diagram showing a data configuration of a combined assignment statement list synthesized based on a synchronization signal in the embodiment.

FIG. 5 is a flowchart showing a procedure of a program on a computer for generating a composite assignment statement list in the embodiment.

FIG. 6 is a diagram showing a data configuration of a drive destination list in the embodiment.

FIG. 7 is a configuration diagram of simulation execution means in the embodiment.

FIG. 8 is a configuration diagram of a simulation data generation unit of the functional simulation device according to the second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Simulation data generation means 12 Test data input means 13 Simulation execution means 14 Simulation result display means 21 Syntax analysis means 22 Assignment sentence list storage means 23 Synchronous assignment sentence selection means 24 Synthetic assignment sentence list storage means 25 Evaluation program generation means 26 Driving destination List generation means 27 Event selection means

Claims (4)

(57) [Claims] 1. A function simulation apparatus for simulating the operation of a logic device described using a function description language using an event driving method, wherein the function description in the function description language is parsed, and a logic device to be simulated is analyzed. Extract an assignment statement for assigning a signal value to a functional element constituting a component element, select an assignment statement to be assigned by the same synchronization signal among the extracted assignment statements, and collectively assign assignment statements having the same synchronization signal. It comprises a simulation data generation means for generating an evaluation program for evaluating Te, the simulation by the data generation means to generate an evaluation program group, start the evaluation program group generated by event-driven method, substituting in the functional description A function simulation device for evaluating a sentence. 2. A function simulation apparatus for simulating the operation of a logic device described using a function description language by using an event driving method, wherein a function description in the function description language is analyzed and a logic device to be simulated is analyzed. Extract an assignment statement for assigning a signal value to a functional element constituting a component element, select an assignment statement to be assigned by the same synchronization signal among the extracted assignment statements, and collectively assign assignment statements having the same synchronization signal. Simulation data generating means for generating an evaluation program to be evaluated and evaluated, and event selecting means for selecting only a synchronization signal event of the evaluation program among events for driving the evaluation program generated by the simulation data generating means. Generating an evaluation program group by the simulation data generating means Select the events that drive the evaluation program group by the previous SL event selection means as well as, said evaluation program assignment statement with a synchronizing signal during simulation run is performed only by an event corresponding synchronizing signal changes A functional simulation device. 3. A logic device implemented by using an event driving method.
Function simulation language
The function description of the logic device to be simulated
Assignment statement that analyzes the statement and assigns the signal value to the functional element to be configured
And the same synchronizing signal among the extracted assignment statements
Select an assignment statement to assign by using the same synchronization signal
Generates an evaluation program that evaluates assignment statements with
Generate an evaluation program group by using
Start the evaluation program group that is generated by,
A functional system characterized by evaluating an assignment statement in a functional description
Simulation method. 4. An evaluation program group is generated,
Select the event of the synchronization signal that drives the evaluation program group
When the simulation is executed, the
The evaluation program determines that the corresponding synchronization signal has changed.
Claims: Only performed by venting
3. The function simulation method according to 3.