JP4183035B2 - Design support apparatus, source code coverage method, and program thereof - Google Patents

Description

【００４１】
図９の例では、分岐先が５個、各分岐先が活性化された回数はそれぞれ１、０、０、０、２４、仮に偏りなく理想的にまんべんに各分岐先が活性化されたとすると各分岐先は５回ずつ活性化される。よって平均偏差は、（｜１−５｜＋｜０−５｜＋｜０−５｜＋｜０−５｜＋｜２４−５｜）／５＝（４＋５＋５＋５＋１９）／５＝７．６である。仮に分岐の活性化回数が２５回の乱数印加の結果、４、５、５、５、６だとすると、（｜４−５｜＋｜５−５｜＋｜５−５｜＋｜５−５｜＋｜６−５｜）／５＝（１＋０＋０＋０＋１）／５＝０．４となる。なお、この平均偏差値は値が小さくなればなるほど、偏りが無く、大きければ偏りがある、と認識できる。
【００４２】
上記コードカバレッジの処理は、シミュレーション中の分岐条件式の条件式の真偽の結果を逐一システムメモリに格納し、最終的に前記平均偏差の統計処理計算を行う、例えばＣ言語によるプログラミングで実現する。
【００４３】
コードカバレッジ解析手段は、１ビットもしくはビット幅を有するバス形式のレジスタやネット、ポートに関し前記平均偏差を算出し、偏りを解析する。図１０に、３ビットのレジスタに１２８回の乱数を印加して、結果取り得た値のリストを示す。仮に偏りなく、理想的にレジスタ値をまんべんに網羅したとすると、０００，００１，０１０，０１１，１００，１０１，１１０，１１１の値をそれぞれ１６回ずつとることが可能である。よって、平均偏差は、（｜１２０−１６｜＋｜２−１６｜＋｜０−１６｜＋｜０−１６｜＋｜６−１６｜＋｜０−１６｜＋｜０−１６｜＋｜０−１６｜）／８＝（１０４＋１４＋１６＋１６＋１０＋１６＋１６＋１６）／８＝２６である。
【００４４】
上記コードカバレッジの処理はシミュレーション中のレジスタやネットなどの内部変数の値を逐一システムメモリに格納し、最終的に前記平均偏差の統計処理計算を行う、例えばＣ言語によるプログラミングで実現する。
【００４５】
本発明に係るソースコードカバレッジ方法に対応する実施例として、図６のフロー図を示した。詳細な説明は前記に記した通りであるため、ここでは割愛する。
【００４６】
上述の実施形態において、コンピュータを、前記ハードウェア記述データ入力手段、前記レジスタ変数認識手段、前記乱数発生手段、前記コードカバレッジ解析手段として機能させるためのプログラムをアプリケーションソフトとして、ＣＤ−ＲＯＭ等の記録媒体に格納しておいてもよい。このようにすれば、ＣＤ−ＲＯＭ等の、該プログラムを記録するためのコンピュータ読み取り可能な可搬型記録媒体に該プログラム等を格納して売買したり、携帯することができるようになる。
【００４７】
【発明の効果】
以上、詳細に説明したように、本発明に係る設計支援装置、及びソースコードカバレッジ方法によれば、ロジックＢＩＳＴで実施される擬似乱数によるテストのシミュレーションがＲＴＬで実施可能となるので、ロジックＢＩＳＴにおける諸問題をＲＴＬの段階で確認可能となる。
また、乱数によって内部状態が常に０（初期値）であったり、条件分岐の分岐カバレッジが低い場合は、ロジックＢＩＳＴのテストで可制御性・可観測性の低下の原因であるため、従来故障シミュレーションを実行するまで判明しなかった可制御性・可観測性及びそれらの低下の要因がＲＴＬの段階で調査、判別可能である。
【００４８】
また、同様に条件分岐の分岐カバレッジが低い場合は、ＡＴＰＧ（Ａｕｔｏ Ｔｅｓｔ Ｐａｔｔｅｒｎ Ｇｅｎｅｒａｔｏｒ）におけるスキャンテスト量の増加を引き起こすので、ＲＴＬの段階でスキャンテスト量増加の要因を調査、判別可能である。
【００４９】
また、本例のコードカバレッジ解析手段によれば、特に条件分岐の分岐先の活性化頻度における偏りの度合いを解析するようにしたので可制御性・可観測性の低下の要因を容易に特定可能となる。たとえば、ｃａｓｅ文のｄｅｆａｕｌｔ、ｉｆ−ｅｌｓｅのｅｌｓｅの分岐先ばかりが活性化され、その他はほとんど活性化されない場合は、活性化されなかった信号ライン又は演算式の記述は制御不能であり、ＲＴＬの改善、修正が必要である。従来によるロジックＢＩＳＴでは、テストデータが擬似乱数であるために十分な故障検出率が得られないケースが多く、ゲートレベルのネットリスト中の可制御性、可観測性の悪い箇所にテスト回路を挿入する等による故障シミュレーションを実行するまで、ロジックＢＩＳＴで故障検出率の低下の要因であるＲＴＬ記述箇所が判明しなかったが、将来、上記コートカバレッジ解析手段によることで、ＲＴＬの段階で調査、判別可能である。
【００５０】
また、本例の、コードカバレッジ解析手段によれば、バス形式のレジスタ、ネット、ポートに関して乱数をテストデータにしたときのシミュレーション結果による変数のカバレッジが確認でき、さらに取り得た値の発生頻度が確認可能である。例えば、レジスタ値が常にオール０である場合は、当該レジスタに関わる演算式は、十分な可制御性、可観測性が得られない。従来によるロジックＢＩＳＴでは、テストデータが擬似乱数であるために十分な故障検出率が得られないケースが多く、故障シミュレーションを実行するまで、ロジックＢＩＳＴで故障検出率の低下の要因であるＲＴＬ記述箇所が判明しなかったが、将来、上記本例のコートカバレッジ解析手段によることで、ＲＴＬの段階で調査、判別可能である。
例えば、乱数を印可した結果、レジスタがＸ値をとるようであればＸ伝播の問題が発生していることを示し、従来ゲートレベルのネットリストにおいてのみ実施されていたＸ値伝播違反の確認がＲＴＬの段階で実施可能で、回路設計の早期に確認、対策、修正が可能となる。
【図面の簡単な説明】
【図１】本発明に係る設計支援装置の第１の構成図である。
【図２】レジスタトランスファレベルの機能記述データの一例とこれから作成されるパースツリーのイメージ図である。
【図３】処理フロー記述を展開したパースツリーのイメージ図である。
【図４】本発明に係る設計支援装置の第２の構成図である。
【図５】本発明に係る設計支援装置の第３の構成図である。
【図６】第１（図１）、第２（図４）、第３（図５）の構成図におけるコントローラによる主制御フロー図である。
【図７】記憶素子推量のための記述形式の例図である。
【図８】ｒｅｇ変数宣言した変数に対して同期されるクロックによるａｌｗａｙｓ文のｐｏｓｅｄｇｅ記述によるセンシティビティがある場合に、推量されるフリップフロップ図である。
【図９】ＶｅｒｉｌｏｇＨＤＬによる２５回の乱数印加の結果、分岐先の活性化頻度にに偏りが発生したＲＴＬの例図である。
【図１０】３ビットのレジスタに１２８回の乱数を印加して、結果取り得た値のリストである。
【図１１】乱数印加、クロック印加によるイベントをシミュレートした結果、内部変数や条件分岐活性化状況のとり込み、クロックの立ち上がりパルスの印加、前記クロックの印加によるイベントをシミュレートした結果による内部変数の状況のとり込み、以上を実施するタイミングをシミュレーション時刻の経過を横軸にとって示した図である。
【図１２】オペレータのタイプに関する識別子の割り当て例、レジスタ、ネット、ポートの識別に関する識別子の割り当て例、および識別子の割り当て例の図である。
【符号の説明】
１０１ メモリもしくはハードディスク
１０２ ＣＰＵ
１０３ キーボード・マウスなどの入力手段
１０４ ＣＲＴ
１０５ システムバス
４０１ 構文解析手段
４０２ レジスタ変数認識手段
４０３ 乱数発生手段
４０４ クロック生成手段
４０５ シミュレータ
４０６ コードカバレッジ解析手段
４０７ コントローラ
４０８ システムメモリ
４０９ システムバス
５０１ ＰＬＩ機構に含まれる構文解析手段
５０２ レジスタ変数認識手段
５０３ 乱数発生手段
５０４ クロック生成手段
５０５ コードカバレッジ解析手段
５０６ ＰＬＩ機構に含まれるシミュレータ
５０７ コントローラ
５０８ システムメモリ
５０９ 入力するＲＴＬの記述データ
５１０ パースツリー
５１１ テーブルもしくはリストからパースツリーへのポインタ参照
５１２ パースツリーを走査可能にするためのテーブルもしくはリスト
５１３ ＰＬＩ機構
５１４ ＶＰＩ Ｉ／Ｆ
５１５ コードカバレッジ解析結果のログ、もしくはＣＲＴへ出力されるべきメッセージ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a testability analysis and a testability analysis, and a testability design and a testability design apparatus. More specifically, the present invention relates to an architecture for testing a large-scale integrated circuit by a built-in logic self-test mechanism. The present invention relates to a design support apparatus, a source code coverage method, and a program for confirming a description that is difficult to detect a failure during hardware function description that does not depend on.
[0002]
[Prior art]
Details of the technique of the scan-based built-in self-test method (hereinafter referred to as logic BIST (Built-in-self-Test)) using pseudo-random numbers as test data is disclosed in Japanese Patent Laid-Open No. 5-241882 (Patent Document 1). Reference is made to Japanese Patent No. 2711492 (Patent Document 2). JP-A-11-85828 (Patent Document 3), JP-A 2000-215225 (Patent Document 4), JP-A-6-259596 (Patent Document 5) There is.
[0003]
Patent Documents 3 and 5 are support devices for the purpose of improving test quality using a user-created test bench. From the simulation results using the user's test bench, the state coverage and inactive state of the sequential circuit are determined. Warning.
[0004]
The above-mentioned patent document 4 examines data propagation from input to output based on a simulation result by a user-created test bench, and checks test facilitation.
[0005]
In the logic BIST, there is a case where a sufficient failure detection rate cannot be obtained because the test data is a pseudo random number. In particular, a multi-bit comparison arithmetic unit is a circuit (hereinafter referred to as a random resistant) that is difficult to detect a failure as a result of a test using a pseudo-random number. Even for an encoder or a circuit having nested conditional branch processing, if the test data is a pseudo-random number, a bias occurs in the conditional branch destination, and as a result, a circuit that is not tested remains.
[0006]
Conventionally, there is a technique for inserting a test circuit at a location where controllability and observability are poor in a gate-level netlist to solve such a problem. This is referred to USP 6,070,261 (Patent Document 6). However, this method has a problem that the circuit function, particularly the speed, is deteriorated due to the inserted test circuit. In the case of a large-scale circuit, there is a problem that the execution time becomes long in the controllability and observability analysis tool.
[0007]
In order to solve the above problems, for example, at the register transfer level (hereinafter referred to as RTL), a description portion where failure detection by logic BIST is difficult can be extracted, and a test circuit description can be added thereto. For example, a gate level netlist in which the above problem is addressed is obtained by logic synthesis.
[0008]
[Patent Document 1]
JP-A-5-241882
[Patent Document 2]
Japanese Patent No. 2711492
[Patent Document 3]
Japanese Patent Laid-Open No. 11-85828
[Patent Document 4]
JP 2000-215225 A
[Patent Document 5]
JP-A-6-259596
[Patent Document 6]
US Pat. No. 6,070,261
[0009]
[Problems to be solved by the invention]
However, in order to use the above solution, it is necessary to know in advance which description of the register transfer level (hereinafter referred to as RTL) is a random register.
[0010]
Therefore, an object of the present invention is to provide a design support apparatus that detects a random resistant description in the RTL, warns the designer, and supports RTL improvement for the logic BIST.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a design support apparatus according to the present invention includes means for inputting register transfer level hardware description data, and registers in which a memory element can be estimated by a logic synthesis system with respect to variables in the function description data. Register variable recognition means for recognizing a variable, random number generation means for applying a random number to the register variable recognized by the register variable recognition means, a simulator for simulating an event caused by the application of the random number, and a result of the simulation And code coverage analysis means for performing source code coverage analysis of hardware description data.
[0012]
In order to realize the design support apparatus, a computer is caused to function as the hardware description data input unit, the register variable recognition unit, the random number generation unit, and the code coverage analysis unit according to claim 1. It features a computer-readable recording medium on which a program is recorded.
[0013]
Further, the code coverage analysis means analyzes the bias of the activation frequency with respect to the activation rate of the branch processing relating to the conditional branch description described in the hardware description data.
[0014]
In addition, the code coverage analyzing means performs statistical processing on a change caused by a simulation result regarding a variable of a register or a net, and analyzes an occurrence frequency of the obtained value.
[0015]
In addition, a code coverage method for simulating register transfer level hardware description data and performing source code coverage analysis recognizes register variables whose storage elements can be inferred by the logic synthesis system with respect to variables in the function description data. A random number is applied to the register variable recognized by the register variable recognition means, and an event caused by the application of the random number is simulated.
[0016]
Further, the inventive step compared with Patent Documents 3, 4 and 5 is that the present invention aims to improve the test quality when the test data is a pseudo-random number in the scan-based test method. is there.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
FIG. The book invention Pertaining to The 1st block diagram of a design support apparatus is shown.
Reference numeral 101 denotes a memory or hard disk, which stores register transfer level (hereinafter referred to as RTL) function description data and each means of the present invention in the form of a program. Reference numeral 102 denotes a CPU (Central Processing Unit), which controls execution of the present invention. Reference numeral 103 denotes an input means such as a keyboard / mouse, which interactively inputs execution / execution instructions of a program that implements the hardware function description independent of architecture and each means of the present invention. Reference numeral 104 denotes a CRT, which displays a hardware function description that does not depend on the architecture, and a program execution progress and execution results that implement each means of the present invention. Reference numeral 105 denotes a system bus, which performs I / F for each of the components 101, 102, 103, and 104.
[0018]
If there are multiple operation expressions or conditional branch processing in the input RTL function description data, a parse tree is created for each operation, and the top node of each parse tree is stored in the form of a list or hash table in memory. It can be browsed and browsed. The RTL referred to here is, for example, VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) or Verilog HDL (Variable Hardware Description).
[0019]
FIG. 2 shows an example of function transfer data at the register transfer level and an image diagram of a parse tree created from this.
2A is an example of function description data at the register transfer level, FIG. 2B is an image of a parse tree that has been parsed from the description at the register transfer level and expanded on a memory or a hard disk, and FIG. Information stored in a structure format in each node on the tree is shown.
[0020]
The node of the parse tree stores variable operands and operators. The operand corresponds to a register or a net. The operator corresponds to the type of operation such as addition, subtraction, multiplication, and comparison. The node L in FIG. 2B is the top node of the parse tree for the left side of the arithmetic expression in the description data, and R is for the right side.
[0021]
In the structure of FIG. 2C, the file name is, for example, a C language char type array, and stores a file name that is function description data at the register transfer level. Line numbers are int type. The type stores an operator type or an identifier such as a register, net, or port. FIG. 12A shows an example of assigning identifiers related to operator types. In the table, SubOp indicates “−”, DivOp indicates “/”, AddOp, and MultiOp indicate “+” and “*” operations, respectively. FIG. 12B shows an example of assignment of identifiers relating to register, net, and port identification. When the node type is a register, net, or port, bit width information is also stored in the structure shown in FIG.
[0022]
The processing flow description in the RTL function description data is also stored in a parse tree format. The processing flow description corresponds to, for example, a Verilog_HDL case statement or an if-else conditional branch description.
FIG. 3 shows an image diagram of a parse tree in which the processing flow description is expanded. C in the figure is a node for storing a condition expression, that is, a reference pointer of a parse tree relating to a conditional expression, and the conditional expression similarly constitutes a parse tree. In the figure, y and n are nodes for storing reference pointers of parse trees related to operations executed when the conditions are true and false, respectively, and the operations to be executed constitute a parse tree. These parse trees are stored in the form of a list or a hash table on a memory, and can be browsed and browsed.
[0023]
FIG. The book The 2nd block diagram of the design support apparatus which concerns on invention is shown.
Reference numeral 401 denotes a syntax analysis unit that parses the input RTL function description data and expands it into a parse tree. The expanded parse tree is stored in the system memory 408 and can be referred to from each component via the system bus 409.
[0024]
Reference numeral 402 denotes a register variable recognizing unit that refers to a parse tree in 408, and among the register variables in the RTL, a storage element can be inferred. recognize. A random number generation unit 403 applies a random number to the register variable recognized in 402. Reference numeral 404 denotes clock generation means that controls the application of clock pulses. Reference numeral 405 denotes a simulator, which simulates changes in events caused by application of random numbers 403 and 404 and clock pulses. Changes in the variables in the RTL due to internal events caused by the simulation are sequentially stored on the parse tree nodes on 408.
[0025]
A code coverage analysis unit 406 analyzes the coverage of register variables, net and port variables in RTL description data input with reference to the simulation result stored in the parse tree on 408. Log output or display the result on the CRT. The code coverage analysis unit 406 performs coverage analysis on the branch destination activated by the simulation in the conditional branch description in the RTL description data, performs statistical processing, and activates the branch destination activation frequency of the conditional branch processing. Is analyzed, and the analysis result is output as a log or CRT. Reference numeral 407 denotes a controller that controls the entire system, such as the arrangement of processing procedures for each component and the transmission of processing instructions.
[0026]
The simulation means 405 may use a commercially available RTL simulator. CADENCE Corporation ( http: // www. cadence. com / [Search on December 24, 2002]), Verilog_XL and NC-Verilog, which are RTL simulators for Verilog HDL, are supplied. These simulators parse RTL description data and develop a parse tree on the system memory. The simulation is executed according to the test bench.
[0027]
CADENCE has a programming language interface (PLI) integration mechanism, and provides an access routine called Verilog Procedural Interface (VPI). According to this, it is possible to refer to the parse tree. In addition to the test bench, the access routine also includes a function for performing a simulation execution instruction applying a value to an internal variable, advancing the simulation time, and referring to the simulation result.
[0028]
FIG. 5 shows a register recognition means, a random number application means using a Verilog Procedural Interface (VPI) access routine of the Programming language interface (PLI) Integration mechanism using Verilog_XL or NC-Verilog of CADENCE as simulation means. When realized book of The 3rd block diagram of the design support apparatus which concerns on invention is shown.
[0029]
Reference numeral 513 denotes a PLI mechanism, and reference numeral 501 denotes syntax analysis means included in the PLI mechanism, which expands the input RTL description data into a parse tree and registers it in the system memory 508. Reference numeral 506 denotes a simulator included in the PLI mechanism, which can read and write a parse tree on 508.
[0030]
510 is a parse tree, 512 is a table or list for enabling scanning of the 510 parse tree, and 511 is a pointer reference from the table or list to the parse tree.
Reference numeral 514 denotes a VPI I / F that performs reference of a parse tree and simulation control by a VPI access routine. The register variable recognition unit 502, the random number generation unit 503, the clock generation unit 504, and the code coverage analysis unit 505 that can perform reference to the parse tree and simulation control via the VPI I / F are respectively VPI I / F. Reference to the parse tree and simulation control can be performed via
Note that 509 is input RTL description data, 515 is a code coverage analysis result log, or a message to be output to the CRT.
[0031]
FIG. 6 shows a main control flow by the controller in the first, second, and third configuration diagrams.
First, a register variable whose storage element can be guessed by scanning a parse tree is recognized (601), a random number is applied to the register variable (602), and an event due to the random number application is simulated (603). The internal variables (registers, nets, ports) and conditional branch activation statuses based on the simulation results are stored in the system memory (604). Subsequently, a clock is applied (605), an event due to the clock application is simulated, and the simulation time is advanced (606). The value of the internal variable based on the simulation result is stored in the system memory (607). The steps 602 to 607 are executed a plurality of times. For example, the number of times equivalent to the number of tests performed in the logic BIST is repeated. In addition, the number shown in () has shown the code | symbol added to each process shown in FIG.
[0032]
FIG. 11 shows a result of simulating an event due to application of a random number, an event due to the application, an internal variable or conditional branch activation status, an application of a rising pulse of the clock, and an event due to the application of the clock. The timing of the execution of the internal variable status by means of the simulation time is shown on the horizontal axis. In the figure, (1) is a random number application, (2) is a simulation result fetch, (3) is a clock application, and (4) is a simulation result fetch timing.
[0033]
Less than In An embodiment relating to a register recognition means will be described.
The logic synthesis system defines a description format for guessing the memory elements. The register recognition means also extracts the description format part of the storage element guess similar to the logic synthesis system by scanning the parse tree, and uses the register variable on the left side in the assignment expression related to the description format as the recognition result as the next process. To random number application means. FIG. 7 shows an example of a description format for the storage element guess in Verilog HDL.
If there is a sensitivity according to the posted description of the always statement by the clock synchronized with the variable declared in the reg variable, the flip-flop shown in FIG. 8 is inferred.
[0034]
Disorder Regarding the application of random numbers and clocks in the number generation means and the clock generation means, for example, Verilog HDL, there is a “force” command as a value forced application command. According to this, an arbitrary logical value can be applied to an arbitrary register, net, or port in the RTL. For example, if the simulator is Verilog XL or NC-Verilog, the random number can be obtained by the $ random () command. Alternatively, for example, when it is realized by programming in C language, it is obtained by a rand function. The random number generation means and the clock generation means may be configured in the form of a test bench using a force and $ random command.
[0035]
In the embodiment according to the third configuration diagram, a logical value can be set in a desired register or net by using the VPI access function vpi_put_value (). For example, when applying a random number to the register “A”, in C programming using the VPI access function vpi_put_value (), vpi_put_value (a node on the parse tree corresponding to the register “A”, rand (), simulation time); Can be described.
[0036]
When applying a pulse to the clock port “CK”,
vpi_put_value (node on parse tree corresponding to port “CK”, 1, simulation time 1);
vpi_put_value (node on the parse tree corresponding to port “CK”, 0, simulation time 2);
Can be described. In this case, a rising event is generated at CK at simulation time 1, and a falling event is generated at CK at simulation time 2. Note that the simulation execution of 603 and 605 is realized by advancing the simulation time given to the third argument of the vpi_put_value () function.
[0037]
Co The mode coverage analysis means can be realized by analyzing the dump file of the simulation result, but can refer to the value of the desired register or net in the third configuration and the truth of the conditional expression of the branch condition expression. Therefore, the internal variable and the activation status of the conditional branch processing based on the simulation results in 604 and 607 are extracted by scanning the parse tree and registering the internal state by the VPI access function vpi_get_value () for each register, net, or conditional branch node. And the truth of the conditional expression of the branch conditional expression is referred to and stored in the system memory. Since the node name in the parse tree stores the file name and line number of the RTL source, for example, the branch destination that has never been activated in the conditional branch process description has the file name and line as a result of the coverage being 0. Log output or message output to CRT along with the number.
[0038]
Co For example, when the register latches the X value, the managed coverage analysis means issues a warning to the log or CRT that an X value propagation violation has occurred.
Also, For example, when the register always takes 0 (initial value) only, the possibility of resetting may be considered as the cause, and the coverage analysis means issues a warning to the log or CRT.
Also, For example, if the variable of the conditional expression of the conditional branch does not toggle, the managed coverage analysis means issues a warning to the log or the CRT that the activation rate of the conditional branch destination is low.
[0039]
Also, The coverage analysis means analyzes whether or not the activation frequency of the branch destination to be activated is biased with respect to the conditional branch processing description in the RTL.
FIG. 9 shows an example of an RTL in which the activation frequency of the branch destination is biased as a result of applying random numbers 25 times by Verilog HDL. Reference numeral 901 indicates the number of times of activation.
[0040]
In order to express the bias numerically, for example, there is a means indicated by an average deviation. The average deviation represents the degree of deviation between the measured value and the average value, and is an average value of the sum of the “absolute value of the difference from the arithmetic average value”. When the number of valid cases is n, the measured value of each case is Xi (i = 1, 2,..., N), and the arithmetic average value is X bar, the following equation 1 is defined.
[Expression 1]

[0041]
In the example of FIG. 9, there are 5 branch destinations, and the number of times each branch destination is activated is 1, 0, 0, 0, 24, respectively. Assuming that each branch destination is activated five times. Therefore, the average deviation is (| 1-5 | + | 0-5 | + | 0-5 | + | 0-5 | + | 24-5 |) / 5 = (4 + 5 + 5 + 5 + 19) /5=7.6. . If the number of branch activations is 25, the result of random number application is 4, 5, 5, 5, 6 (| 4-5 | + | 5-5 | + | 5-5 | + | 5-5 | + | 6-5 |) / 5 = (1 + 0 + 0 + 0 + 1) /5=0.4. In addition, it can be recognized that the average deviation value is less biased as the value is smaller, and is biased when it is larger.
[0042]
The code coverage processing is realized by programming, for example, C language, which stores the true / false result of the conditional expression of the branch conditional expression in the simulation one by one in the system memory and finally calculates the statistical processing of the average deviation. .
[0043]
Co The mode coverage analysis means calculates the average deviation for a bus-type register, net, or port having 1 bit or bit width, and analyzes the deviation. FIG. 10 shows a list of values obtained by applying 128 random numbers to a 3-bit register. Assuming that the register values are ideally covered without any bias, the values of 000,001,010,011,100,101,110,111 can be taken 16 times each. Therefore, the average deviation is (| 120-16 | + | 2-16 | + | 0-16 | + | 6-16 | + | 0-16 | + | 0-16 | + | 0−16 |) / 8 = (104 + 14 + 16 + 16 + 10 + 16 + 16 + 16) / 8 = 26.
[0044]
The code coverage processing is realized by programming, for example, in C language, in which the values of internal variables such as registers and nets during simulation are stored in the system memory one by one, and the statistical processing of the average deviation is finally calculated.
[0045]
According to the present invention As an example corresponding to the source code coverage method, the flowchart of FIG. 6 is shown. Since the detailed description is as described above, it is omitted here.
[0046]
In the above embodiment, a computer Before A program for functioning as hardware description data input means, register variable recognition means, random number generation means, and code coverage analysis means may be stored in a recording medium such as a CD-ROM as application software. . In this way, the program or the like can be stored in a computer-readable portable recording medium for recording the program, such as a CD-ROM, and sold or carried.
[0047]
【The invention's effect】
As described above in detail, the present invention relates to the present invention. Set up Meter support equipment, and Biso According to the source code coverage method, simulation of pseudo random numbers performed in the logic BIST can be performed in the RTL, so that various problems in the logic BIST can be confirmed in the RTL stage.
Also, if the internal state is always 0 (initial value) due to random numbers or the branch coverage of the conditional branch is low, it is a cause of deterioration of controllability and observability in the logic BIST test. Controllability, observability, and the factors of their decrease that have not been revealed until after executing can be investigated and discriminated at the RTL stage.
[0048]
Similarly, when the branch coverage of the conditional branch is low, an increase in the scan test amount in ATPG (Auto Test Pattern Generator) is caused. Therefore, the cause of the increase in the scan test amount can be investigated and determined at the RTL stage.
[0049]
Also, Of this example According to the code coverage analysis means, in particular, the degree of bias in the activation frequency of the branch destination of the conditional branch is analyzed, so that it is possible to easily identify the cause of the decrease in controllability and observability. For example, if only the branch destination of the default of the case statement and the else of if-else is activated and the others are hardly activated, the description of the signal line or the arithmetic expression that has not been activated is uncontrollable, and the RTL Improvement and correction are required. In conventional logic BIST, test data is a pseudo-random number, so there are many cases where a sufficient failure detection rate cannot be obtained, and a test circuit is inserted in a controllable or unobservable part of the gate level netlist. Until the failure simulation was performed, the RTL description location that caused the failure detection rate decline was not found in the logic BIST. Writing By using the data coverage analysis means, it is possible to investigate and discriminate at the RTL stage.
[0050]
Also, This example According to the code coverage analysis means, it is possible to check the coverage of the variables based on the simulation results when random numbers are used as test data for the bus format registers, nets, and ports, and to check the occurrence frequency of the obtained values. For example, when the register value is always all 0, the arithmetic expression related to the register cannot obtain sufficient controllability and observability. In the conventional logic BIST, the test data is a pseudo-random number, so there are many cases where a sufficient failure detection rate cannot be obtained, and until the failure simulation is executed, the RTL description location that is the cause of the failure detection rate decrease in the logic BIST Was not found, but in the future, the above Of this example By using the coat coverage analysis means, it is possible to investigate and discriminate at the RTL stage.
For example, if a register takes an X value as a result of applying a random number, it indicates that an X propagation problem has occurred, and an X value propagation violation that has been performed only in the net list at the gate level has been confirmed. It can be implemented at the RTL stage, and confirmation, countermeasures, and corrections can be made early in circuit design.
[Brief description of the drawings]
FIG. 1 is a first configuration diagram of a design support apparatus according to the present invention.
FIG. 2 is an image diagram of an example of function description data at a register transfer level and a parse tree created from the example.
FIG. 3 is an image diagram of a parse tree in which a processing flow description is expanded.
FIG. 4 is a second block diagram of the design support apparatus according to the present invention.
FIG. 5 is a third block diagram of the design support apparatus according to the present invention.
6 is a main control flow chart by a controller in the first (FIG. 1), second (FIG. 4), and third (FIG. 5) configuration diagrams.
FIG. 7 is an example of a description format for a storage element guess.
FIG. 8 is a flip-flop diagram to be inferred when there is sensitivity according to a posure description of an always statement by a clock synchronized with a variable declared in a reg variable.
FIG. 9 is an example of an RTL in which a bias has occurred in the activation frequency of a branch destination as a result of applying random numbers 25 times by Verilog HDL;
FIG. 10 is a list of values obtained by applying 128 random numbers to a 3-bit register.
FIG. 11 shows the result of simulating an event due to random number application and clock application, taking in an internal variable and conditional branch activation status, applying a clock rising pulse, and simulating an event due to the clock application. It is the figure which showed progress of the simulation time on the horizontal axis | shaft about the timing of taking in the situation of, and implementing the above.
FIG. 12 is a diagram of an identifier assignment example regarding an operator type, an identifier assignment example regarding register, net, and port identification, and an identifier assignment example;
[Explanation of symbols]
101 Memory or hard disk
102 CPU
103 Input means such as keyboard and mouse
104 CRT
105 System bus
401 Syntax analysis means
402 Register variable recognition means
403 Random number generation means
404 Clock generation means
405 simulator
406 Code coverage analysis means
407 controller
408 system memory
409 system bus
501 Syntax analysis means included in PLI mechanism
502 Register variable recognition means
503 Random number generation means
504 Clock generation means
505 Code coverage analysis means
506 Simulator included in PLI mechanism
507 controller
508 System memory
509 RTL description data to be input
510 parse tree
511 Pointer reference from table or list to parse tree
512 Table or list to make the parse tree traversable
513 PLI mechanism
514 VPI I / F
515 Log of code coverage analysis result or message to be output to CRT

Claims (5)

Means for inputting function description data at the register transfer level;
Regard variables in the functional description data, recognizing register variable recognition means register variables that storage element is allocated by logic synthesis system,
Random number generating means for applying a random number to the register variable recognized by the register variable recognizing means;
A simulator for simulating the events caused by the application of the random number, and a code coverage analysis means for performing source code coverage analysis functional description data according to the results of the simulation Yes,
The code support analysis unit analyzes a bias in activation frequency with respect to an activation rate of a branch process related to a conditional branch description described in function description data . Means for inputting function description data at the register transfer level;
Register variable recognition means for recognizing a register variable to which a memory element is assigned by a logic synthesis system with respect to the variable in the function description data;
Random number generating means for applying a random number to the register variable recognized by the register variable recognizing means;
A simulator for simulating an event caused by the application of the random number; a code coverage analysis means for performing source code coverage analysis of function description data based on the result of the simulation;
Have
The code coverage analysis means performs statistical processing on a change caused by a simulation result with respect to a register or a net variable, and analyzes the occurrence frequency of the obtained value. A program for causing a computer to function as each means in the design support apparatus according to claim 1 . A computer-readable recording medium on which the program according to claim 3 is recorded. Simulate the hardware description data of register transfer level, it met code coverage method of performing source code coverage analysis,
As means for executing programmed computer processing, each means in the design support apparatus according to claim 1 or 2 is provided,
3. A source code coverage method, comprising: executing each process in the design support apparatus according to claim 1 by each means provided.

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