JPH06259495A - Logic simulation system - Google Patents

Abstract

PURPOSE:To obtain an exact simulation result by controlling the execution sequence of an operation description model in a prescribed sequence. CONSTITUTION:A simulation executing part 7 operates the logic simulation of a simulation object logic circuit by using the logic data of a table expression stored in a simulation execution form file 3 and input data from a simulation data file 4. Then, at the time of the simulation processing, the part of the execution form of gate level logic description data(logic gate model) in the logic data is processed by a logic gate processing part 8, and the part of the execution form of an operation description data(operation description model) is processed by an operation description language processing part 9. At that time, the execution sequence of an event from the logic gate model to the operation description model generated at the same time is controlled by an execution sequence control part 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method for a digital logic circuit, and more particularly to a logic simulation method for a behavioral description model described in a behavioral description language.

[0002]

2. Description of the Related Art In general, a logic simulation for performing logic verification of a logic circuit is performed by a hardware model based on a logic gate connection description written in a gate level logic description language and an operation description model written in a register transfer level logic description language. It is performed using a logic simulation device capable of handling and.

As a conventional technique relating to this type of logic simulation, for example, a technique described in Japanese Patent Laid-Open No. 1-266676, "Logic Simulation Device" is known.

[0004]

Generally, when performing a logic simulation process of a logic simulation model consisting of a logic gate connection description part and a plurality of behavior description model parts, a plurality of behavior description models are obtained at a certain simulation time. Events may occur at the same time. In this case, the processing order of each behavioral description model is uncertain because it is performed in the event occurrence order.

Therefore, the above-mentioned conventional technique has a problem that the simulation result becomes inaccurate when the processing order between the behavioral description models is restricted.

An object of the present invention is to solve the above-mentioned problems of the prior art, and when an event occurs simultaneously in a plurality of behavioral description models at a certain simulation time, a predetermined simulation processing order of the behavioral description models is set. An object of the present invention is to provide a logic simulation method that can be controlled in order and can obtain accurate simulation results.

[0007]

According to the present invention, the above object is to provide a logic gate model described by a gate connection description language for describing a connection relation of logic gates and a logic operation of a change in a signal state by a programming language or the like. When multiple events occur in the behavioral description model from the logic gate model at the same simulation time in the logic simulation against the logic simulation model consisting of the described behavioral description model, the processing order of each behavior description model is set before the simulation starts. Means to specify,
This is achieved by providing means for holding the execution order and means for processing each behavior model according to the order specified when the simulation is executed.

[0008]

When the execution order of each behavioral description model is designated before the execution of the logic simulation, the execution order is held in the storage device. Then, when an event occurs in a plurality of behavioral description models at the same simulation time during simulation execution, the events for each behavioral description model are sequentially executed according to the held execution order.

According to the present invention, since the execution order of the behavioral description models can be controlled in a predetermined order in this manner, for example, data is passed between the behavioral description models and the behavioral description models are exchanged. An accurate logical simulation result can be obtained even when performing simulation on a logical simulation model in which the simulation result differs depending on the execution order of.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a logic simulation system according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a logic simulation processing apparatus according to an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a logic circuit to be simulated, and FIG. 3 is a circuit representation of the circuit of FIG. 2 in a logic gate model. FIG. 4 is a diagram illustrating an information table in which the circuit of FIG. 2 is represented by a behavioral description model, FIG. 5 is a diagram illustrating an execution order table of the behavioral description model, and FIG. 6 is an operation. FIG. 7 is a diagram illustrating a description example of a description model, FIG. 7 is a diagram illustrating a simulation time and an event table, FIG. 8 is a flowchart illustrating a processing operation of sorting an event table, and FIG. 9 is a work table before sorting processing. FIG. 10 is a diagram for explaining the contents of the work table after the sorting process, and FIG. 11 is a diagram for explaining the contents of the event table after the sorting process. Akira figures, FIG. 12 is a flowchart for explaining the execution operation of the logic simulation. 1 and 2, 1 is a logic simulation processing device, 2 is a logic description file, 3 is a simulation execution format file, 4 is a simulation data file, 5 is a simulation result file, 6 is a logic compiling unit, and 7 is a simulation executing unit. , 8 is a logic gate processing unit, 9 is a behavioral description language processing unit, 10 is an execution order control unit, 20 is a simulation target logic circuit, A, B and C.
Is an AND gate, and X and Y are LSIs (Large Scale Integrated Circuits).

In the embodiment of the present invention shown in FIG. 1, the logic simulation processing apparatus 1 is configured to include a logic compiling unit 6 and a simulation executing unit 7 as main components, and data of each file described below. Perform a logical simulation by referring to.

In the logic description file 2, gate level logic description data described in a gate connection description language (gate level logic description language) for describing a connection relation of logic gates of a simulation target circuit, and a logic operation due to a signal change are described. It stores behavioral description data described in a programming language or the like. These logical description data are converted into logical data of a table expression suitable for simulation by the logical compiling unit 6 and stored in the simulation execution format file 3.

Also, the simulation data file 4
Contains the microprograms, test programs, input / output signal values from the outside required to operate the logic circuit to be simulated, and each behavior description when an event occurs from the logic gate model to multiple behavior description models at the same time. Stores the model execution order.

Then, the simulation executing unit 7 uses the logic data represented by the table stored in the simulation execution format file 3 and the input data from the simulation data file 4 to perform a logic simulation of the simulation target logic circuit.

In the above-mentioned simulation processing, the execution form (logic gate model) portion of the gate level logic description data in the logic data is processed by the logic gate processing section 8 and the execution form (behavior description model) portion of the behavioral description data. Is processed by the behavioral description language processing unit 9. At this time, the events from the logic gate model to the behavioral description model that occur at the same time are executed by the execution order control unit 10
Controls the order of execution.

The simulation executing section 7 uses the logical data stored in the simulation executing file 3 to change the input data stored in the simulation data file 4 as many times as necessary, unless the logical description data is changed. A logic simulation of the circuit to be simulated can be performed. The simulation result is stored in the simulation result file 5, then edited and output as a list from a printer device (not shown), and is displayed on a terminal device (not shown) such as a video display.

As an example for explaining an embodiment of the present invention, FIG.
The simulation target logic circuit 20 shown in (1) is a combination logic circuit of three AND gates A, B, and C and two LSIs (large-scale integrated circuits) X and Y. Of these, LSI
The internal operation of X and Y is described by a programming language, and the other parts are described by a gate level logic description language. Also, the logic circuit 20 is converted by the logic compiling unit 6 into logic data in a table expression suitable for simulation, and converted into a format that can be processed by the logic simulation processing device 1.

A logic circuit table 21 of logic data in which the logic description data of the logic circuit 20 of FIG.
Are stored in the logical description file 2 and have a configuration as shown in FIG. This logic circuit table 21
, Gate name 22, function 23, first input signal name 24,
The signal value 25, the second input signal name 26, the signal value 2
7, a column for holding each data of the output signal value name 28, its signal value 29, and the behavioral description model connection flag 2A is provided.

In the column of gate name 22, data of a name for identifying each logic gate, in this example, A, B and C are held as the names of AND gates. In the column of function 23,
Functions such as AND, OR, and EOR for each logic gate are assigned to the first input signal name 24 and the second input signal name 26.
The input signal name of the logic gate is held, and the signal value 25 and the signal value 27 hold the signal value of each input signal.
The column of the output signal name 28 holds the output signal name of the logic gate, and the signal value 29 holds the signal value of the output signal.

For example, in the illustrated example, the logic gate A is ANDed.
A gate, and the input signals of the AND gate are s1 having a signal value of "0" and s2 having a signal value of "1", and
The output signal of the AND gate indicates that the signal value is s3 of "0". Also, the connection destination of this gate is
The behavioral description model connection flag 2A is turned ON only when the behavioral description model of the simulation target logic circuit is used.
It is said that This flag 2A makes it possible to know whether or not the event has propagated to the behavioral description model.

The table for storing the information of the behavioral description model shown in FIG. 4 is stored in the logic description file 2, and the information indicating the behavior of the LSIs X and Y is stored therein. As shown in FIG. 4, the behavior description model information table 2
B is the behavior description model name 2C, signal name 2D, signal value 2E
The columns for holding the respective data are provided.
The behavior description model name 2C holds data of a name that identifies each behavior description model. The signal name 2D column holds the signal name connected to the behavioral description model, and the signal value 2E column holds the signal value of the signal.

In this example, the behavior description model name 2C is L
The behavior description model LSI holds SI names X and Y.
X includes a signal s3 (signal value "0") and a signal s4 (signal value "1"), a signal s5 (signal value "0"), a signal s6 (signal value "0"), a signal s8 (signal value " 1 ") is connected.

The execution order table 30 shown in FIG. 5 is stored in the simulation data file 4 and indicates the execution order of each behavioral description model when events to a plurality of behavioral description models occur at the same time. It's a table. As shown in FIG. 5, the behavioral description model execution order table 30 is provided with columns indicating a behavioral description model name 31 and an execution order 32 of the behavioral description model. The execution order table 30 is created by the user in advance, stored in the simulation data file 4, and stored in the memory of the logic simulation processing device before the simulation is executed.

In this execution order table, only one surface is provided, assuming that the execution order of events is common to all simulation times.

The example of the behavioral description model shown in FIG. 6 is an example of the behavioral description model in which the logic behavior of the simulation target logic circuit 20 is described in a behavioral description language. In this example, the logic description is based on the command sequence 40. Here is an example. In this example, the LSI of the logic circuit 20 shown in FIG.
The logical operations of X and LSI Y are described.

In the simulation process of the logical operation by the command of this operation description language, if the condition described by the ON command is satisfied, the process described by the EX command is executed (after the designated time elapses), and the logical operation of the logical operation is executed. It shows performing a logical simulation. Therefore,
This operation description model is described by a set of ON command and EX command, and the command 41 and the command 42 indicate the operation of the LSI X, and the command 43 and the command 44 indicate the operation of the LSI Y.

Then, the conditional expression "s1 | s" of the ON command
2 ”indicates that the condition is satisfied when the signal value of either the signal s1 or the signal s2 changes, and when the condition of the ON command 41 is satisfied, the signal of the signal s5 is processed in the processing of the next EX command 42. Set the value to "1" and set the signal s6
It is shown that the process of setting the signal value of "0" and the signal value of the signal value s8 to "1" is performed.

That is, the LSI X is an AND gate A
When the signal value of the output signal s3 of the signal or the signal s4 from the terminal changes, the signal value of the signal s5 to the terminal is set to "1" and the signal value of the signal s5 to the AND gate B is set to "0". , And the signal value of the signal s8 to the LSI Y is set to "1". Similarly, command 43 and command 44
Describes the operation of LSI Y.

Such a behavioral description model is executed by the behavioral description language processing unit 9 in the embodiment of the present invention shown in FIG. In the above description, an example of a simple behavioral description model described by ON commands and EX commands has been described for convenience, but it is possible to describe more complicated logical behaviors by using a more advanced logical behavioral description language. Needless to say.

FIG. 7 shows a simulation time management table and an event table for each simulation time.
These relationships are shown. These tables are provided in the simulation executing unit 7. The simulation time management table 51 has records for all simulation times. The address of the event table 52 in which all the events to be processed at the simulation time are registered is stored in each record.

In the example shown in FIG. 7, only the event table 52 at the simulation time T is shown.
Event table 52 for all simulation times
There is an event table similar to.

As shown in FIG. 7, the event table 52
Includes a signal name 53 to be an event processing target, a signal value 54 thereof, and a column for holding the behavioral description model name 53 when the event is an event to the behavioral description model of the simulation target logic circuit. .

In the fields of signal name 53 and signal value 54, the signal name of the event processed at the simulation time and the signal value of the signal are stored. Further, in the field of the behavior description model name 55, when the event is an event to the behavior description model of the simulation target logic circuit, the behavior description model name is stored, and when the event is not an event to the behavior description model. "-1" is stored in.

In the example shown in FIG. 7, at the simulation time T, an event to the non-behavioral description model that sets the signal value of the signal s1 to "0", and to the behavioral description model Y that sets the signal value of the signal s9 to "1". Event of the non-behavior description model in which the signal value of the signal s11 is “1”, the signal s3
It is shown that there is an event to the behavioral description model X having a signal value of “0” and a non-behavioral description model having a signal value of the signal s13 of “0”.

Such an event table is created based on the information of the logic circuit table 21 described with reference to FIG. 3 and the behavioral description model information table 2B described with reference to FIG.

Next, referring to the flow shown in FIG.
The processing operation of rearranging the events of the behavioral description model performed by the execution order control unit 10 at each simulation time will be described.

(1) The behavior description model name 53 of the event table at the corresponding simulation time is searched from the first record to the last record (step 61).

(2) The behavior description model name of the event obtained as a result of the search in step 61 and the behavior description model name 31 of the execution order table 30 are compared, and the event to be executed at this simulation time is the execution order table. Thirty
Check whether it is specified in. If not specified, the process is terminated without rearranging the events at this simulation time (step 62).

(3) In step 62, the event to be executed at this simulation time is the execution order table 30.
, All the events are extracted to the work table 66 shown in FIG. 9, and all the events are deleted from the event table 52. In the example of FIG. 9, the behavioral description model Y and the behavioral description model X registered in the execution order table 30 from the event table 52.
Is extracted into the work table 66 (step 63).

(4) Next, the events extracted in the work table 66 are rearranged according to the execution order 32 registered in the execution order table 30. As a result,
A work table 67 having contents as shown in 0 is obtained (step 64).

(5) Finally, the event in the work table 67 whose rearrangement has been completed in step 64 is added to the end of the event table at this simulation time.
As a result, the event table 52 described with reference to FIG.
Is rewritten into the event table 68 as shown in FIG. 11 (step 65).

Next, the processing performed by the simulation executing unit 7 using the logic simulation method according to the embodiment of the present invention that enables the rearrangement of events as described above will be described with reference to the flow shown in FIG. To do.

(1) First, referring to the simulation data file 4, the logic table 21, and the behavioral description model information table, an input value is applied to the simulation target logic circuit, and an event table is created for each simulation time. (Step 71).

(2) In step 71, when the creation of the event table for each simulation time is completed, in order to sequentially execute the simulation processing for each simulation time, as described in detail in FIG. Sort events (step 7)
2).

(3) Next, the events in the event table at the current time are sequentially processed from the beginning of the event table. At this time, the logic gate model is the logic gate processing unit 8
The behavioral description model is processed by the behavioral description language processing unit 9. (Step 73).

(4) Further, the events generated by these event processes are registered in the event table of the corresponding simulation time (step 74).

(5) The event table at the current simulation time is searched again to check whether any unprocessed events remain. If any unprocessed events remain, the event processing is performed and the generated event is re-evented. Register in the table (steps 75, 76, 74).

(6) The processing of steps 74, 75, and 76 is repeatedly executed until there are no unprocessed events in the event table at the current simulation time, and when the processing of all the events at a certain time is completed, the simulation is performed. Advance time by one, step 72
The processes from 1 to 7 are repeatedly executed (steps 77 and 78).

(7) The above-mentioned processing is executed until the end of the simulation time, and the entire simulation processing is completed. The result obtained by this simulation is stored in the simulation result file 5.

According to the above-described embodiment of the present invention, it is possible to specify the execution order of each behavioral description model before the execution of the logic simulation, whereby a plurality of behavioral description models can be executed at the same simulation time during simulation execution. When an event occurs in, each behavioral description model can be executed sequentially according to the specified order.

Therefore, according to one embodiment of the present invention, for example, for a logical simulation model in which data is passed between the behavioral description models and the simulation result differs depending on the execution order of the behavioral description models. An accurate logic simulation result can be obtained even when performing a simulation.

[0053]

As described above, according to the present invention, when an event occurs in a plurality of behavioral description models at the same simulation time, the simulation processing order of each behavioral description model is controlled in a predetermined order. It is possible to obtain accurate simulation results.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a logic simulation processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a simulation target logic circuit.

FIG. 3 is a diagram illustrating a logic circuit table in which the circuit of FIG. 2 is expressed by a logic gate model.

4 is a diagram illustrating an information table in which the circuit of FIG. 2 is represented by a behavioral description model.

FIG. 5 is a diagram illustrating an execution order table of a behavioral description model.

FIG. 6 is a diagram illustrating a description example of a behavioral description model.

FIG. 7 is a diagram illustrating a simulation time and an event table.

FIG. 8 is a flowchart illustrating a processing operation of rearranging an event table.

FIG. 9 is a diagram illustrating the contents of a work table before rearrangement processing.

FIG. 10 is a diagram illustrating the contents of a work table after a rearrangement process.

FIG. 11 is a diagram illustrating the contents of an event table after a rearrangement process.

FIG. 12 is a flowchart illustrating an execution processing operation of a logic simulation.

[Explanation of symbols]

 1 logic simulation processing device 2 logic description file 3 simulation execution format file 4 simulation data file 5 simulation result file 6 logic compiling unit 7 simulation executing unit 8 logic gate processing unit 9 behavioral description language processing unit 10 execution sequence control unit 20 simulation target logic Circuit A, B, C AND gate X, Y LSI (Large scale integrated circuit)

Claims (1)

[Claims] 1. A logic simulation model composed of a plurality of behavioral description models described by a logic gate model by a gate connection description language that describes a connection relation of logic gates and a behavioral description language that describes a logical behavior of a change in a signal state. In the logic simulation processing method, when the logic simulation processing is executed, if an event occurs in a plurality of behavioral description models at the same simulation time, the events of each behavioral description model are sequentially processed according to a predetermined order. A logic simulation method characterized by.