JP2000181942A - Automatic i/o buffer operation power source check system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically check an I/O buffer operation power source. SOLUTION: An LSI pin assignment 21, an LSI logic net list 22 and an I/O buffer block library 23 stored by a storage device 2 are read by the respectively corresponding read means 11 and 12 of a data processor 1, the consistency of an I/O buffer operation power source level and a supply power source is checked by a power source level check means 13 for each I/O net of an object to be inspected and the checked collation result is outputted to the storage device 2 as a collated result 24. By the procedure, the consistency of a base supply power source and the I/O buffer operation power source is automatically checked without manual aid and the I/O design quality of the various kinds of power source operation LSIs is improved. Also, since the consistency is confirmed not by a back end but by the front end of logic design, the retrogression of design correction is reduced, power source inconsistency is detected more quickly and the design is quickly corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic I / O buffer operation power supply check system for automatically checking an I / O buffer operation power supply.

[0002]

2. Description of the Related Art Heretofore, a check of an I / O buffer operation power supply is generally performed manually. Therefore, there is no system corresponding to the automatic I / O buffer operation power supply check system of the present invention. Also, in an I / O logic design of a multi-power supply operation LSI, a system for checking whether or not a buffer operated by the power supply is used in a base I / O area corresponding to each power supply, and Such a system does not exist in the back-end system.

Therefore, it is necessary to carefully connect the interface block to the external terminal corresponding to the underlying I / O area, and to check the consistency by visually comparing the netlist with the underlying information.

As a conventional example 1 having a similar technical content of the present invention, there is “Test Circuit and Test Method for Microcomputer” in JP-A-8-272639. The conventional example 1 relates to a screening test using an LSI tester, and has a single terminal used only as an output terminal during normal operation as an input terminal for setting a test mode and a test circuit of a microcomputer using the output buffer thereof. And technology related to test methods.

[0005]

However, in the above-mentioned prior art, since the checking operation is performed manually, there is a problem that in the worst case, there is a possibility that the work is paid out to the manufacturing process in an inconsistent state. Note that the above publication examples differ in the symmetry of the check.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an automatic I / O buffer operation power supply check system capable of automatically checking an I / O buffer operation power supply.

[0007]

In order to achieve the above object, an automatic I / O buffer operation power supply check system according to the present invention uses an LSI pin assignment, an LSI logical netlist, an I / O buffer block library, and a comparison result. The storage device to be stored, the LSI pin assignment, and the LSI logical netlist are read, the I / O buffer operation power supply level and the consistency of the supply power are checked for each I / O net, and the result of this check is compared. And a data processing device that outputs the result to a storage device.

Further, the above-mentioned LSI pin assignment corresponds to each LS
The terminal name and terminal information for the I external terminal are data stored in advance for each LSI type, and the LSI logical netlist is data storing the gate level netlist of the LSI before physical design. The O-buffer block library may be data storing the operating characteristics of the I / O buffer.

Further, the above data processing device may be an LSI
A pin assignment reading means for reading the pin assignment and setting the information in an internal table;
The SI logical netlist is read, and the I / O of the internal table already constructed by the pin assignment reading means is read.
Based on the O-net, the type of the I / O buffer used in the I / O interface section of the net list is specified,
And a logical netlist reading means for setting an information item for checking in an internal table with reference to the / O buffer block library.

The above data processing apparatus includes a power supply level checker for checking the consistency between the I / O buffer operation power supply level and the supply power supply for each I / O net in the internal table and outputting the result as a comparison result. It is good to have it further.

The information items are, for example, an I / O buffer name, an I / O buffer instance name, and an operation power supply level. The LSI pin assignment may be external pin information of an LSI linked to the background information. .

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of an automatic I / O buffer operation power supply check system according to the present invention will be described with reference to the accompanying drawings. 1 to 10, there is shown a diagram for explaining a configuration of an embodiment of an automatic I / O buffer operation power supply check system according to the present invention.

Referring to FIG. 1, an embodiment of an automatic I / O buffer operation power supply check system according to the present invention includes a data processing device 1 having a computer which operates under program control, and a method for storing information permanently. And a storage device 2 using a hard disk for storing the information.

The storage device (hard disk) 2 is subdivided according to the type of information stored in the storage device.
The stored information includes an LSI pin assignment 21 and an LSI
The comparison includes a logical netlist 22 and an I / O buffer block library 23, and is performed on the collation result 24 as an output destination of a collation result based on the information.

The LSI pin assignment 21 stores, for each LSI external terminal, a terminal name, an I / O net name, and a power supply level of a base I / O area for each LSI type.

The LSI logical netlist 22 stores a gate level netlist of the LSI before physical design.

I / O buffer block library 23
Stores the operation characteristics and the like of the I / O buffer.

For example, the consistency of the power supply level is output to the collation result 24 which stores the collation result provided in the area in the storage device 2.

The data processing apparatus 1 constituted by a computer or the like is further subdivided and includes a pin assignment reading means 11, a logical net list reading means 12, and a power level checking means 13.

The pin assignment reading means 11 is an LSI
The pin assignment 21 is read, and the information is set in an internal table.

The logical netlist reading means 12 stores the L
The SI logical netlist 22 is read, and the type of the I / O buffer used in the I / O interface of the netlist is determined based on the I / O net of the internal table already constructed by the pin assignment reading means 11. Identify and refer to the I / O buffer block library 23 and set information items for checking in the internal table. This information item is, for example, an I / O buffer name,
The I / O buffer instance name and the operating power level.

The power level checking means 13 checks the I / O buffer operating power level for consistency with the supplied power for each I / O net in the internal table, and outputs the result as a comparison result 24. Each of these means operates as follows.

(Explanation of Operation) Next, an example of the overall operation of the present embodiment will be described in detail with reference to the configuration diagram of FIG. 1 and the flowcharts of FIGS. 2 to FIG. 5 show the basic processing procedure in FIG.
3, 4, and 5 each show a more detailed processing procedure example of steps A1, A2, and A3.

The LSI pin assignment 21 provided from the storage device 2 is supplied to the pin assignment reading means 11 (step A1). Pin assignment reading means 11
Reads the file line by line (step B1) and repeats the next step (B2 to B3) until the end of the file. The line is analyzed to extract the I / O net name and the power supply level field of the base I / O area (step B2).
The power supply level of the base I / O area is set to I
The / O net name is stored in the internal table as a key (step B3).

Next, the LSI logical netlist 22 given from the storage device 2 is supplied to the logical netlist reading means 12 (step A2). The logical netlist reading means 12 reads one instance at a time (step C1), and continues to the next step (C2) until the end of the file.
To C4) are repeated. In these steps, the net connected to the instance is the I / O of the internal table.
Check whether it exists as a net. That is, it is checked whether the instance is an I / O buffer (step C2).

If the I / O net does not exist in the internal table, the instance immediately returns to step C1 because the instance is a normal logical block. I / in the internal table
If it exists as an O-net, the I / O of the netlist
I / O buffer block library 23 from buffer name
To obtain the operating power supply level (step C3). Then, the I / O buffer name, the instance name, and the operating power level are stored in the record corresponding to the currently focused I / O net in the internal table (step C4).

Next, the internal table is provided to the power supply level checking means 13 (step A3). For the record corresponding to each of the I / O nets which are the keys of the internal table, the next step (D2 to D
3) is repeated (step D1).

The power supply level of the base I / O area of the internal table is compared with the power supply level of the I / O buffer operation (step D2). As a result of this collation, if there is a mismatch at the end, the I / O net name, the base supply power level, the I / O buffer name, the operation power level, and the instance name are output to the collation result 24 (step D3).

Next, a specific example will be described. For example,
The LSI pin assignment 21 is prepared in advance in a configuration as shown in FIG. 6, and is input by spreadsheet software. In FIG. 6, the terminal names in column A and the power supply in column C are linked to the background information and are automatically input. Now, it is assumed that this is given from the storage device 2 to the pin assignment reading means 11.

Using the I / O net name in column B as a key for associative storage, the base power supply in column C is stored in an internal table (A,
(B column) (step B3).

Next, as shown in FIG. 7, for example, a gate-level LSI logic netlist 22 is created by a front-end tool such as logic synthesis. Now, this is the logical netlist reading means 1 from the storage device 2.
Suppose that it was given to 2.

Looking at the ninth line in FIG. 7, the net names connected to the instances are AIN [0] and A [0]. It is checked whether or not these exist as the I / O net name (column A in FIG. 9) of the internal table key (step C).
2). A [0] exists in column A, row 4, and the instance is I
Since the I / O buffer is determined to be an I / O buffer, the operation power supply (VOLTAG) is referred to by using the I / O buffer = IBUF as a key and referring to the I / O buffer block library in FIG.
E) = 3.3V is acquired (step C3). After this,
I / O buffer name = IBUF, instance name = I0,
Operating power supply = 3.3 V is stored in the internal table (C column 4 rows in FIG. 9,
(D column, 4 rows, E column, 4 rows) (step C4). Thereafter, similar processing is repeated for the entire netlist.

Finally, the power level check means 13
The power level consistency is checked based on the internal table shown in FIG. Focusing on the sixth row, the B-column base supply power is 3.
Since the 3V and E column operation power supply is 2.5V and is inconsistent, as shown in FIG.
[2], base supply power = 3.3 V, I / O buffer name =
IBUF2, operating power supply = 2.5V, instance name = I
2 is output (step D3). A similar process is performed on the entire internal table.

In the above embodiment, the operating power supply of the I / O buffer in the logical netlist of the LSI and the I / O
It is configured as an automatic I / O buffer operation power supply check system for checking the consistency with the power supply in the O area. In this configuration, a pin assignment, which is external pin information of the LSI linked to the base information, is prepared in advance, and the operation power level of the I / O buffer can be checked in the logic design phase.

In FIG. 1, the LSI pin assignment 21
Holds the correspondence between the terminal name, the power supply level of the terminal position on the base, and the I / O net name for each external terminal. The I / O net name indicates a net name that connects an external terminal to the I / O buffer. Power level check means 13
Is the operating power supply (I) of the connected I / O buffer for each I / O net in the LSI logical netlist 22.
/ O buffer block library 23) and the power supply level of the LSI pin assignment 21 corresponding to the I / O net.

In this way, it is possible to check the consistency between the supply power of the underlying I / O area and the operation power of the I / O buffer.

The above embodiment is an example of a preferred embodiment of the present invention. However, it is not limited to this.
Various modifications can be made without departing from the spirit of the present invention.

[0038]

As is clear from the above description, the I / O buffer operation power supply automatic check system according to the present invention has the LS
The I-pin assignment, the LSI logical netlist, the I / O buffer block library, and the collation result are stored in the LSI.
Read pin assignment and LSI logic netlist,
The consistency between the I / O buffer operation power supply level and the supply power is checked for each I / O net, and the checked result of the check is output to the storage device as a check result.

Therefore, the consistency between the base supply power and the I / O buffer operation power can be automatically checked without manual operation.
For this reason, the I / O design quality of the multi-power supply operation LSI can be improved. Also, consistency can be confirmed at the front end of the logical design, not at the back end. For this reason, the number of regressions of the design correction is reduced, and the mismatch of the power supply can be detected earlier and the design can be corrected quickly.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an automatic I / O buffer operation power supply check system of the present invention.

FIG. 2 is a flowchart illustrating an operation example of the embodiment of the present invention.

FIG. 3 is a partial processing procedure 1 of the flowchart in FIG. 2;

FIG. 4 is a partial processing procedure 2 of the flowchart in FIG. 2;

FIG. 5 is a partial processing procedure 3 of the flowchart in FIG. 2;

FIG. 6 is a chart of an LSI pin assignment showing a specific example of the operation.

FIG. 7 is an LSI logical netlist showing a specific example of operation.

FIG. 8 is an I / O buffer block library showing a specific example of the operation.

FIG. 9 is an internal table image diagram showing a specific example of the operation.

FIG. 10 is a diagram illustrating a configuration example of a comparison result indicating a specific example of an operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data processing device (computer) 2 Storage device (hard disk) 11 Pin assignment reading means 12 Logical net list reading means 13 Power supply level checking means 21 LSI pin assignment 22 LSI logical net list 23 I / O buffer block library 24 Matching result

Claims (6)

[Claims] 1. A storage device for storing an LSI pin assignment, an LSI logical netlist, an I / O buffer block library, and a comparison result, and reading the LSI pin assignment and the LSI logical netlist, and A data processing device for checking the consistency between the I / O buffer operation power supply level and the supply power, and outputting the checked result of the check to the storage device as the check result. I / O buffer operation power supply automatic check system. 2. The LSI pin assignment is data in which a terminal name and terminal information of each LSI external terminal are stored in advance for each LSI type. The I / O buffer operation according to claim 1, wherein the I / O buffer operation is data storing a netlist, and the I / O buffer block library is data storing operation characteristics of the I / O buffer. Automatic power check system. 3. The data processing device reads a pin assignment of the LSI and sets the information in an internal table. The type of the I / O buffer used in the I / O interface section of the net list is specified based on the I / O net of the internal table, and the I / O buffer block library is referred to, and the internal table is referred to. 3. A logical netlist reading means for setting an information item for checking, comprising:
2. The automatic I / O buffer operation power supply check system according to 1. 4. The power supply level checking means for checking the consistency between an I / O buffer operation power supply level and a supply power supply for each I / O net in an internal table and outputting the result as a collation result. The I / O according to claim 3, further comprising:
O buffer operation power supply automatic check system. 5. The I according to claim 3, wherein the information items are, for example, an I / O buffer name, an I / O buffer instance name, and an operation power supply level.
/ O buffer operation power supply automatic check system. 6. The automatic I / O buffer operation power supply check system according to claim 2, wherein the LSI pin assignment is external pin information of an LSI linked to background information.