JP2004013851A - Lsi design support system and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a burden when an interface part of an LSI (large scale integrated circuit) is designed. <P>SOLUTION: In terminals 1, external information 3, internal information 4 and library information 5 of the LSI are read from a database, and the external information 3, the internal information 4 and the library information 5 are used to automatically generate an I/F information table with design information of the interface part recorded thereon. When automatically generating the I/F information table, an external signal is made to correspond to an internal signal, a buffer to be disposed between the both signals is determined, and the both signal names are made to correspond to the determined buffer and recorded in the I/F information table. In the buffer determination, buffers in which at least a calculated value of a time delay is smaller than an expected value are selected among buffers recorded in the library information, and the buffer having the smallest calculated value is further selected among the selected buffers. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an LSI design support system that supports the design of an interface between an internal circuit and an external circuit of an LSI, and a program used for the system.
[0002]
[Prior art]
Conventionally, the basic design process of an LSI is to first create specifications, divide the inside of the LSI into blocks for each function, determine the processing and data flow between each block, and then design the internal circuit of the LSI. I do. Next, in order to design an interface (I / F) circuit between an internal circuit of the designed LSI and an external circuit on a substrate on which the LSI is mounted, an internal / external circuit for determining a correspondence relationship of connection pins between the two circuits is designed. Perform link processing. Then, this is verified and an I / F circuit is designed.
[0003]
In designing an I / F circuit, a designer extracts information on connection pins on a board on which an LSI is mounted from CAD data for the board, or makes predictions or assumptions.
[0004]
[Problems to be solved by the invention]
However, since the scale of the I / F circuit has been increased with the recent increase in the scale of the LSI, an enormous amount of work time has been spent on the design of the I / F circuit, and the burden on the designer has been increased. As this adverse effect, human error is likely to occur.
[0005]
SUMMARY OF THE INVENTION The present invention has been made in view of the above, and an object of the present invention is to provide an LSI design support system and a program used for the LSI design support system, which can reduce the burden when designing an I / F circuit. It is in.
[0006]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided an LSI design support system comprising: storage means for storing external information, internal information, and library information of an LSI; and an interface portion of the LSI using the external information, the internal information, and the library information. Generating means for generating the design information.
[0007]
According to the present invention, the external part information, the internal information, and the library information of the LSI are read out from the storage means, and the design information of the interface part is automatically generated by using the information. Since the time is shortened and the work by manual input is reduced, the burden on the designer can be reduced, and human errors can be reduced.
[0008]
According to a second aspect of the present invention, in the above-described LSI design support system, the generation unit associates an external signal name and an internal signal name of the LSI using the external information and the internal information, A buffer to be arranged between signals is determined, and the design information is generated by recording both signal names and the determined buffer names in association with each other.
[0009]
In the present invention, a buffer to be arranged between an external signal and an internal signal is determined, and design information is generated by recording both signal names and the determined buffer names in association with each other.
[0010]
According to a third aspect of the present invention, in the LSI design support system, the buffer is determined from among buffers recorded in the library information, the calculated delay time being smaller than an expected value. It is characterized by.
[0011]
According to a fourth aspect of the present invention, in the LSI design support system, the buffer is determined by determining a buffer having a minimum calculated value among buffers having a calculated delay time smaller than an expected value. .
[0012]
According to the third and fourth aspects of the present invention, among the buffers recorded in the library information, at least the calculated value of the delay time is smaller than the expected value, and Is determined as a buffer to be arranged in the interface part, so that an appropriate buffer is applied.
[0013]
In a fifth aspect of the present invention, in each of the above-mentioned LSI design support systems, the external information is board information on a board on which the LSI is installed.
[0014]
In a sixth aspect of the present invention, in the above-mentioned LSI design support system, the board information is at least one of a data list and a circuit diagram.
[0015]
According to the fifth and sixth aspects of the present invention, by using a data list and / or a circuit diagram that can be automatically generated in designing a board as the external information, a task of creating the external information is performed. To reduce human error.
[0016]
According to a seventh aspect of the present invention, in each of the above-described LSI design support systems, the internal information uses at least one of a system description language or a circuit diagram.
[0017]
According to the present invention, by using a system description language and / or a circuit diagram that can be automatically generated in LSI design as internal information, the task of creating internal information is reduced, and Mistakes are reduced.
[0018]
According to an eighth aspect of the present invention, in each of the above-mentioned LSI design support systems, there is provided output means for outputting design information of the interface portion in a predetermined format.
[0019]
In the present invention, the design information of the interface portion is output in a predetermined format, so that the work when using the design information is reduced, and the human error is reduced.
[0020]
A ninth aspect of the present invention is the above-mentioned LSI design support system, wherein the predetermined format is at least one of a system description language and a circuit diagram.
[0021]
According to the present invention, the design information of the interface portion is output in a system description language, a circuit diagram, or both, so that the design information can be used quickly and easily.
[0022]
An LSI design support program according to a tenth aspect of the present invention provides a read processing for reading out external information, internal information, and library information of a LSI from storage means for storing the information, and using the external information, the internal information, and the library information. And a generation process for generating design information of an interface portion of the LSI.
[0023]
An eleventh aspect of the present invention is the LSI design support program, wherein the generation processing associates an external signal name with an internal signal name using the external information and the internal information, and uses the library information to create a relationship between the two signals. The design information is generated by deciding a buffer to be arranged in the, and recording both signal names and the decided buffer name in association with each other.
[0024]
In a twelfth aspect of the present invention, in the above-mentioned LSI design support program, the buffer is determined from among buffers recorded in the library information, wherein the calculated delay time is smaller than an expected value. It is characterized by.
[0025]
According to a thirteenth aspect of the present invention, in the above-described LSI design support program, the determination of the buffer is performed by determining a buffer having a minimum calculated value among buffers having a calculated delay time smaller than an expected value.
[0026]
A fourteenth invention is characterized in that, in each of the above-mentioned LSI design support programs, the external information is board information on a board on which the LSI is installed.
[0027]
According to a fifteenth aspect of the present invention, in the above-mentioned LSI design support program, at least one of a data list and a circuit diagram is used as the board information.
[0028]
According to a sixteenth aspect of the present invention, in each of the above-described LSI design support programs, the internal information uses at least one of a system description language or a circuit diagram.
[0029]
According to a seventeenth aspect of the present invention, in each of the above-mentioned LSI design support programs, a computer executes an output process of outputting design information of the interface portion in a predetermined format.
[0030]
An eighteenth aspect of the present invention is the above-mentioned LSI design support program, wherein the predetermined format is at least one of a system description language and a circuit diagram.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0032]
FIG. 1 is a block diagram showing an overall configuration of an LSI design support system according to one embodiment. The system shown in the figure has a configuration in which a terminal 1 for executing an LSI design support program and a database storing various information are connected via a network 7.
[0033]
As the terminal 1, a computer such as a personal computer 1a or an EWS (engineering workstation) 1b is used. The database includes information on the board on which the LSI is mounted (hereinafter referred to as "external information") 3, information on the inside of the LSI (hereinafter referred to as "internal information") 4, and information on interfaces such as buffers used between the LSI and the board. Information (hereinafter, “library information”) 5 is stored.
[0034]
As the external information 3, board information automatically generated when a board is designed by CAD or the like is used. The board information is represented by, for example, a data list shown in FIG. 2 or a circuit diagram shown in FIG.
[0035]
As the internal information 4, LSI information automatically generated when the inside of the LSI is designed by CAD or the like is used. The LSI information is represented by a system description language such as VHDL, Verilog, SystemC, and SpecC, or a circuit diagram of the LSI portion as shown in FIG.
[0036]
The library information 5 includes types of the external signal and the internal signal, information on the buffer shown in FIG. 4, and the like. 2A shows information on an input buffer, FIG. 2B shows information on an output buffer, and FIG. 2C shows information on an input / output buffer.
[0037]
The memory of the terminal 1 stores a design support program for supporting the design of the interface between the LSI and the board. The terminal 1 executes the program by the CPU to read the external information 3, the internal information 4, and the library information 5 from the database, and uses the information to design interface information (hereinafter referred to as “I / F information”). ) And a process of outputting the I / F information 6 in a predetermined format such as a system description language or a circuit diagram.
[0038]
The external information 4, the internal information 5, the library information 5, and the I / F information 6 may be stored separately in separate databases, or may be stored in a single database.
[0039]
FIG. 5 is a flowchart showing an overall outline of the I / F circuit design support processing by the present system. In this process, predetermined items are sequentially input into blanks of the I / F information table shown in FIG. 14 by an external information input process (step 1), an input buffer determination process (step 2), and an output buffer determination process (step 3). In the I / F information output process (step 4), the I / F information is output as a file or a circuit diagram described in a system description language based on the completed I / F information table. Hereinafter, the processing in each step will be described in detail.
[0040]
[1. External information input processing]
This process is a process for inputting external information to the I / F information table and for matching with the internal information, and can switch between manual input and automatic input.
[0041]
FIG. 6 is a flowchart showing an example of the external information input processing by manual input. First, the operator specifies the input line by inputting the Pin number of the I / F information table using the terminal 1, and determines whether the signal of the Pin number is power (VDD) or GND (VSS). (Steps 11 to 12). If it is power supply or GND, input VDD or VSS in the power supply column of the I / F information table. If it is not power supply or GND, determine whether an external signal name has been determined or whether an internal signal name has been determined. It is determined (steps 13 and 14).
[0042]
If the external signal name is determined and the internal signal name is also determined, the external signal name is input to the external signal name column of the I / F information table, and the internal signal name is input to the internal signal name column. (Step 15).
[0043]
If the external signal name is determined and the internal signal name is not determined, the external signal name is input to the external signal name column of the I / F information table, the internal signal name is determined, and the internal signal name is determined. Input (step 16).
[0044]
If the external signal name has not been determined and the internal signal name has been determined, the external signal name is determined and input to the external signal name column of the I / F information table, and the internal signal name is entered in the internal signal name column. (Step 17).
[0045]
If the external signal name has not been determined and the internal signal name has not been determined, the external signal name is determined and input to the external signal name column of the I / F information table, and the internal signal name is determined and the internal signal name is determined. Input into the signal name column (step 18).
[0046]
After the processes of steps 11 to 18 have been executed for all the pins of the LSI, the consistency between the external signal name and the internal signal name is confirmed (step 19). If the matching has not been achieved, the process returns to step 11 and the above processing is repeated. If the matching has been confirmed for all the pins, this processing ends. As a result of this processing, the I / F information table enters a state in which external information consistent with the internal information has been input, as shown in an example in FIG.
[0047]
FIG. 7 is a flowchart showing an example of the external information input processing by automatic input. Here, an agreement is previously defined between the external signal name and the internal signal name. Specifically, if an internal signal is used for input, it is represented by a character string “internal signal name” = “I” + “external signal name”, and if an internal signal is used for output, “internal signal name” = It is represented by “O” + “external signal name”. If the internal signal is used for both input and output, it is represented as "internal signal name" = "Bl" + "external signal name".
[0048]
First, the terminal 1 reads the Pin number and the external signal name from the board information in the order of the Pin numbers, substitutes the Pin number into the variable PinNo, and substitutes the external signal name into the variable OutName (steps 21 to 23). Next, the terminal 1 determines whether the external signal name is power supply or GND, and if it is power supply or GND, the Pin No. of the I / F information table is determined. Enter the Pin number in the column and VDD or VSS in the power supply column (steps 24 to 25). On the other hand, if the external signal name is not power supply or GND, the pin number is input in the Pin No column of the I / F information table, and the external signal name is input in the external signal name column (step 26).
[0049]
Subsequently, the terminal 1 reads the internal signal name and the I / O type from the internal information, substitutes the I / O type for the variable IOType, and substitutes the internal signal name for the variable InName (steps 27 to 29).
[0050]
The terminal 1 compares the internal signal name with “I” + “external signal name” if the I / O type of the internal signal is input, and proceeds to step 33 if they are equal. If the I / O type of the internal signal is output, the internal signal name is compared with "O" + "external signal name". If the I / O type of the internal signal is bidirectional, the internal signal name is compared with “BI” + “external signal name”, “BO” + “external signal name”, “BEN” + “external signal name”, If any one of them is equal, the process proceeds to step 33 (steps 30 to 32). In step 33, the terminal 1 inputs the I / O type read from the internal information in the I / O type column of the I / F information table, and in step 34, inputs the internal signal name in the internal signal name column.
[0051]
The processes in steps 28 to 34 are performed for all internal signals, or repeated until the correspondence between all external signal names and internal signal names matches. When this process ends, the process returns to the step 21, and when the processes of the above-mentioned steps 21 to 34 have been executed for all the external signals, this process ends. As a result of this processing, the I / F information table is in a state where external information that is consistent with the internal information is input, as shown in FIG. 15, as in the case of manual input.
[0052]
[2. Input buffer determination processing]
In this process, information necessary for determining an input buffer of an interface portion of an LSI is collected in an I / F information table, an appropriate input buffer is determined using this information, and the input buffer name is stored in the I / F information table. This is entered in the buffer name field.
[0053]
FIG. 8 is a flowchart showing an overall outline of the input buffer determination process. First, referring to the library information, the types of the external signal and the internal signal are added to the I / F information table shown in FIG. 15 (step 41). Here, the type indicates whether or not the clock is a clock, whether or not it is a Schmitt, whether or not there is a pull resistor, and if there is a pull resistor, whether it is a pull-up resistor or a pull-down resistor, CMOS or TTL. FIG. 16 shows an example of the I / F information table at this time. This additional processing may be performed manually or the terminal 1 may automatically input.
[0054]
Subsequently, the terminal 1 selects one external signal from the I / F information table, and determines whether or not the input signal input from the external circuit to the internal circuit is a clock (step 42). In the case of the clock, the processing for the high drive type described later is performed, and in the case of not the clock, the processing for the standard drive type described later is performed (steps 43 and 44). Subsequently, a process for a pull resistor to be described later is performed (step 45). Then, the input buffer name for the external signal and the internal signal is determined, and the input buffer name is input to the buffer name column of the I / F information table. When the processing in steps 42 to 45 has been performed for all the input signals, the present processing ends. Hereinafter, the processing of steps 43, 44, and 45 will be described in detail.
[0055]
FIG. 9 is a flowchart showing an example of the process for the high drive type in step 43. First, the terminal 1 determines whether an input signal is a CMOS level or a TTL level using an I / F information table. In the case of the TTL level, the input type of the input buffer is determined to be the TTL level input buffer (steps 51 to 52). On the other hand, in the case of the CMOS level, it is determined whether or not it is a Schmitt trigger type (step 53). In the case of the Schmitt trigger type, the input type of the input buffer is determined to be the Schmitt trigger CMOS level input buffer.
[0056]
FIG. 10 is a flowchart showing an example of the process for the standard drive type in step 44. First, the terminal 1 determines whether the input signal is a CMOS level or a TTL level using the I / F information table (step 56). In the case of the TTL level, it is determined whether or not it is a Schmitt trigger type. In the case of the Schmitt trigger type, the input type of the input buffer is determined as the Schmitt trigger TTL level input buffer, and in the case of not the Schmitt trigger type, the input type is determined as the TTL level input buffer (steps 57 to 59). On the other hand, if it is determined at step 56 that the input signal is of the CMOS level, it is determined whether or not the input signal is of the Schmitt trigger type. In this case, a CMOS level input buffer is determined (steps 60 to 62).
[0057]
FIG. 11 is a flowchart illustrating an example of the processing regarding the pull resistance in step 45. The terminal 1 uses the I / F information table to determine whether there is a pull resistor and, if there is a pull resistor, whether it is a pull-up resistor or a pull-down resistor (step 63). In the case of a pull-up resistor, the input type of the input buffer is optionally provided with a pull-up, in the case of a pull-down resistor, a pull-down is provided, and when there is no pull resistor, no option is provided (steps 64 to 66).
[0058]
Next, the input buffer determination process will be described using a specific example. Here, a description will be given of a process in which the terminal 1 determines a buffer name for the external signals I1 to I4 shown in the I / F information table of FIG. 16 and inputs the buffer name to the buffer name column of the I / F information table.
[0059]
1. First, the terminal 1 checks whether or not the external signal I1 is a clock. Here, the external signal I1 is a clock from the I / F information table of FIG.
[0060]
2. Next, it is checked whether the external signal I1 is at the CMOS level or the TTL level. From the I / F information table of FIG. 16, the external signal I1 is at the CMOS level.
[0061]
3. Next, it is checked whether the external signal I1 is a Schmitt trigger. From the I / F information table in FIG. 16, the external signal I1 is not a Schmitt trigger.
[0062]
4. Next, the pull resistance of the external signal I1 is examined. From the I / F information table of FIG. 16, the external signal I1 has no pull resistance.
[0063]
5. The terminal 1 determines the input type of the external signal I1 to be a high drive type CMOS level input buffer by the above-described processes 1 to 4. There is no optional pull resistor.
[0064]
6. Subsequently, the terminal 1 checks whether or not the external signal I2 is a clock. From the I / F information table of FIG. 16, the external signal I1 is not a clock.
[0065]
7. Next, it is checked whether the external signal I2 is at the CMOS level or the TTL level. From the I / F information table of FIG. 16, the external signal I2 is at the CMOS level.
[0066]
8. Next, it is checked whether the external signal I2 is a Schmitt trigger. From the I / F information table in FIG. 16, the external signal I2 is not a Schmitt trigger.
[0067]
9. Next, the pull resistance of the external signal I2 is examined. From the I / F information table of FIG. 16, a pull-up resistor is attached to the external signal I2.
[0068]
10. Through the above processes 6 to 9, the terminal 1 determines the input type of the external signal I2 to be a standard drive type CMOS level input buffer. A pull-up resistor is added as an option.
[0069]
11. Subsequently, the terminal 1 checks whether or not the external signal I3 is a clock. From the I / F information table of FIG. 16, the external signal I3 is not a clock.
[0070]
12. Next, it is checked whether the external signal I3 is at the CMOS level or the TTL level. From the I / F information table in FIG. 16, the external signal I3 is at the CMOS level.
[0071]
13. Next, it is checked whether or not the external signal I3 is a Schmitt trigger. From the I / F information table in FIG. 16, the external signal I3 is a Schmitt trigger.
[0072]
14． Next, the pull resistance of the external signal I3 is examined. From the I / F information table of FIG. 16, no pull resistance is attached to the external signal I3.
[0073]
15. Through the processes 11 to 14, the terminal 1 determines the input type of the external signal I3 to be a standard drive type Schmitt trigger CMOS level input buffer. Do not attach an optional pull resistor.
[0074]
16. Subsequently, the terminal 1 checks whether or not the external signal I4 is a clock. From the I / F information table of FIG. 16, the external signal I4 is not a clock.
[0075]
17. Next, it is checked whether the external signal I4 is at the CMOS level or the TTL level. From the I / F information table in FIG. 16, the external signal I4 is at the TTL level.
[0076]
18. Next, it is checked whether or not the external signal I4 is a Schmitt trigger. From the I / F information table of FIG. 16, the external signal I4 is not a Schmitt trigger.
[0077]
19. Next, the pull resistance of the external signal I4 is examined. According to the I / F information table of FIG. 16, the external signal I4 has no pull resistance.
[0078]
20. Through the above processes 16 to 19, the terminal 1 determines the input type of the external signal I4 to be the standard drive type TTL level input buffer. Do not attach an optional pull resistor.
[0079]
21. Subsequently, using the library information about the input buffer shown in FIG. 4A, a buffer name corresponding to the input type of each external signal determined in the above-described processing of 1 to 20 is extracted, and the I / F information table is extracted. In the buffer name field. FIG. 17 shows an example of the state of the I / F information table when the input buffer determination processing has been completed.
[0080]
[3. Output buffer determination process]
In this processing, information necessary for determining an output buffer for an interface portion of an LSI is collected in an I / F information table, an appropriate output buffer is determined using this information, and the output buffer name is stored in the I / F information table. Is input in the buffer name field of the.
[0081]
FIG. 12 is a flowchart illustrating an example of the overall outline of the output buffer determination process. First, referring to the library information 5, the expected values of the wiring capacity and the delay time are added to the I / F information table shown in FIG. 17 (step 71). FIG. 18 shows an example of the I / F information table at this time. There are two types of expected values of the delay time, when the signal changes from low to high (L → H) and when the signal changes from high to low (H → L). Note that this additional processing may be performed manually or may be performed automatically by the terminal 1.
[0082]
Subsequently, the terminal 1 selects one external signal from the I / F information table, determines an appropriate output buffer using the library information (step 72), and sets the output buffer name in the buffer name column of the I / F information table. (Step 73). When the processing of steps 72 to 73 has been performed for all external signals, this processing ends. Hereinafter, the process of step 72 will be described in detail.
[0083]
FIG. 13 is a flowchart illustrating an example of a process for determining an output buffer. First, the terminal 1 selects one external signal from the I / F information table shown in FIG. 18 and also selects one first output buffer from the library information of the output buffer shown in FIG. 4B (step 81). . Next, the delay time of the output buffer is calculated using the expected value of the load capacity recorded in the I / F information table for the external signal (step 82). For this calculation, for example, a calculation formula provided by a semiconductor vendor or the like is used. Next, the calculated value of the delay time is compared with the expected value (step 83). If the calculated values for both L → H and H → L are smaller than the expected values, the process proceeds to step 84; otherwise, the process proceeds to step 90.
[0084]
In step 84, the difference between the expected value and the calculated value for both L → H and H → L (result 1 for L → H and result 2 for H → L) is determined. The sum of these two differences (result 1 + result 2) is registered as a comparison value. The name of the output buffer at that time is registered in the sub-buffer, and the process proceeds to the calculation of the next output buffer (steps 85 to 91). In the second and subsequent calculations, the comparison value already registered is compared with the sum of newly calculated results 1 and 2. If the sum is smaller, the comparison value is updated with that value, and the sub-buffer is updated with the output buffer at that time (steps 85 to 89). The above processing is repeated until the output buffer becomes the last one (step 90).
[0085]
If the output buffer has been registered in the sub-buffer after the above processing for the last output buffer is completed, the final output buffer is determined as the output buffer and registered in the buffer. If no output buffer is registered in the sub-buffer, error processing is performed (steps 92 to 94).
[0086]
Subsequently, the next external signal is selected from the I / F information table, and the processes in steps 81 to 94 are performed. When the above processing is completed for all the external signals, the present processing ends. Each output buffer name registered in the buffer is used for input processing to the buffer name column in step 73 described above.
[0087]
Next, the output buffer determination process will be described using a specific example. Here, a process in which the terminal 1 determines an output buffer for the external signals O1 to O4 and B1 shown in the I / F information table of FIG. 18 and inputs the buffer name to the buffer name column of the I / F information table. explain.
[0088]
1. First, the terminal 1 selects the first output buffer for the external signal O1 from the information library of the output buffer shown in FIG.
[0089]
2. The expected value of the wiring capacitance of the external signal O1 is substituted into a predetermined formula to calculate the delay time for both L → H and H → L.
[0090]
3. The calculated value of the delay time is compared with the expected value, and if the calculated value is smaller than the expected value for both L → H and H → L, the difference between the calculated value and the expected value is determined.
[0091]
4. Obtain the sum of the two differences, register the value as a comparison value, and register the output buffer at that time in the sub-buffer.
[0092]
5. The next output buffer is selected from the information library, the above processes 2 and 3 are performed, and the sum of the two differences is obtained. If this sum is smaller than the registered comparison value, the comparison is performed using this sum. Update the value and update the subbuffer with the current output buffer.
[0093]
6. The above process 5 is repeated until the last output buffer is reached, and the name of the output buffer finally registered in the buffer is input to the buffer name column for the external signal I1 in the I / F information table.
[0094]
7. The above processes 1 to 6 are also performed on the external signals O2 to O4 and B1. However, for the external signal B1, the library information of the input / output buffer shown in FIG. 4C is used instead of the library information of the output buffer. FIG. 19 shows an example of the state of the I / F information table when the output buffer determination processing has been completed.
[0095]
[4. Output processing of I / F information]
In this process, the terminal 1 outputs I / F information in a predetermined format using the I / F information table completed by the above processes. The output format is, for example, a system description language or a circuit diagram. 20 and 21 show the contents of a series of output files showing I / F information in VHDL of the system description language. FIG. 22 shows the contents of a file indicating an external additional capacity, and FIG. 23 shows the contents of a file indicating a Pin No, a signal name, and a buffer name. FIG. 24 is an example of a circuit diagram showing I / F information.
[0096]
Therefore, according to the present embodiment, the design information of the interface part is automatically generated as an I / F information table using the external information, the internal information, and the library information of the LSI, thereby shortening the design work time. It is possible to reduce the number of operations by manual input and reduce human error.
[0097]
According to the present embodiment, the buffer to be arranged in the interface portion of the LSI is determined, and the buffer name is recorded in the I / F information table in association with the external signal name and the internal signal name, thereby designing the interface portion. Information can be generated accurately.
[0098]
According to the present embodiment, among the buffers recorded in the library information, those having at least the calculated value of the delay time smaller than the expected value, and those having the smallest calculated value among the buffers, are used for the interface part. In this case, an appropriate buffer can be applied.
[0099]
According to the present embodiment, by using a data list or a circuit diagram that can be automatically generated when designing a board as external information of an LSI, the work of creating external information can be reduced, and Mistakes can be reduced.
[0100]
According to this embodiment, a system description language or a circuit diagram that can be automatically generated when designing an LSI is used as the internal information of the LSI. Mistakes can be reduced.
[0101]
According to the present embodiment, the design information of the interface part recorded in the I / F information table is output in a system description language or a circuit diagram, so that the design information can be used quickly and easily. .
[0102]
【The invention's effect】
According to the LSI design support system and the program according to the present invention, by automatically generating the design information of the interface part of the LSI, the work time for designing the interface part is reduced, and the work by manual input is reduced. Therefore, the burden on the designer can be reduced, and human errors can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an LSI design support system according to one embodiment.
FIG. 2 is a data list showing an example of board information.
FIG. 3 is a circuit diagram illustrating an example of board information.
FIG. 4 is a diagram illustrating an example of library information relating to a buffer;
FIG. 5 is a flowchart illustrating an example of an overall outline of an I / F circuit design support process.
FIG. 6 is a flowchart showing an example of external information input processing by manual input.
FIG. 7 is a flowchart showing an example of external information input processing by automatic input.
FIG. 8 is a flowchart illustrating an example of an overall outline of input buffer determination processing.
FIG. 9 is a flowchart illustrating an example of a process for a standard drive type.
FIG. 10 is a flowchart illustrating an example of a process for a standard drive type.
FIG. 11 is a flowchart illustrating an example of processing for a pull resistor.
FIG. 12 is a flowchart illustrating an example of an overall outline of an output buffer determination process.
FIG. 13 is a flowchart illustrating an example of a process for determining an output buffer.
FIG. 14 is a diagram illustrating an example of an initial state of an I / F information table.
FIG. 15 is a diagram illustrating an example of a state of an I / F information table after an external information input process is completed.
FIG. 16 is a diagram illustrating an example of a state of an I / F information table immediately after starting an input buffer determination process;
FIG. 17 is a diagram illustrating an example of a state of an I / F information table after an input buffer determination process has been completed;
FIG. 18 is a diagram illustrating an example of a state of an I / F information table immediately after starting output buffer determination processing.
FIG. 19 is a diagram illustrating an example of a state of an I / F information table after an output buffer determination process has been completed;
FIG. 20 is a diagram illustrating an example of an output file when I / F information is output in a system description language.
FIG. 21 is a diagram showing a subsequent portion of the output file.
FIG. 22 is a diagram illustrating an example of a file indicating an external additional capacity.
FIG. 23 is a diagram illustrating an example of a file indicating a Pin No, a signal name, and a buffer name.
FIG. 24 is a diagram illustrating an example when I / F information is output in a circuit diagram.
[Explanation of symbols]
1 terminal
3 external information
4 inside information
5 Library information
6 Interface part design information
7 Network

Claims (18)

Storage means for storing external information, internal information, and library information of the LSI;
Generating means for generating design information of an interface portion of an LSI using the external information, the internal information, and the library information;
An LSI design support system comprising: The generating unit associates an external signal name and an internal signal name of the LSI using the external information and the internal information, determines a buffer to be arranged between the two signals using the library information, and 2. The LSI design support system according to claim 1, wherein the design information is generated by recording the determined buffer name in a corresponding manner. 3. The LSI design support system according to claim 2, wherein said buffer is determined from among buffers recorded in said library information, among buffers whose calculated delay time is smaller than an expected value. 4. The LSI design support system according to claim 3, wherein the determination of the buffer determines a buffer having a minimum calculated value among buffers having a calculated delay time smaller than an expected value. 5. The LSI design support system according to claim 1, wherein said external information is board information on a board on which an LSI is installed. 6. The LSI design support system according to claim 5, wherein at least one of a data list and a circuit diagram is used as the board information. 7. The LSI design support system according to claim 1, wherein the internal information uses at least one of a system description language and a circuit diagram. 8. The LSI design support system according to claim 1, further comprising an output unit that outputs the design information of the interface part in a predetermined format. 9. The LSI design support system according to claim 8, wherein the predetermined format uses at least one of a system description language and a circuit diagram. A reading process for reading out external information, internal information, and library information of the LSI from storage means for storing the information;
A generation process of generating design information of an interface portion of an LSI using external information, internal information, and library information;
An LSI design support program for causing a computer to execute the following. In the generation processing, the external signal and the internal signal are associated with the external signal name and the internal signal name using the external information and the internal information, and a buffer to be arranged between the two signals is determined using the library information. 11. The LSI design support program according to claim 10, wherein the design information is generated by recording a buffer name in association with the buffer name. 12. The computer-readable storage medium according to claim 11, wherein the buffer is determined from among buffers recorded in the library information, the buffer having a calculated delay time smaller than an expected value. 13. The LSI design support program according to claim 12, wherein the determination of the buffer determines a buffer having a minimum calculated value among buffers having a calculated delay time smaller than an expected value. 14. The LSI design support program according to claim 10, wherein the external information is board information on a board on which an LSI is installed. 15. The LSI design support program according to claim 14, wherein at least one of a data list and a circuit diagram is used as the board information. 16. The LSI design support program according to claim 10, wherein the internal information uses at least one of a system description language and a circuit diagram. 17. The LSI design support program according to claim 10, wherein the program causes a computer to execute an output process of outputting the design information of the interface portion in a predetermined format. 18. The LSI design support program according to claim 17, wherein the predetermined format uses at least one of a system description language and a circuit diagram.

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