JP3105782B2 - Logic generation method for electronic circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic generation method for an electronic circuit that generates a logic description with a low degree of abstraction from a logic description with a high level of abstraction.

[0002]

2. Description of the Related Art A logic generation system is a type of electronic circuit design automation system that generates a logic description having a low abstraction such as a gate level from a logic description defined at a high abstraction such as a register transfer level. .

A conventional operation in such a logic generation system will be described with reference to FIG.

FIG. 5A shows a logical description 500 having a high level of abstraction used in the present description. The logical description 500 in this example includes logical descriptions 501 and 502 of sequential elements and logical elements other than the sequential elements. It consists of a logical description 503.

The logical descriptions 501 and 502 of the sequential elements include:
Element identification information 505, 506 called an instance
Are defined, following the identification information 505 and 506, the element name “FF” and the output signal name “FFOUT00,
FFOUT01 ", input signal name" IFFOUT00, I
FFOUT01 ”is described.

Here, FF indicates a flip-flop.

The identification information (instance) 505,
Reference numeral 506 denotes information used for designating a stop point of a simulation when verifying logic with a high degree of abstraction by an interactive simulator, and the definition is not essential in the grammar of a hardware description language used for logic description. However, designers often consciously define. Also, “!” In the logical description 503 other than the sequential element means “inversion”. That is, “FFOUTN” means that the logic is the inverted logic of “FFOUT00”.

FIG. 6 shows an example of the processing flow of the conventional logic generation system. First, at step 510, the logic description 500 shown in FIG. 5 is read into the logic generation system, and at step 511 An actual sequential element is synthesized from the logical descriptions 501 and 502 of the sequential elements.
Specifically, the sequential elements whose functions are described are described at the gate level.

Thereafter, in step 512, the initial synthesis of the combinational circuit, that is, the logical description 50 other than the sequential elements
3 is initially synthesized. Then, in step 513,
A logic optimization process such as deletion of redundant logic is performed on the initial synthesis result so as to reach a desired gate scale and circuit speed, and a final logical description with a low abstraction is output.

FIGS. 7A and 7B show the logical description states at the end of steps 512 and 513, respectively. In FIG. 7A, 521 and 522 are sequential elements and 52, respectively.
3, 524 are output signal names “F” of the sequential elements 521, 522.
FOUT00 ”,“ FFOUT01 ”, 527, 528
Is the identification information “F” of the sequential elements 521 and 522, respectively.
1 "and" F2 ". The identification information “F1”, “F
"2" corresponds to 505 and 506 defined in the logical description 500.

Reference numeral 529 denotes a negation element having a signal name "FFO".
The logic of the output signal of "UT00" is inverted and output. 53
Numerals 0 and 531 are combinational logics corresponding to the description contents of the logical description 503 other than the sequential elements in FIG. 532 is one of the output pins of the sequential element 521, and can output a signal obtained by inverting the output signal of the signal name “FFOUT00” from this pin.

When the logic description state shown in FIG. 7A is subjected to the optimization processing in step 513, the logic description state is optimized to the logical description state shown in FIG. 7B. That is, the output signal of the NOT element 529 input to the combinational logic 530 is a signal of the same logic as the output pin 532 of the sequential element 521,
Even if the output signal of the output pin 532 is input to the combinational logic 530, it is equivalent. That is, the negation element 529 is redundant.

In the optimizing process, such a redundant portion is optimized. The logical description state of FIG. 7A is optimized by optimization processing to the logical description state as shown in FIG. 7B.

In FIG. 7B, the output signal of the output pin 532 of the sequential element 521 is input to the combinational logic 530, and the negation element 529 is deleted.

Here, the output pin 532 of the sequential element 521
Signal name "SIG00" 5
44 is attached.

As a known example related to this kind of logic generation method, for example, “Nikkei Electronics”
(May 30, 1988, no. 448, p. 185
193) "Developed a logic design automation system, ASIC
Aiming for a short-term design ”.

[0017]

[0005] Electronic circuits such as LSIs are becoming larger and more sophisticated. As a method of designing such an electronic circuit, a logic with a high level of abstraction (register transfer level / operation level) is described using a hardware description language, and a logic simulation using the logic description with the high level of abstraction is performed. After that, a logic generation system generally generates a logic description with a low level of abstraction (gate level) from a logic description with a high level of abstraction, and performs a logic simulation timing check at the gate level.

In the event that the designed electronic circuit does not operate as expected in the logic simulation / timing check at the gate level, the designer can use the information output by the logic simulator / timing checker to obtain a high level of abstraction. Identify the defective part of the logical description and change the logical description.

At this time, the defective part is specified by using the output signal name of the sequential element in the information output by the logic simulator / timing checker as a key. Is the signal name. In this case, when the conventional logic generation method described with reference to FIGS. 5 to 7 is used, the signal name used in the high-level abstraction logical description is generated independently of the signal name in the low-level abstraction logical description. ,
It is highly likely that some of the signal names on the low-level abstraction logical description generated in the optimization process are different from the signal names on the high-level abstraction logical description.

For this reason, there has been a problem that it is difficult to identify a defective portion of the logic description having a high abstraction level from information output by the logic simulator / timing checker.

It is an object of the present invention to simplify the correspondence between a high-level abstraction logic description and a low-level abstraction logic description. It is an object of the present invention to provide a method of generating a logic of an electronic circuit which can easily specify a defective portion in a logic description of the electronic circuit.

[0022]

In order to achieve the above object, according to the present invention, a logic generation system includes signal name storage means for storing output signal names of sequential elements defined by a logic description having a high degree of abstraction. If the output signal names of the sequential elements generated after the optimization processing performed when generating a logical description with a low degree of abstraction are different from the output signal names stored in the signal name storage means, the optimization processing is performed. The main feature is that a later output signal name is generated based on identification information of a sequential element defined in a logical description having a high degree of abstraction.

Also, instead of generating based on the identification information of the sequential element defined in the logical description having a high degree of abstraction, the output signal name after the optimization processing is replaced with the output signal name itself stored in the signal name storage means. Or a part of a character string of the stored output signal name is changed to a signal name using the output signal name.

In this case, during the logic optimization process, when the output signal name of the sequential element is changed by the optimization, the optimization for the sequential element may be substantially stopped. That is, when the output signal name of the generated sequential element is different from the output signal name stored in the signal name storage means at the stage of the optimization processing performed when generating the logical description with a low abstraction, May be returned to the state before the execution of the optimization processing. By returning to the state before the execution of the optimization processing, the optimization for the sequential element is substantially stopped. In addition,
This does not apply to the sequential element whose output signal name is not changed.

[0025]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a system configuration diagram showing an embodiment of a logic generation system to which the present invention is applied, and FIG.
FIG. 6 shows an example of a gate-level logic description 600 generated from the logic description 500 of FIG.

In FIG. 1, reference numeral 101 denotes a high-level description file defining a logical description with a high degree of abstraction. As shown in FIG. 5, a logical description 50 at the register transfer level is provided.
0 is stored.

Reference numeral 110 denotes a logic generation system that reads the contents of the high-level description file 101 and generates a low-level abstraction logical description. This is a description file.

Inside the logic generation system 110, an initial synthesis unit 111 for synthesizing sequential elements and initial synthesis of combinational logic, and an optimization unit 1 for optimizing combinational circuits
12, an intermediate file 113 for temporarily storing the processing result of the initial synthesizing unit 111, a signal name generating unit 114 newly added in the present invention, and an output signal name table 200.

FIG. 3 is a diagram showing the structure of the output signal name table 200. Reference numeral 201 denotes identification information of the sequential element (F
1, F2), 202 is the identification information 20
The output signal name of the sequential element corresponding to 1 (FFoutT1, F
FouT2).

FIG. 4 is a flowchart showing the procedure of the logic synthesis method for an electronic circuit according to the present invention.

Step 301 is performed in the logic generation system 11.
0 is the content of the high-level description file 101 that is a logical description with a high degree of abstraction to be subjected to the logical generation processing (logical description 500)
Steps 302 to 304 are processes performed by the initial synthesizing unit 111.
Are combined (step 302), and the output signal names 53 of the sequential elements 521 and 522
2, 524 is used as the identification information F of the sequential elements 521, 522.
After storing in the output signal name table 200 together with F1 and F2 (step 303), the combinational logics 530 and 531 are initially synthesized (step 304).

Next, with respect to the initial synthesis result of the combinational logic, the optimization unit 112 performs logic optimization by deleting redundant logic so as to reach a desired gate scale and circuit speed (step 305).

In this logic optimization, the sequential element 52
Since the output signal names of 1,522 may be changed,
Steps 306 to 31 which are processing of the signal name generation unit 114
In step 1, an output signal name is generated based on the identification information F1 and F2 of the sequential elements 521 and 522.

Since the identification information F1 and F2 are generally uniquely assigned, a signal name generated from one identification information can be generated without overlapping a signal generated from another identification information.

Therefore, it is first determined whether or not the output signal names of the sequential elements 521 and 522 are different from the output signal names stored in the output signal name table 200 of FIG. 3 (step 306).

If the output signal names are different, the sequential element 52
A signal name is generated using the identification information F1 and F2 of the first and 522 (step 307).

The rule to be generated is, for example, identification information F1, F
It is easiest to add a character to 2.

Next, it is determined whether or not the same signal name as the generated signal name exists (step 308). If the same signal name exists, the output signal name of the sequential element generated by the optimization is determined in step 308. A signal having the same name as the signal generated in 307 is added (step 309).

Next, the generated signal name is assigned to the output signal of the sequential element (step 310).

Next, it is determined whether or not the processing for all the sequential elements has been completed (step 311). If the processing has been completed, a logical description with a low abstraction level converted by the above procedure is output (step 311). 312).

FIG. 2 shows an example of a gate-level logic description 600 generated from the logic description 500 of FIG. 5. In the prior art, the output pin 5 of the sequential element 521 is shown.
As shown in FIG. 7B, the output signal name of 32 has an unknown meaning such as the signal name “SIG00” 544. However, in the logic generation method according to the present invention, “F1 — 0” is used.
The name is associated with the identification information F1 of the sequential element 521.

Thus, when a logic failure is extracted by a logic simulation / timing check at the gate level, it is possible to easily specify a failure location in the logic description with a high abstraction level.

In this case, the signal name generation method in step 307 in FIG. 4 may be generated from the signal names stored in the output signal name table 200 of the sequential element, regardless of the identification information of the sequential element. The output signal names of the sequential elements are also uniquely assigned like the identification information. Therefore, even in this case, the output signal name before logic generation can be easily associated with the signal name after logic generation.

If the output signal names of the sequential elements are changed by optimization during the logic optimization process, instead of converting the signal names after the logic optimization process, the optimization is stopped. Thus, the output signal names of the sequential elements can be stored.

[0046]

As described above, according to the present invention, the description of the corresponding sequential element on the logical description with a high degree of abstraction can be easily specified from the output signal name of the sequential element in the logical description with a low level of abstraction. When a logic failure is extracted by logic simulation / timing check at the gate level, it is possible to easily specify a failure location in a logic description with a high level of abstraction.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing an embodiment of a logic generation system to which the present invention is applied.

FIG. 2 is a diagram showing an example of gate level logic generation according to the present invention.

FIG. 3 is a configuration diagram of an output signal name table.

FIG. 4 is a flowchart showing a processing procedure of the logic synthesis system of FIG. 1;

FIG. 5 is a diagram showing an example of a logic description with a high abstraction level in a conventional logic generation system.

FIG. 6 is a flowchart showing a processing procedure in a conventional logic generation system.

FIG. 7 is a diagram showing an example of a gate-level logic description generated in a conventional logic generation system.

[Explanation of symbols]

101: high-level description file, 102: low-level description file, 110: logic generation system, 111: initial synthesis unit,
112: optimization unit, 113: intermediate file, 114: signal name generation unit, 200: output signal name table.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-282595 (JP, A) JP-A-5-20394 (JP, A) JP-A 4-77873 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G06F 17/50

Claims (3)

(57) [Claims] 1. A logic generation method for an electronic circuit in a logic generation system for generating a logic description with a low degree of abstraction from a logic description with a high level of abstraction, comprising: an output signal of a sequential element defined by the logic description with a high level of abstraction Output signal names of sequential elements generated after the optimization processing performed when generating a low-level abstraction logic description are provided in the signal name storage means. Wherein the output signal name after the optimization processing is generated based on the identification information of the sequential element defined in the logical description having a high degree of abstraction when the name is different from the name. . 2. A logic generation method for an electronic circuit in a logic generation system for generating a logic description having a low degree of abstraction from a logic description having a high level of abstraction, comprising: an output signal of a sequential element defined by the logic description having a high level of abstraction Output signal names of sequential elements generated after the optimization processing performed when generating a low-level abstraction logic description are provided in the signal name storage means. If the output signal name is different from the name, the output signal name after the optimization process is changed to the output signal name stored in the signal name storage means or the signal name using a part of the character string of the stored output signal name. A logic generation method for an electronic circuit, characterized in that: 3. A logic generation method for an electronic circuit in a logic generation system for generating a logic description with a low degree of abstraction from a logic description with a high level of abstraction, the output signal of a sequential element defined by the logic description with a high level of abstraction A signal name storing means for storing a name, and at the stage of optimization processing performed when generating a low-level abstraction logical description, the output signal name of the generated sequential element is stored in the signal name storing means. When the signal name is different from the signal name, the output signal name of the sequential element is returned to a state before the optimization processing is performed.