JP3652220B2 - Logic circuit verification device, logic circuit verification method, and recording medium storing logic circuit verification program - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a logic circuit verification device, a logic circuit verification method, and a recording medium storing a logic circuit verification program, and more particularly to a logic circuit verification device, a logic circuit verification method, and a logic for verifying logic equivalence in the type verification of a logic circuit. The present invention relates to a recording medium storing a circuit verification program.
[0002]
[Prior art]
Conventionally, in order to verify the equivalence of two logic circuits, the locations where the logic in the two logic circuits to be verified are considered to be equivalent are divided into circuits such as flip-flops and external cut-out terminals. The logic equivalence point is determined from information such as signal names and the like, and the logic equivalence is verified for each corresponding partial circuit.
[0003]
In many cases, BDD (binary decision diagram) is used for verification of logical equivalence for each partial circuit.
[0004]
Since BDD can uniquely determine the BDD representation of the equivalent logic if the input variables are ordered, the logic equivalence is verified using this.
[0005]
In recent years, a circuit is described using a hardware description language such as VHDL (IEEE 1076) or Verilog-HDL (IEEE 1364), and the circuit is divided into a plurality of layers for each specific function in order to describe a larger circuit. In general, a method of automatically generating a logic circuit using a logic synthesis tool is described.
[0006]
At the time of this logic synthesis, in order to further optimize the circuit, when the target circuit is composed of a plurality of layers, the plurality of layers are simultaneously optimized. When the upper layer of the target circuit has constant information, it is required to simplify the constant information by propagating the constant information from the upper layer to the lower layer.
[0007]
Similarly, it is also required to simplify the logic in other hierarchies by moving a part of the logic to other hierarchies and to improve the placement and routing accuracy in the hierarchies.
[0008]
In the general first conventional logic circuit verification method, FIG. 3 showing the circuit 100 before optimization and the optimization are shown for an example in which equivalence verification is performed when the circuit is optimized according to this requirement. Referring to FIG. 7 showing the subsequent circuit 400, the logic verification method for both the circuits 100 and 400 is verified for each layer.
[0009]
When the input terminals G of the flip-flops 212 as the verification points in the lower layer (SUB) layers 201 and 201A of the circuit 100 and the circuit 400 are the verification points 401 and 401A, respectively, It is expressed by equations (1) and (2).
[0010]
Circuit 100: G = D * E (1)
Circuit 400: G = D (2)
Accordingly, when the expressions (1) and (2) are compared as they are, the determination of matching results in a logical mismatch.
[0011]
As described above, the conventional first logic circuit verification method has a problem in that verification cannot be performed in consideration of the influence of propagation of constants across hierarchies.
[0012]
For this reason, in the conventional second logic circuit verification method described in Japanese Patent Laid-Open No. 10-63707, the circuit 100 before optimization and the circuit 400 after optimization are shown in FIG. 14 and FIG. Like the circuit 800, a plurality of hierarchies are expanded into one hierarchy, and logic verification is performed on verification points 701 and 801 corresponding to the input terminal G of the flip-flop that is the original verification point.
[0013]
When the logic of each of the verification points 701 and 801 is represented by a Boolean expression, it is represented by the following expression.
[0014]
Circuit 700: SUB / G = SUB / F (3)
SUB / F = C * 1 (4)
C = A * B (5)
Summarizing equations (3)-(5):
SUB / G = A * B (6)
Circuit 800: SUB / G = C (7)
C = A * B (8)
Summarizing Equations 7 and 8,
SUB / G = A * B (9)
In the second conventional logic circuit verification method, it is determined that the logically coincides with each other by comparing the equations (6) and (9).
[0015]
As a result, since the partial circuit to be verified becomes large by expanding the hierarchy, there is a problem that a required memory amount becomes large when expressed by BDD used when verifying the partial circuit.
[0016]
[Problems to be solved by the invention]
The above-described conventional first logic circuit verification device and logic circuit verification method cannot perform verification in consideration of the influence of constant propagation across hierarchies when the target circuit is composed of a plurality of hierarchies. There were drawbacks.
[0017]
In the conventional second logic circuit verification apparatus and logic circuit verification method that solves the above-mentioned drawbacks, since the partial circuit to be verified becomes large by expanding the hierarchy, it is expressed by BDD used when verifying the partial circuit. In this case, there is a drawback that a required memory amount becomes large.
[0018]
An object of the present invention is to provide a logic circuit verification apparatus and a logic circuit verification method that enable verification of a circuit that has been optimized across hierarchies and that can be verified with a smaller amount of memory.
[0019]
[Means for Solving the Problems]
The logic circuit verification device according to the first aspect of the present invention extracts a place where logic in a logic circuit to be verified having a hierarchical structure is equivalent as a verification point using a register and / or an external cut terminal, and pays attention to the verification point. The logic equivalence between multiple logic circuits is verified by dividing the circuit into partial circuits, determining the logical equivalence point from the information including the signal name, and verifying the logical equivalence for each corresponding partial circuit. In the logic circuit verification device,
Data input means for reading circuit information from the circuit data and library of the logic circuit to be verified and converting the circuit information into an intermediate format; and
Hierarchical expansion processing means for generating a hierarchical expansion intermediate format in which the intermediate format is hierarchically expanded and the hierarchical cut terminal information, which is information related to a hierarchical cut terminal that is a boundary terminal between hierarchies in this hierarchical expansion processing, is stored;
A verification point extraction means for extracting the verification point as a comparison from the hierarchical expansion intermediate format and outputting verification point information;
Circuit dividing means for generating partial circuit data by dividing the verification target logic circuit into partial circuits using the hierarchical cut-out terminal information with reference to the hierarchical expansion intermediate format and the verification point information;
Comparison verification means for verifying the logical equivalence of the corresponding partial circuit with reference to the verification point information and the partial circuit data;
A verification result determination unit for determining a verification result by the comparison verification unit;
Partial circuit information extraction means for extracting partial circuit information from the partial circuit data using the hierarchical cut end terminal information in the hierarchical expansion intermediate format when the verification result does not match the determination result;
And a verification result output means for outputting the verification result.
[0020]
According to a second aspect of the present invention, there is provided the logic circuit verification apparatus according to the first aspect, further comprising constant propagation processing means for performing constant propagation processing on the hierarchical expansion intermediate format generated by the hierarchical expansion processing means. It is what.
[0021]
According to a third aspect of the present invention, there is provided a logic circuit verifying apparatus that extracts a portion in which logic in a verification target logic circuit having a hierarchical structure is regarded as equivalent as a verification point using a register and / or an external cut terminal. By paying attention, the circuit is divided into partial circuits, logical equivalence points are determined from information including signal names, and logical equivalence between multiple logical circuits is verified by verifying logical equivalence for each corresponding partial circuit. In the logic circuit verification device to verify,
Data input means for reading circuit information from the circuit data and library of the logic circuit to be verified and converting the circuit information into an intermediate format; and
Hierarchical expansion processing means for generating a hierarchical expansion intermediate format in which the intermediate format is hierarchically expanded and the hierarchical cut terminal information, which is information related to a hierarchical cut terminal that is a boundary terminal between hierarchies in this hierarchical expansion processing, is stored;
A verification point extraction means for extracting the verification point as a comparison from the hierarchical expansion intermediate format and outputting verification point information;
Circuit dividing means for generating partial circuit data by dividing the verification target logic circuit into partial circuits using the hierarchical cut-out terminal information with reference to the hierarchical expansion intermediate format and the verification point information;
Partial circuit information extracting means for performing processing for storing the logical information of the partial circuit on the input side with respect to the hierarchical cut terminal in the partial circuit data after the circuit division by the circuit dividing means;
Comparison verification means for verifying the logical equivalence of the corresponding partial circuit with reference to the verification point information and the partial circuit data;
A verification result determination unit for determining a verification result by the comparison verification unit;
And a verification result output means for outputting the verification result.
[0022]
Furthermore, the invention according to claim 4 is the logic circuit verification device according to claim 1 or 3, wherein the hierarchy cut terminal information is stored in a buffer set in the partial circuit data during the hierarchy development process. It is a feature.
[0023]
According to the logic circuit verification method of the invention described in claim 5, a location where logic in a logic circuit to be verified having a hierarchical structure is regarded as equivalent is extracted using a register and / or an external cut terminal as a verification point, and attention is paid to this verification point. The logic equivalence between multiple logic circuits is verified by dividing the circuit into partial circuits, determining the logical equivalence point from the information including the signal name, and verifying the logical equivalence for each corresponding partial circuit. In the logic circuit verification method,
A data input step of reading circuit information from the circuit data of the logic circuit to be verified and the library from the library and converting the circuit information to an intermediate format;
A hierarchical expansion processing step for generating a hierarchical expansion intermediate format in which the intermediate format circuit information is hierarchically expanded and the hierarchical cut terminal information that is a boundary terminal between the hierarchical levels is stored in the hierarchical expansion processing;
A verification point extraction step for extracting a verification point as a comparison reference from the hierarchical expansion intermediate format and outputting the verification point information;
A circuit division step of referring to the hierarchical expansion intermediate format and the verification point information, performing circuit division using the hierarchy cut terminal information, and outputting partial circuit data;
A comparison verification step of verifying the logical equivalence of the corresponding partial circuit with reference to the verification point information and the partial circuit data;
A verification result determining step for determining a verification result of the verification point information and the partial circuit data;
If the verification result information and the verification result of the partial circuit data match in the verification result determination step, a verification result output step of outputting the verification result;
If the verification point information and the verification result of the partial circuit data do not match in the verification result determination step, the partial circuit data is referred to again, and a new partial portion is used by using the hierarchical cut terminal information in the hierarchical expansion intermediate format. And a partial circuit information extraction step for extracting circuit information.
[0024]
The invention described in claim 6 further includes a constant propagation processing step for performing constant propagation processing on the intermediate layer expansion format generated in the layer expansion processing step in the logic circuit verification method according to claim 5. It is characterized by.
[0025]
According to the logic circuit verification method of the invention described in claim 7, a location where logic in the logic circuit to be verified having a hierarchical structure is regarded as equivalent is extracted using a register and / or an external cut terminal as a verification point. By paying attention, the circuit is divided into partial circuits, logical equivalence points are determined from information including signal names, and logical equivalence between multiple logical circuits is verified by verifying logical equivalence for each corresponding partial circuit. In the logic circuit verification method to verify,
A data input step of reading circuit information from the circuit data of the logic circuit to be verified and the library from the library and converting the circuit information to an intermediate format;
A hierarchical expansion processing step for generating a hierarchical expansion intermediate format in which the intermediate format circuit information is hierarchically expanded and the hierarchical cut terminal information that is a boundary terminal between the hierarchical levels is stored in the hierarchical expansion processing;
A verification point extraction step for extracting a verification point as a comparison reference from the hierarchical expansion intermediate format and outputting the verification point information;
A circuit division step of referring to the hierarchical expansion intermediate format and the verification point information, performing circuit division using the hierarchy cut terminal information, and outputting partial circuit data;
A partial circuit information extraction step for performing a process of storing logical information of the partial circuit on the input side of the partial circuit data in the partial circuit data after the circuit dividing step;
A comparison verification step of verifying the logical equivalence of the corresponding partial circuit with reference to the verification point information and the partial circuit data;
A verification result determining step for determining a verification result of the verification point information and the partial circuit data;
If the verification result information and the verification result of the partial circuit data match in the verification result determination step, the verification result output step of outputting the verification result,
If the verification point information and the verification result of the partial circuit data do not match in the verification result judging step, the logical information stored in the hierarchical cut terminal is used again in the partial circuit information extraction step. In the comparison verification step, re-verification is performed.
[0026]
The storage medium storing the logic circuit verification program of the invention according to claim 8 extracts a place where the logic in the logic circuit to be verified having a hierarchical structure is regarded as equivalent, using a register and / or an external cut terminal as a verification point, Pay attention to the verification points, divide the circuit into partial circuits, determine the logical equivalence point from the information including the signal name, and verify the logical equivalence for each corresponding partial circuit. In a storage medium storing a logic circuit verification program for verifying equivalence,
A data input step of reading circuit information from the circuit data of the logic circuit to be verified and the library from the library and converting the circuit information to an intermediate format;
A hierarchical expansion processing step for generating a hierarchical expansion intermediate format in which the intermediate format circuit information is hierarchically expanded and the hierarchical cut terminal information that is a boundary terminal between the hierarchical levels is stored in the hierarchical expansion processing;
A verification point extraction step of extracting a verification point as a comparison reference from the hierarchical expansion intermediate format and outputting the verification point information;
A circuit division step of referring to the hierarchical expansion intermediate format and the verification point information, performing circuit division using the hierarchy cut terminal information, and outputting partial circuit data;
A comparison verification step of verifying the logical equivalence of the corresponding partial circuit with reference to the verification point information and the partial circuit data;
A verification result determining step for determining a verification result of the verification point information and the partial circuit data;
If the verification result information and the verification result of the partial circuit data match in the verification result determination step, a verification result output step of outputting the verification result;
If the verification point information and the verification result of the partial circuit data do not match in the verification result determination step, the partial circuit data is referred to again, and a new partial portion is used by using the hierarchical cut terminal information in the hierarchical expansion intermediate format. And a partial circuit information extraction step for extracting circuit information.
[0027]
According to a ninth aspect of the present invention, in the storage medium storing the logic circuit verification program according to the eighth aspect, constant propagation for performing constant propagation processing on the hierarchical expansion intermediate form generated in the hierarchical expansion processing step. It has a processing step.
[0028]
The storage medium storing the logic circuit verification program of the invention according to claim 10 extracts a place where the logic in the logic circuit to be verified having a hierarchical structure is regarded as equivalent, using a register and / or an external cut terminal as a verification point, Pay attention to the verification points, divide the circuit into partial circuits, determine the logical equivalence point from the information including the signal name, and verify the logical equivalence for each corresponding partial circuit. In a storage medium storing a logic circuit verification program for verifying equivalence,
A data input step of reading circuit information from the circuit data of the logic circuit to be verified and the library from the library and converting the circuit information to an intermediate format;
A hierarchical expansion processing step for generating a hierarchical expansion intermediate format in which the intermediate format circuit information is hierarchically expanded and the hierarchical cut terminal information that is a boundary terminal between the hierarchical levels is stored in the hierarchical expansion processing;
A verification point extraction step for extracting a verification point as a comparison reference from the hierarchical expansion intermediate format and outputting the verification point information;
A circuit division step of referring to the hierarchical expansion intermediate format and the verification point information, performing circuit division using the hierarchy cut terminal information, and outputting partial circuit data;
A partial circuit information extraction step for performing a process of storing logical information of the partial circuit on the input side of the partial circuit data in the partial circuit data after the circuit dividing step;
A comparison verification step of verifying the logical equivalence of the corresponding partial circuit with reference to the verification point information and the partial circuit data;
A verification result determining step for determining a verification result of the verification point information and the partial circuit data;
If the verification result information and the verification result of the partial circuit data match in the verification result determination step, the verification result output step of outputting the verification result,
If the verification point information and the verification result of the partial circuit data do not match in the verification result judging step, the logical information stored in the hierarchical cut terminal is used again in the partial circuit information extraction step. In the comparison verification step, re-verification is performed.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
[0030]
In the logic circuit verification method of the present embodiment, in the logic equivalence verification in the format verification between a plurality of logic circuits, the layer cut-out terminal information is stored in the layer expansion processing part, and the verification target is obtained using the information. This logic circuit is divided into partial circuits, and the logical equivalence is verified for each partial circuit.
[0031]
Next, referring to FIG. 1 showing the first embodiment of the present invention as a block, the logic circuit verification apparatus according to the present embodiment shown in this figure shows circuit data of a logic circuit having a hierarchical structure to be verified. Data input unit 1 that reads circuit information from F1 and library F2 and converts and outputs this circuit information to intermediate format F3, and circuit information from intermediate format F3 is hierarchically expanded and is a terminal at the boundary between layers in this hierarchical expansion processing. A hierarchy expansion processing unit 2 that outputs a hierarchy expansion intermediate format F4 in which hierarchy cut terminal information is stored; a verification point extraction unit 3 that extracts a verification point as a comparison from the hierarchy expansion intermediate format F4 and outputs verification point information F5; The target circuit is divided into partial circuits using the hierarchical cut terminal information by referring to the hierarchical expansion intermediate format F4 including the hierarchical cut terminal information and the verification point information F5, and the partial circuit data F6 is generated. Circuit dividing unit 4 that performs verification, comparison verification unit 5 that verifies the logical equivalence of the corresponding partial circuit with reference to verification point information F5 and partial circuit data F6, verification result determination unit 6 that determines the verification result, and verification If the result does not match, the partial circuit information extraction unit 7 extracts partial circuit information from the partial circuit data F6 using the hierarchical cut terminal information of the hierarchical expansion intermediate format F4, and the verification result output unit 8 outputs the verification result F7. With.
[0032]
Here, the circuit data F1 includes a hardware description language such as VHDL (IEEE 1076) or Verilog-HDL (IEEE 1364), or a netlist such as EDIF. The library F2 is data describing macro logic information used in the circuit data F1.
[0033]
Further, the intermediate format F3, the verification point information F5, and the partial circuit data F6 are temporarily stored in a storage device and used at an intermediate stage of processing.
[0034]
Next, the operation of the present embodiment will be described with reference to FIG. 1 and FIG. 2 showing the processing in a flowchart. In the present embodiment, the partial circuit information on the input side is searched and extracted from the hierarchical cut terminal. Verify logical equivalence by re-verifying. In this figure, the processing flow is indicated by a solid line, and the data flow is indicated by a dotted line.
[0035]
First, the data input unit 1 reads the circuit data F1 and the library F2, and converts the circuit data F1 and the library F2 into an intermediate format F3 (step S1).
[0036]
The hierarchy expansion processing unit 2 hierarchically expands the circuit information of the intermediate format F3 and generates a hierarchy expansion intermediate format F4 in which the hierarchy cut terminal information which is a boundary terminal between the hierarchies is stored in the hierarchy expansion processing (step S2).
[0037]
Next, the verification point extraction unit 3 extracts a verification point as a comparison reference from the hierarchical development intermediate format F4, and outputs it to the verification point information F5 (step S3).
[0038]
Next, the circuit dividing unit 4 refers to the hierarchical expansion intermediate format F4 and the verification point information F5, performs circuit division using the hierarchical cut terminal information, and outputs partial circuit data F6 (step S4).
[0039]
Next, the comparison verification unit 5 verifies the logical equivalence of the corresponding partial circuit with reference to the verification point information F5 and the partial circuit data F6 (step S5).
[0040]
As a verification method, a verification method using BDD (Binary Decision Graph: Binary Decision Diagrams), a test pattern generated using ATPG (Automatic Test Pattern Generator), a verification method for performing simulation, etc. Validate.
[0041]
The verification result determination unit 6 determines the verification result of the verification point information F5 and the partial circuit data F6 (step S6). If they match, the verification result output unit 8 sends the verification result to the verification result output unit 8. The verification result F7 is output (step S8).
[0042]
If they do not match in step S6, the partial circuit information extraction unit 7 refers again to the partial circuit data F6 and the hierarchical expansion intermediate format F4, and uses the hierarchical cut terminal information of the hierarchical expansion intermediate format F4 to create a new partial. New partial circuit information for extracting circuit information is extracted (step S7) and supplied to the comparison verification unit 5. The comparison verification unit 5 performs the verification of step S5 again.
[0043]
Until the verification of all the parts of the circuit to be verified is completed (step S9), the verification by the comparison verification unit 5 (step S4) is repeated.
[0044]
Next, referring to FIG. 3 showing a circuit 100 as an example of circuit data F1 of the circuit to be verified, this circuit 10 has an upper (TOP) hierarchy 101 and a lower (SUB) hierarchy which is a lower hierarchy. 201.
[0045]
The TOP hierarchy 101 includes a logic gate C111 whose input terminal is connected to the terminals A and B, and constant information 112 whose output terminal is connected to the terminal E.
[0046]
The SUB hierarchy 201 includes a logic gate F211 whose input terminal is connected to the terminals D and E, and a flip-flop whose input terminal G is connected to the output terminal of the logic gate F211 and output terminal H is connected to the terminal I and clock terminal is connected to the terminal CLK1. 212.
[0047]
As verification points, there are terminals A, B and J outside the TOP hierarchy 101, a clock terminal CLK, terminals D, E and I outside the SUB hierarchy 102, and a clock terminal CLK1. Among these, the terminals D, E, and I and the clock terminal CLK1 are hierarchy cut terminals between the TOP hierarchy 101 / SUB hierarchy 201.
[0048]
Referring to FIG. 4 in which circuit data of the circuit 100 is divided into hierarchical units, FIG. 4A shows the TOP hierarchy 101 and FIG. 4B shows the SUB hierarchy 201. The TOP hierarchy 101 shown in FIG. 4A has a block 102 corresponding to the SUB hierarchy 201.
[0049]
The circuit data F1 read into the data input unit 1 with reference to FIG. 5 showing the circuit 200 as a result of the hierarchical expansion of the circuit data of FIG. 3, FIG. 4 and FIG. The processing in the case of having the structure will be described. In this way, when the circuit 200 has a structure having a plurality of, in this example, two layers, the circuit data F1 is shown in FIGS. As shown in FIG. 2, each of the two layers of TOP / SUB has a structure of a separate data unit.
[0050]
The hierarchy development process can be realized by replacing the block 102 with the SUB hierarchy 201 for the two hierarchies, the TOP hierarchy 101 and the SUB hierarchy 201. At this time, in order to store the cut terminal information held by the block 102, buffers 701 to 704 are inserted and connected to the respective positions of the upper and lower hierarchical cut terminals D, E, I and the clock terminal CLK1.
[0051]
Identifiers SUB / D, SUB / E, SUB / I, and SUB / CLK1 are added to the buffers 701 to 704, respectively, so that it can be identified that they are hierarchical cut terminals. Similarly, identifiers SUB / F, SUB / G, and SUB / H are added to the terminals of logic gate F211 and flip-flop 212, respectively. In this way, it is converted into one hierarchical structure as shown in FIG.
[0052]
Referring to FIG. 6A showing the input side circuit 300 of the input terminal SUB / G401 of the register such as the flip-flop 212 in the circuit 200, this input side circuit 300 includes terminals A and B, logic gates. C 111, signal source 112, logic gate SUB / F 211, and buffers 701 and 702.
[0053]
The input-side circuit 300 is further divided into partial circuits 301, 302, and 303 shown in FIGS. 6B, 6C, and 6D, respectively.
[0054]
The partial circuit 301 includes buffers SUB / D701A and SUB / E702A, a logic gate SUB / F211 and a terminal SUB / G401. The partial circuit 302 includes terminals A and B, a logic gate C111, and a buffer SUB / D701B. The partial circuit 303 includes a signal source 112 and a buffer SUB / E702B.
[0055]
Next, the circuit division processing step S3 in the circuit dividing unit 4 will be described with reference to FIGS. 5 and 6. The partial circuit when the input terminal SUB / G401 of the flip-flop 212 is used as the verification point is the input side. In the data input unit 1, there are buffers 701 and 702 for storing the set hierarchical cut information, so that the portion up to that is recognized as the partial circuit 301.
[0056]
Similarly, the circuits on the input side of the buffers 701 and 702 for storing the hierarchical cut information are recognized as partial circuits 302 and 303, respectively.
[0057]
Next, referring to FIG. 7 showing a circuit diagram of a circuit 400 obtained by performing optimization across the layers using constant information for the circuit 100, the circuit 400 includes the optimized upper (TOP) layer 101A and , And a lower (SUB) layer 201A that is a lower layer.
[0058]
The TOP hierarchy 101A has a logic gate C111 whose input terminal is connected to terminals A and B. The signal source 112 existing in the upper layer 101 before the optimization is omitted.
[0059]
The SUB hierarchy 201A includes a flip-flop 212 in which an input terminal G is connected to a terminal D, an output terminal H is connected to a terminal I, and a clock terminal is connected to a terminal CLK1. The logic gate F211 existing in the lower hierarchy 201 before optimization is omitted.
[0060]
FIG. 8 is a circuit diagram of the circuit 500 obtained as a result of hierarchical expansion of the circuit 400 by the logic circuit verification method of this embodiment, and the input side of the input terminal SUB / G401A of the flip-flop 212 in the circuit of FIG. Referring to FIG. 9A showing the extracted circuit 600, the input side circuit 600 has terminals A and B, a logic gate C111, and a buffer 701, and existed in the circuit of the same function before optimization. The signal source 112, the logic gate SUB / F 211, and the buffer 702 are omitted.
[0061]
Similarly, referring to FIGS. 9B and 9C showing the partial circuits 601 and 602 obtained by dividing the input side circuit 600, the partial circuit 601 includes the buffer SUB / D 701A, and the partial circuit 602 includes the terminals A and 602. B, logic gate C111, and buffer SUB / D701B.
[0062]
Next, with reference to FIG. 5 to FIG. 9, a description will be given of processing when it is determined that there is a mismatch in the verification result determination (step S5) of the comparison verification (step S4) in the comparison verification unit 5.
[0063]
As the corresponding verification points, the input terminal SUB / G401 and the input terminals SUB / G401 and 401A of the flip-flop 212 are verified.
[0064]
Corresponding partial circuits are a partial circuit 301 and a partial circuit 601, respectively. When equivalence is verified for these two partial circuits 301 and 601 (steps S4 and S5), it is determined that the two do not match. When the information on the input side of each partial circuit is searched because of mismatch, the hierarchical circuit terminals SUB / D and SUB / E corresponding buffers 701 and 702 are connected to the partial circuit 301, while the partial circuit 601 is connected to the partial circuit 601. A hierarchical cut terminal SUB / D correspondence buffer 701 is connected.
[0065]
Therefore, the partial circuits 302 and 303 and the partial circuit 602 connected to the input side are further extracted (step S6). Using the partial circuits 302 and 303 and the partial circuit 602 extracted again, the partial circuit on the input side is connected to each of the partial circuits 301 and 601, and the verification target partial circuit is expanded. Can be determined to match.
[0066]
Here, when the partial circuit to be verified is expanded by connecting the partial circuit on the input side and re-verification is performed, it is not necessary to connect all the partial circuits in a single process. It is the same even if the connection of the partial circuits and the re-verification process are repeated until the partial circuits are enlarged and matched.
[0067]
In this way, in this embodiment, when verifying the logic of the hierarchy currently being processed, processing that can refer to logic in other hierarchies is performed, so optimization across multiple hierarchies is performed. It is possible to verify correctly in the verification of logic equivalence in the case of doing.
[0068]
Further, since the process of dividing the partial circuit at the position where the hierarchical cut-off terminal is performed, verification can be performed without maximizing at least the partial circuit, and the amount of memory used can be suppressed. .
[0069]
Next, referring to FIG. 10 in which the second embodiment of the present invention is shown in the same block by adding common reference characters / numbers to the same components as in FIG. The difference from the first embodiment is that the partial circuit data F6 is divided into the partial circuit data F6 after the circuit division by the circuit dividing unit 4 instead of the partial circuit information extracting unit 7, and A partial circuit information extraction unit 7A that performs a process of storing the logic information held in the hierarchical cut terminal.
[0070]
Next, with reference to FIG. 10 and FIG. 11 in which the same reference characters / numbers are assigned to the same components as those in FIG. In this embodiment, after the circuit division in the circuit dividing unit 4 (step S4), the logical information of the partial circuit on the input side of the hierarchical circuit terminal of the partial circuit data F6 is stored in the hierarchical network terminal. The partial circuit information extraction processing step S7A to be stored is performed.
[0071]
If there is no coincidence in the comparison verification steps S4 and S5 of the partial circuits in the comparison verification unit 5 and the comparison result determination unit 5 thereafter, step S5 is performed using the logical information stored in the hierarchical cut terminal. Re-verification is performed in S6.
[0072]
As a result, it is not necessary to perform extraction processing of the partial circuit on the input side as needed.
[0073]
In this case, instead of extracting the logical information of the partial circuit on the input side for all hierarchical cut terminals, a specific condition is set, and the logical information is extracted only when the condition is met. May be.
[0074]
For example, if the optimization across the hierarchy is only in the case of constant propagation, only constant information is used as the extraction condition, and only the case where the logic on the input side of the hierarchy cut terminal is simplified to a constant is extracted. Store at the level cut terminal.
[0075]
In this way, the logical information to be extracted can be reduced, the processing can be performed at high speed, the amount of used memory can be suppressed, and the necessity of re-verification can be determined, and the processing speed can be increased.
[0076]
Next, the third embodiment of the present invention will be described with reference to FIG. 12 in which the same reference characters / numbers are attached to the same components as in FIG. The difference from the first embodiment described above is that a constant propagation processing unit 11 for performing constant propagation processing on the generated hierarchical expansion intermediate format F3 is provided after the hierarchical expansion processing unit 2. .
[0077]
The difference between the operation of the present embodiment and the first embodiment will be described with reference to FIG. 13. In the present embodiment, the hierarchy expansion intermediate format generated after the hierarchy expansion processing in step S2 For F4, the constant propagation processing unit 11 performs constant propagation processing step S11 across hierarchies so that constants set in the upper hierarchies are propagated to the lower hierarchies. Simplify the logic of the hierarchy.
[0078]
As a result, it is possible to prevent in advance that the comparison / verification unit 5 determines that there is a mismatch due to optimization across hierarchies.
[0079]
Therefore, this embodiment is effective when optimized by constant propagation across hierarchies.
[0080]
【The invention's effect】
As described above, the logic circuit verification apparatus and the logic circuit verification method according to the present invention include hierarchical expansion processing means for generating a hierarchical expansion intermediate format in which the intermediate format is hierarchically expanded and the hierarchical cut terminal information is stored in the hierarchical expansion processing. When verifying the logic of the hierarchy currently being processed by providing partial circuit information extraction means for extracting partial circuit information from partial circuit data using hierarchical cut-out terminal information in the case where the verification result judgment result does not match, Since the logic in another hierarchy can be referred to, there is an effect that it is possible to verify correctly even in the verification of the equivalence of logic when optimization is performed across a plurality of hierarchies.
[0081]
Further, by dividing the partial circuit at the position where the hierarchical cut-off terminal is located, at least the partial circuit can be verified without maximizing it, and the amount of used memory can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a logic circuit verification device of the present invention.
FIG. 2 is a flowchart showing an example of operation in the logic circuit verification method of the present embodiment;
FIG. 3 is a circuit diagram showing circuit data of a first target circuit example in the logic circuit verification method of the present embodiment;
4 is a circuit diagram describing the circuit of FIG. 3 by dividing it into hierarchical units.
FIG. 5 is a circuit diagram showing a circuit obtained as a result of hierarchical expansion of the circuit data of FIG. 3 by the logic circuit verification method of the present embodiment;
6 is a circuit diagram of a circuit excerpted from a part of the circuit data of FIG. 5 and a circuit diagram in which this circuit data is divided and described in units of layers.
7 is a circuit diagram showing a circuit obtained as a result of performing optimization across layers using constant information for the circuit of FIG. 3;
FIG. 8 is a circuit diagram showing a circuit obtained as a result of hierarchical expansion of the circuit of FIG. 7 by the logic circuit verification method of the present embodiment;
9 is a circuit diagram of a circuit excerpted from a part of the circuit data of FIG. 8, and a circuit diagram in which this circuit data is divided and described in units of layers.
FIG. 10 is a block diagram showing a second embodiment of the logic circuit verification device of the present invention.
FIG. 11 is a flowchart showing an example of operation in the logic circuit verification method of the present embodiment;
FIG. 12 is a block diagram showing a third embodiment of the logic circuit verification device of the present invention.
FIG. 13 is a flowchart showing an example of operation in the logic circuit verification method of the present embodiment;
14 is a circuit diagram showing a circuit resulting from hierarchical expansion of the circuit of FIG. 3 by a normal method.
FIG. 15 is a circuit diagram showing a circuit obtained as a result of hierarchical expansion of the circuit of FIG. 7 by a normal method;
[Explanation of symbols]
1 Data input part
2 Hierarchy expansion processing part
3 Verification point extraction unit
4 Circuit division part
5 comparison verification part
6 Verification result judgment part
7,7A Partial circuit information extraction unit
8 Verification result output part
11 Constant propagation processor
101 TOP hierarchy
102 blocks
201 SUB hierarchy
111 logic gate C
112 Constant information
211 Logic gate F
212 flip-flop
100, 200, 300, 400, 500, 600 circuits
301, 302, 303, 601, 602 Partial circuit
701-704 buffers

Claims (7)

Information where the logic in the logic circuit to be verified that has a hierarchical structure is regarded as equivalent is extracted as a verification point using a register and / or an external terminal, and the circuit is divided into partial circuits by paying attention to the verification point, and information including the signal name In the logic circuit verification apparatus that verifies the logic equivalence between a plurality of logic circuits by determining the logic equivalence point from the above and verifying the logic equivalence for each corresponding partial circuit,
Data input means for reading circuit information from the circuit data and library of the logic circuit to be verified and converting the circuit information into an intermediate format; and
Hierarchical expansion processing means for generating a hierarchical expansion intermediate format in which the intermediate format is hierarchically expanded and the hierarchical cut terminal information, which is information related to a hierarchical cut terminal that is a boundary terminal between hierarchies in this hierarchical expansion processing, is stored;
A verification point extracting means for outputting the extracted verification point information the validation points to be compared from the hierarchical decomposition intermediate format,
Circuit dividing means for generating partial circuit data by dividing the verification target logic circuit into partial circuits using the hierarchical cut-out terminal information with reference to the hierarchical expansion intermediate format and the verification point information;
Comparison verification means for verifying the logical equivalence of the corresponding partial circuit with reference to the verification point information and the partial circuit data;
A verification result determination unit for determining a verification result by the comparison verification unit;
Partial circuit information extraction means for extracting partial circuit information from the partial circuit data using the hierarchical cut end terminal information in the hierarchical expansion intermediate format when the verification result does not match the determination result;
A logic circuit verification device comprising: verification result output means for outputting the verification result.   2. The logic circuit verification device according to claim 1, further comprising constant propagation processing means for performing constant propagation processing on the intermediate hierarchy development format generated by the hierarchy development processing means. Information where the logic in the logic circuit to be verified that has a hierarchical structure is regarded as equivalent is extracted as a verification point using a register and / or an external terminal, and the circuit is divided into partial circuits by paying attention to the verification point, and information including the signal name In the logic circuit verification apparatus that verifies the logic equivalence between a plurality of logic circuits by determining the logic equivalence point from the above and verifying the logic equivalence for each corresponding partial circuit,
Data input means for reading circuit information from the circuit data and library of the logic circuit to be verified and converting the circuit information into an intermediate format; and
Hierarchical expansion processing means for generating a hierarchical expansion intermediate format in which the intermediate format is hierarchically expanded and the hierarchical cut terminal information, which is information related to a hierarchical cut terminal that is a boundary terminal between hierarchies in this hierarchical expansion processing, is stored;
A verification point extracting means for outputting the extracted verification point information the validation points to be compared from the hierarchical decomposition intermediate format,
Circuit dividing means for generating partial circuit data by dividing the verification target logic circuit into partial circuits using the hierarchical cut-out terminal information with reference to the hierarchical expansion intermediate format and the verification point information;
Partial circuit information extracting means for performing processing for storing the logical information of the partial circuit on the input side with respect to the hierarchical cut terminal in the partial circuit data after the circuit division by the circuit dividing means;
Comparison verification means for verifying the logical equivalence of the corresponding partial circuit with reference to the verification point information and the partial circuit data;
A verification result determination unit for determining a verification result by the comparison verification unit;
A logic circuit verification device comprising: verification result output means for outputting the verification result.   4. The logic circuit verification device according to claim 1, wherein the hierarchy cut terminal information is stored in a buffer set in the partial circuit data at the time of the hierarchy development process. Information where the logic in the logic circuit to be verified that has a hierarchical structure is regarded as equivalent is extracted as a verification point using a register and / or an external terminal, and the circuit is divided into partial circuits by paying attention to the verification point, and information including the signal name In a storage medium storing a logic circuit verification program for verifying logical equivalence between a plurality of logic circuits by determining a logical equivalence point from each of the corresponding partial circuits,
A data input step of reading circuit information from the circuit data of the logic circuit to be verified and the library from the library and converting the circuit information to an intermediate format;
A hierarchical expansion processing step for generating a hierarchical expansion intermediate format in which the intermediate format circuit information is hierarchically expanded and the hierarchical cut terminal information that is a boundary terminal between the hierarchical levels is stored in the hierarchical expansion processing;
A verification point extraction step of extracting a verification point to be compared from the hierarchical expansion intermediate format and outputting it as verification point information;
A circuit division step of referring to the hierarchical expansion intermediate format and the verification point information, performing circuit division using the hierarchy cut terminal information, and outputting partial circuit data;
A comparison verification step of verifying the logical equivalence of the corresponding partial circuit with reference to the verification point information and the partial circuit data;
A verification result determining step for determining a verification result of the verification point information and the partial circuit data;
If the verification result information and the verification result of the partial circuit data match in the verification result determination step, a verification result output step of outputting the verification result;
If the verification point information and the verification result of the partial circuit data do not match in the verification result determination step, the partial circuit data is referred to again, and a new partial portion is used by using the hierarchical cut terminal information in the hierarchical expansion intermediate format. A storage medium storing a logic circuit verification program, comprising: a partial circuit information extraction step for extracting circuit information.   9. The storage medium storing a logic circuit verification program according to claim 8, further comprising a constant propagation processing step for performing constant propagation processing on the intermediate layer expansion format generated in the layer expansion processing step. Information where the logic in the logic circuit to be verified that has a hierarchical structure is regarded as equivalent is extracted using the registers and / or external terminals as verification points, and the circuit is divided into partial circuits by paying attention to the verification points, and information including signal names In a storage medium storing a logic circuit verification program for verifying logical equivalence between a plurality of logic circuits by determining a logical equivalence point from each of the corresponding partial circuits,
A data input step of reading circuit information from the circuit data of the logic circuit to be verified and the library from the library and converting the circuit information to an intermediate format;
A hierarchical expansion processing step for generating a hierarchical expansion intermediate format in which the intermediate format circuit information is hierarchically expanded and the hierarchical cut terminal information that is a boundary terminal between the hierarchical levels is stored in the hierarchical expansion processing;
A verification point extraction step of extracting a verification point to be compared from the hierarchical expansion intermediate format and outputting it as verification point information;
A circuit division step of referring to the hierarchical expansion intermediate format and the verification point information, performing circuit division using the hierarchy cut terminal information, and outputting partial circuit data;
A partial circuit information extraction step for performing a process of storing logical information of the partial circuit on the input side of the partial circuit data in the partial circuit data after the circuit dividing step;
A comparison verification step of verifying the logical equivalence of the corresponding partial circuit with reference to the verification point information and the partial circuit data;
A verification result determining step for determining a verification result of the verification point information and the partial circuit data;
If the verification result information and the verification result of the partial circuit data match in the verification result determination step, the verification result output step of outputting the verification result,
If the verification point information and the verification result of the partial circuit data do not match in the verification result judging step, the logical information stored in the hierarchical cut terminal is used again in the partial circuit information extraction step. A storage medium storing a logic circuit verification program, wherein re-verification is performed in a comparison verification step.

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