JP2853649B2 - How to create a logic simulation model - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for creating a model for logic simulation, and more particularly to a method for creating a model for software logic simulation having a highly accurate timing function.

[0002]

2. Description of the Related Art A software logic simulation model is used in a board-level or system-level logic simulation for the purpose of speeding up the entire logic simulation by performing a logic design in the past and substituting a verified partial macro. ing.

As a method for creating this kind of software logic simulation model, the present inventor has already disclosed in Japanese Patent Application No.
In No. 40168, a logic simulation model corresponding to high-speed logic simulation is automatically synthesized using a logic synthesis tool, and the logic realized by the circuit is extracted from the verified logic circuit. Proposes a method of creating a logic simulation model which adds a timing data after a logical operation to a database.

FIG. 9 shows a flow of creating the software logic simulation model.

Referring to FIG. 9, this logic simulation model creation method is based on a logic circuit 1001 and a circuit design rule database 1002 (in which circuit design rules, prohibitions, restrictions, and the like Y are stored). Circuit 100
1 and a logic synthesizing means 1004 for extracting the logic function of the combinational partial circuit and optimizing the logic, and extracting delay information between external terminals from the logic circuit 1001 and outputting the delay
7, and delay information creating means 1006 for creating the same. When the logic circuit 1001 includes sequential elements such as flip-flops, the logic elements are divided into these sequential elements and combinational circuits therebetween, and each gate used for the logic circuit 1001 is extracted from the circuit design rule database 1002 (gate logic). ), And the logical expression of the divided partial circuit is
04, respectively. Logic synthesis means 1004
Then, the intermediate variable of the multi-stage logic is expanded into a positive logic and a negative logic by using, for example, an expression of Shannon expansion (circuit expansion step 1010), thereby changing the logic of the divided combinational circuit part from multi-stage to two stages. (The number of logic stages change step 1011), and the logic expression is optimized (combinational logic optimization step 1012). In the optimizing step 1012, for example, common factors of the logic are extracted and the logic expression is changed so that the number of logical operations is minimized. The delay information generating means 1 includes a basic gate / basic block delay time extracting step 1013 and a delay calculating step 1014 between external terminals, which receive gate delay information and connection information as inputs.
By 006, an accurate logic simulation model is created.

The software logic simulation model created by this method can reduce the simulation time to the original logic circuit while maintaining logical equivalence with the original circuit by omitting the optimized combinational logic and detailed timing processing. Than to reduce. The delay function is represented by delay information set between external terminals and stored in a delay database.

FIGS. 10 to 11 show examples of creating a software logic simulation model by the procedure shown in FIG.

A circuit diagram shown in FIG. 10A is a logic circuit for performing modeling. In the circuit shown in FIG. 10A, the combinational partial circuit (1
102, 1103 and 1106) and the sequential element (110
1, 1105, and 1104) as shown in FIG. 10B.
06) and sequential elements (1201, 1205, 1204)
Divided into

Circuit 1202 (inverter, AND gate, and buffer) and circuit 1203 (inverter and AN
D gate) and the logical function of the circuit 1206 (OR gate) obtained by optimizing the logical function by the logic synthesizing unit are expressed by an expression 1210 (D = B · C￣, where “￣” indicates inversion) and an expression, respectively. 1211 (E = B￣ · C), Expression 1212 (X
= F + G).

[0010] The circuit 1202 is obtained by the equation 1210 and the circuit 1203.
Is expressed by Expression 1211 and the operation of the combinational partial circuit is expressed by Expression 1212 using a logical expression as shown in Expression 1212 to create a logical expression (see FIG. 10C).

Next, a delay value between external terminals is calculated. Referring to FIG. 11A, this circuit includes an external input terminal A to an external output terminal X, and an external input terminal B to an external output terminal X
11B, delay information is set between terminals A and X and between terminals B and X, respectively, as shown in FIG. 11B.

Finally, the equations (1210), (1211), and (1212) are connected to the sequential elements 1201, 1205, and 1204 as in the original circuit. A delay value is set between B and terminal X, and a model (a broken line indicates external terminal delay information) shown in FIG. 11C is obtained.

[0013]

In the above-described method of creating a logic simulation model, the function of the combinational partial circuit is represented by a logical expression for the purpose of speeding up the simulation. The delay information of the circuit represented by the connection relationship between the value and the gate is lost.

In a logic simulation model created by the conventional technique, the lost delay information is represented by a delay value assigned between external terminals of the circuit. When there are a plurality of paths between the terminal and the output terminal, the delay values of the plurality of paths cannot be individually expressed. For this reason, the delay value of the simulation model often differs greatly from the simulation by the circuit before modeling. Therefore, as a result of the optimization of the logic, a high-speed simulation model can be created, but it is difficult to put to practical use in terms of accuracy, and there is room for improvement.

In order to solve this problem, when a plurality of signal propagation paths exist between external terminals, a delay value is set for each signal propagation path, and a delay value is set for an external input terminal or an internal register which is a determining factor of the signal propagation path. A method has been proposed in which a circuit designer designates the relationship in turn, and at the time of simulation, the selected delay value is reflected in the simulation by referring to the value of the designated external input terminal or internal register.

However, also in this method, designating an external input terminal or an internal register for all path selections requires
There was a problem that was virtually impossible.

Accordingly, the present invention has been made in view of the above circumstances, and an object of the present invention is to extract a logic realized by a circuit from a verified logic circuit by using a logic synthesizing means and to optimize the logic. In the method of creating a high-speed software logic simulation model to be replaced with a generalized logic expression,
It is an object of the present invention to provide a method for significantly improving the delay accuracy of a simulation model.

[0018]

According to the present invention, a logic block is extracted based on verified logic circuit information, and the logic expressed by the logic block is optimized to achieve the equivalent of the logic circuit. In the logic simulation model created by expressing the logic, the sequential element and the combination element are recognized from the logic circuit information, the external terminal and the sequential element are extracted, and the external terminal and the terminal of the sequential element are further defined as nodes. And a delay information generating unit configured to analyze the signal propagation time for each of the partial paths and configured as delay information, wherein an output of the delay information generating unit is used as the timing information of the logical expression.

In the present invention, the delay database stores the delay times of the partial paths separated by the external terminal and the terminal of the sequential element, and the event has passed along with the propagation of the event starting from the external input terminal during simulation. The acquisition and addition of the delay time from the delay database for each partial path are repeated until the event reaches the external output terminal, whereby it is possible to give a correct delay time to a plurality of signal paths existing between the external terminals. This enables accurate delay time analysis.

[0020]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing a logic simulation model creation procedure of the present invention.

Referring to FIG. 1, a logic circuit 101 and a circuit design database file 102 used for design verification of the logic circuit 101 are input, and a gate logic extraction step 105 for creating a logic simulation model 107 is performed. For the logic synthesizing means 104, the method described in the aforementioned Japanese Patent Application No. 7-40168 is referred to.

This gate logic extraction step 105
Then, the logic of each gate used in the logic circuit 101 is extracted, and the logic synthesizing means 104 performs a logic expression by which the simulation can be performed with the least number of operations on the combinational circuit portion of the gate logic extracted in the gate logic extraction step 105. And a logic simulation model 107 is created. Since the logic simulation model 107 includes only logic information and does not have information on the delay of the logic circuit, the logic simulation model 107 is inaccurate in terms of delay as a logic simulation model.

Therefore, the embodiment of the present invention further includes a delay information creating means 106 for creating delay information from the logic circuit 101 in order to create an accurate simulation model in terms of delay.

First, the delay information creating means 106 extracts a sequential element such as a flip-flop, an external input terminal, and an external output terminal from the logic circuit 101 (step 11).
3).

Next, the external terminal and the input terminal and output terminal of the sequential element extracted in step 113 are set as nodes, and the signal propagation path in the logic circuit 101 is divided into partial paths between these nodes (step 114). .

Next, the delay time of the signal propagation path between the external terminal and the terminal of the sequential element is calculated (step 115).
At this time, the delay time is not calculated for the partial path that does not propagate the event input from the external input terminal to the external output terminal during the simulation. For example, if the end node is a data input terminal of an edge-triggered flip-flop, the event input to that terminal does not propagate to the output of the flip-flop. Is not calculated.
By not calculating the delay time of the unnecessary partial path in this way, the time for creating the simulation model can be reduced, and the size of the delay database 108 can be significantly reduced.

FIG. 2 shows an example of a method (algorithm) for calculating a delay time by searching for a partial route for which the delay time needs to be analyzed. The search is performed from the external output terminal toward the external input terminal.

First, attention is paid to a certain external output terminal, and the external output terminal is set as the end point of the partial path (step 20).
1). Next, a sequential element tracking subroutine is called (step 202). After returning from step 202, the search is started from the next external output terminal. Steps 201 and 20 until the search from all the external output terminals is completed.
Repeat 2.

The sequential element tracking subroutine will be described with reference to FIG.

Going back from the node set as the end point of the partial path in the input direction, pay attention to the node one step before (step 2).
10).

The node noted in step 210 is set as the starting point of the partial path (step 211).

The delay time between the start point and the end point of the partial route is calculated, and the calculation result is written to the delay database 108 (step 212).

If the starting point of the partial path is an external input terminal, the subroutine is exited (step 213).

On the other hand, when the starting point of the partial path is the output terminal of the sequential element, the search is continued in the input direction from all the input terminals of the sequential element. When the search for all the input terminals is completed, the process exits the subroutine (step 2).
14).

One of the input terminals of the sequential element is selected and set as the end point of the partial path (step 215).

If the input terminal that is the end point is the data terminal of the edge trigger type flip-flop, the process returns to step 214 without performing the search in the input direction (step 216).

In step 216, if the end point is not the data terminal of the edge-triggered flip-flop, the sequential element tracking subroutine is recursively called (step 2).
17), returning to step 214, which has returned from the subroutine (step 207).

The delay time of the partial path obtained by the method shown in FIGS. 2 and 3 corresponds to the delay time of the combinational partial circuit existing between the external terminal and the terminal of the sequential element.

For the calculation of the delay time, a static timing analysis (Srinivas Devadas, Kurt Keutzer, Sharad) for obtaining a delay time between specific terminals in a circuit from delay values of gates and signal lines without using a test pattern. Malik, “D
elay Computation in Combinational Logic Circuits:
Theory and Algorithms ”, ICCAD '91. pp. 176, 199
1) can be used. Also, the gate delay of the sequential element can be used as it is for the delay time of the partial path starting from the input terminal of the sequential element and ending at the output terminal of the sequential element.

The delay information thus obtained for each partial path is stored in the delay database 108. In addition, in order to search the delay database 108 at high speed, a search table 109 using a hash table or a binary tree may be created.

As search keys for searching the delay database 108, for example, a node serving as a start point (referred to as an "input node"), a node serving as an end point (referred to as an "output node"), and a signal value of a node serving as a start point (Referred to as an “input node value”) and a signal value of the end node (referred to as an “output node value”).

A hash table (search table) 109 assigns a serial number to each node, sets a hash function using the four search keys as variables, and classifies delay information based on a calculation result of the hash function. The delay information is created by associating the storage location of the delay information with the calculation result of the hash function (step 115).

FIG. 6 shows an example of the configuration of a search table based on the delay database 108 and the hash table 109 as an embodiment of the present invention.

Each delay data calculated by the delay information creating means 106 (see FIG. 1) is a hash function using four variables of an input node number, an input node signal value, an output node number, and an output node signal value. With the use of the hash function 700, classification is performed according to the calculation result of the hash function 700. This calculation result is called a “hash value”. The function 700 is set so that each classification does not have a plurality of delay data as much as possible. The output values of the function 700 are arranged in a hash value table 701, and the delay data classified into each hash value is linked in a list structure like 702 and 703. Each delay data has six elements, as indicated by 705, a delay value, an input node number, an input node value, an output node number, an output node value, and a link to the next data.

When acquiring a delay value, the same value as a hash value obtained by giving a variable value to the function 700 is searched on the hash value table 701, and the link of the delay data associated with the matched value is followed. Finally, the four variable values of the input node number, the input node value, the output node number, and the output node value are compared with the elements of the delay data 705, and the one that matches all is the target delay data.

Delay database 1 using search table 109
08 is added at high speed to the logic simulation model 107 as a mechanism delay function for obtaining an output delay value, and is created as a logic simulation model.

FIG. 4 shows an example in which modeling is performed according to the embodiment of the present invention shown in FIG.

The circuit shown in FIG. 4A is a logic circuit for performing modeling. This circuit is shown in FIG.
It has the same configuration as the circuit shown in FIG. As a procedure for modeling a logical function, a method shown in FIGS. 10B and 10C by a conventional technique can be used.

A method for creating delay information will be described. First, from the logic circuit shown in FIG.
04, 305), external input terminal A, external input terminal B,
Extract the external output terminal X. The inputs (H, D, E) of the sequential elements, the outputs (C, F, G) of the sequential elements, and the terminals A, B, and X are set as nodes.

At these nodes, nodes having connection relations (between AH, between CD, between BD, between CE, and between EX)
, Between G and X). The delay information to be set is obtained by static timing analysis in which the nodes A, C, F, and G are set as the starting points, and the nodes H, D, E, and X are set as the end points.

Referring to FIG. 4B, delay information 403 and delay information 405 are represented by a logical expression 1210 (see FIG. 10C,
D = BC￣), that is, in the circuit 302, the delay information 404 and the delay information 406 are expressed by a logical expression 1211 (see FIG. 10C, E
= B￣C) That is, in the circuit 303, the delay information 409 and the delay information 410 are expressed by a logical expression 1212 (see FIG. 10C, X = F
+ G), that is, the circuit 306. Also, the delay information 40
2 is the sequential element 301, and the delay information 407 is the sequential element 30.
5. The delay information 408 corresponds to the delay information of the sequential element 304. The delay information 401 to the delay information 410 are stored in the delay database 108.

In this manner, the delay information of the combinational partial circuit lost by the logic optimization can be expressed by the delay information between the nodes, and can be managed integrally with the delay information of the sequential elements.

Finally, the logical expressions 1210, 1211, 12
12 and the sequential elements 302, 303, and 306 are connected as in the original circuit.
By setting 01 to 410, a model shown in FIG. 4C is obtained.

FIG. 5 shows the operation at the time of simulation as one embodiment of the present invention. Starting the simulation
It starts with a signal change at the input pin (step 600). The event generated in response to this is registered in the event queue (step 601). The events are sequentially retrieved from the event queue (step 602), and the operation of the gate to which the event has propagated is performed (step 603).

It is determined whether or not an event has occurred due to a change in the output value of the gate due to the calculation in step 603 (step 604).
The delay value of the partial path in which the event has propagated is searched for, added to the delay time from the input terminal (step 605; the delay value is obtained by referring to the hash table 109 and the delay database 108), and the event is registered (step 605). Return to 601). If no event has occurred, it is checked whether or not the event remains in the event queue (step 606). If the event has remained, the process returns to event retrieval (step 602). The output value and the delay time are passed to the simulator (step 607), and the simulation using this software model ends. By not searching for and adding delay time when no event has occurred,
Simulation can be performed at a higher speed than when searching and adding the delay time together with the operation of the gate.

In order to explain the embodiment of the present invention in more detail, an embodiment of a method of calculating a delay time at the time of simulation will be described below with reference to FIG. Note that FIG.
From the external input terminal A to the external output terminal X of the logic circuit shown in FIG.
2 shows a signal propagation path to the control unit. In FIG. 7,
Numerical values attached to the partial paths indicated by broken lines indicate delay values between nodes.

If a change occurs in the external output terminal due to a change in the external input terminal A, the signal propagation path from the external input terminal A to the external output terminal X is 801 (path AH-
C-D-F-X) and 802 (Route A-H-C-E-G)
−X), and the delay times are “75” and “60”, respectively.

Consider a case where a signal has propagated along the path 801. When the signal changed at the external input terminal A propagates to the node H, the delay time between A and H is searched in the delay information file, and "0" is obtained as the delay time. The delay time and signal change (event) are propagated to the output side.

Next, a delay time “20” between HC is obtained, and a delay time “0” to the node H is added to obtain “2”.
"0" is propagated to the output side together with the signal change. Similarly, C-
By repeating the search, addition, and propagation of the delay time between D, DF, and F-X to the external output terminal, the path 801 is obtained.
To obtain the delay time “75”.

On the other hand, in the conventional technique described with reference to FIG. 11B, only one delay information is set between A and X, that is, only one of “75” or “60” is set. Was not able to be performed, and compared to the original circuit and the delay time, "1"
5 "may occur.

FIG. 8 shows, for comparison, the average delay error rate in the simulation using the simulation model according to the conventional technique and the average delay error rate in the simulation using the simulation model according to the present invention. . Circuits A to I indicate various logic circuits for benchmarking.

Each average delay error rate (%) was obtained using the following equation (1).

[0063]

(Equation 1)

The average delay error rate indicates the degree of error in the delay time obtained by the simulation using the simulation model with respect to the average of the delay times obtained by the simulation using the original circuit. I have. For example, when the delay time in the original circuit is “100”, the delay time in the simulation model is “15”.
If "0", this average delay error rate is 50%.

As is apparent from the graph shown in FIG. 8, according to the present invention, the average delay error rate is at most about several percent (more than 100% in the conventional method), and the delay error can be significantly reduced. I understand.

[0066]

As described above, according to the present invention,
By analyzing the delay of the partial path in the circuit before optimization and making it into a database, and searching for and adding the delay accompanying the event propagation during simulation to the logically optimized model, the external input terminal, A correct delay time can be given to each of a plurality of signal propagation paths existing between the combinations of the external output terminals, and a simulation model of the delay time with high accuracy can be created.

[Brief description of the drawings]

FIG. 1 is a flowchart of a method for creating a logic simulation model according to an embodiment of the present invention.

FIG. 2 is a flowchart of a delay information creating method according to the embodiment of the present invention.

FIG. 3 is a flowchart of a delay information creating method according to the embodiment of the present invention.

4A and 4B are diagrams for explaining an embodiment of the present invention, in which FIG. 4A shows a circuit diagram applied to the present invention and a signal propagation path thereof, and FIG. 4B shows a configuration of delay information; , (C)
Is a diagram of a logic simulation model.

FIG. 5 is a flowchart when the logic simulation model created according to the embodiment of the present invention is operated.

FIG. 6 is a diagram for describing an embodiment of the present invention, and is a diagram illustrating an example of a configuration of a delay database.

FIG. 7 is a diagram for describing an embodiment of the present invention, and is a diagram illustrating delay calculation.

FIG. 8 is a diagram comparing the effects of the embodiment of the present invention and the conventional technology.

FIG. 9 is a flowchart for creating a conventional logic simulation model.

FIG. 10A is a circuit diagram used for explaining a conventional technique. (B) It is a figure of the logic block extracted from the circuit of (A). (C) is a diagram of an optimized logical expression of the prior art.

11A is a diagram illustrating a signal propagation path of the circuit in FIG. FIG. 2B is a diagram illustrating delay information according to the related art. (C) is a diagram of a logic simulation model according to a conventional technique.

[Explanation of symbols]

101, 1001 Logic circuit 102, 1002 Circuit design rule database 103, 1003 Logic gate 104, 1004 Logic synthesis means 105, 1005 Gate logic extraction step 106 Delay information creation means 107 Logic simulation model 108 Delay database 109 Search table 110, 1010 Circuit Expansion step 111, 1011 Number of logic stages change step 112, 1012 Combinational logic optimization step 113 External terminal / sequential element extraction step 114 Path division step 115 Partial path delay time analysis step 200 All external output terminal processing end determination step 201 External output terminal end point Setting step 202 sequential element tracking subroutine calling step 210 input direction tracking step 211 reaching node start point setting step 212 partial process Delay time calculation step 213 Start point external input terminal judgment step 214 All input terminal processing end judgment step 215 Input terminal end point setting step 216 End point data terminal judgment step 217 Ordered element tracking subroutine recursive call step 301, 302, 303, 304, 305, 306 , 1
101, 1102, 1103, 1104, 1105, 1
106 circuit configuration blocks 401, 402, 403, 404, 405, 406, 4
07, 408, 409, 410 Delay information between nodes 600 Input pattern change detection processing 601 Event registration processing 602 Event retrieval processing 700 Hash function 701 Hash value table 702, 703 Delay data link 704 Delay data 705 Breakdown of delay data 801, 802 Delay path 900 average delay error rate calculation formula 1006 delay information creating means 1007 delay database 1008 hash table 1013 basic gate, basic block delay time extraction step 1014 external terminal delay calculation step 1201, 1202, 1203, 1204, 1205,
1206 extracted partial circuits 1210, 1211, 1212 logical expressions 1301, 1302, 1303, 1304, 1305,
1306 Simulation model building block

Claims (5)

(57) [Claims] A logic block is extracted based on verified logic circuit information, and a logic function expressed by a connection relationship between the logic block and the logic block is optimized to create a logic expression equivalent to the logic circuit. In the method for creating a logic simulation model having logic synthesis means for creating, a sequential element and a combination element in a logic circuit are determined, and an external terminal and a terminal of the sequential element are used as nodes for each partial path from the logic circuit information. Delay information generating means for extracting timing information and calculating a signal propagation time from an input terminal to an output terminal of the logic circuit based on the timing information by adding the signal propagation time according to a signal propagation path in the logic circuit; A logic simulation wherein an output of the delay information creating means is timing information of the logic expression. How to create a use model. 2. A logic block is extracted based on verified logic circuit information, and a logic function expressed by a connection relationship between the logic block and the logic block is optimized to obtain a logic expression equivalent to the logic circuit. (A) inputting delay information and connection information of elements of the logic circuit and extracting external terminals and sequential elements of the logic circuit with respect to the logic expression model output by the created logic synthesis means; (B) With the external terminal and the input terminal or output terminal of the sequential element as nodes, a signal propagation path in the logic circuit
A simulation comprising: a step of dividing a sub-path between these nodes into sub-paths; and (c) a step of calculating a delay time of the sub-path and storing the delay information of the sub-path in a delay database. A method for creating a model for logic simulation, wherein a model obtained by adding a delay time to each partial circuit at that time is used as a model for logic simulation. 3. In the step (c), when calculating a delay time of a partial path of a signal propagation path between an external terminal of the logic circuit and a terminal of a sequential element, the delay time is calculated from an external input terminal of the logic circuit during a simulation. A delay time is not calculated for a partial path that does not propagate the event input to the external output terminal of the logic circuit, and only the delay time of the partial path for which the delay time needs to be analyzed is calculated. 3. The method for creating a logic simulation model according to claim 2, wherein: 4. The delay database stores a delay time of a partial path delimited by an external terminal of the logic circuit and a terminal of a sequential element, and stores a delay time of an event starting from the external input terminal when executing a simulation of the logic circuit. 3. The logic simulation according to claim 2, wherein a delay time is obtained from the delay database for each partial path through which the event has passed along with the propagation, and the addition operation of the delay time is repeated until the event reaches the external output terminal. How to create a model. 5. The method according to claim 2, wherein when accessing the delay information of the partial route in the delay database, a search is performed using a value generated based on the connection information of the partial route as a key. How to create a logic simulation model.