JP3191183B2 - Scan test control gate insertion method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CAD (Computing) system.
er Aided Design) system,
The present invention relates to a method for automatically inserting a scan test control gate into circuit connection information of an already designed circuit, and more particularly to a method for inserting a scan test control gate when a design circuit operates with multiple clocks.

[0002]

2. Description of the Related Art Generally, when a clock-based scan test control gate is inserted into circuit connection information of an already-designed circuit, a scan test is performed from the clock terminals of all flip-flops in a state where all circuit connection information is hierarchically expanded. Searching for control gate insertion position.

First, a flip-flop for starting a search is set, and the search is started from the clock terminal of the flip-flop to the input side. Then, it is ensured that all the outputs of the gates that have been searched for on the input side are connected to the clock terminal of the flip-flop. If the searched gate is a buffer and all outputs of the gate are connected to the clock terminal of the flip-flop, the input side of the buffer is further traced. On the other hand, if all the outputs of the searched gate are not connected to the clock terminal of the flip-flop, or if the searched gate is a gate other than the buffer, a scan test control gate is inserted and the control gate of the control gate is inserted. The output is connected to the clock terminal of the flip-flop with and without passing through a buffer.

When a buffer is connected to the output side of the searched gate, all the output sides are searched, and all the outputs are connected to the clock terminal of the flip-flop even in a state of passing through the buffer. Secure state.

Here, the process of inserting a scan test control gate into the circuit shown in FIG. 15 will be described. First,
The flip-flop 101 is set as a search start flip-flop. The buffer terminal 110 is connected to the clock terminal of the flip-flop 101, and all the outputs of the gate 110 are connected to the clock terminal of the flip-flop 101, and therefore go back to the gate 109. Since the buffer 111 is connected to the output of the gate 109, the output side is searched. Since all outputs of the gate 111 are connected to the clock terminal of the flip-flop, the gate 109 is further advanced to the input terminal. Here, a scan test control gate is inserted on the input side of the gate 109. By the same processing, a scan test control gate is inserted on the input side of the gate 113 and the output side of the gate 114.

FIG. 16 shows a state circuit in which the scan test control gate 116 is inserted in the circuit shown in FIG.

The set scan test control gate and the reset scan test control gate are also inserted in the same manner as the clock scan test control gate, but the description is omitted here.

[0008]

As described above, in the conventional insertion method, a gate connected to a clock terminal, a set terminal, and a reset terminal of a flip-flop is searched first. Next, all the output destinations of this gate are searched. If a gate whose logic does not change is connected to the output destination, the search is further performed to the output destination, and the clock terminal, set terminal, and reset of the flip-flop are searched. The state of connection to the terminal is secured.

In a large-scale circuit, gates whose logic does not change are often connected in multiple stages, and all the output destinations of the gates whose logic does not change are searched, and then a scan test control gate is inserted. Then, a large amount of calculation time is required.

For example, it is assumed that a buffer tree in which five buffers are connected to the output of one buffer is formed in five stages. The number of buffers in the last stage is 625, and the total number of nets is 781. If the clocks of the five flip-flops are connected to the outputs of all the buffers in the last stage, the search from the clock terminals of all the flip-flops is 625 × 781 times. That is, the number of searches is the number of flip-flops × the number of nets in the buffer output.

It is an object of the present invention to provide an insertion method capable of searching for an insertion position of a scan test control gate in a short calculation time.

[0012]

In the scan test control gate insertion method according to the present invention, the retroactive processing for one stage of the buffer is performed in one processing. In the first processing, the search is started from the clock terminal of the flip-flop, and when the insertion position of the scan test control gate is determined,
A clock scan test control gate is inserted at that position. If the buffer is searched and the insertion position of the scan test control gate is not determined, a clock-related dummy gate is inserted into the input side of the buffer, and the first processing ends.

In the second and subsequent processes, a search is performed from the input terminal of the clock system dummy gate inserted in the first and subsequent processes. Similarly to the first time, when the insertion position of the clock scan test control gate is determined, the clock dummy gate is replaced with the clock scan test control gate. If the buffer is searched and the insertion position of the clock scan test control gate is not determined,
Delete the already inserted clock dummy gate,
The clock dummy gate is inserted again into the input side of the buffer.

The second and subsequent processes are repeated until there is no clock-system dummy gate, so that the insertion position of the clock-system scan test control gate is determined.

When the search is started from the set terminal of the flip-flop, the search from the set terminal of the flip-flop is started in the first processing, the same processing as that of the clock is performed, and the set scan test control gate is set. insert.

Similarly, when the search is started from the reset terminal of the flip-flop, the search from the reset terminal of the flip-flop is started in the first processing, and the same processing as that of the clock is performed. Insert the gate.

As described above, when searching for the output destination of the gate,
Even when a buffer is searched, there is no need to search the output destination of the gate, so that the processing time is reduced.

For example, it is assumed that a buffer tree in which five buffers are connected to the output of one buffer is formed in five stages. The number of buffers in the last stage is 625, and the total number of nets is 781. If the clocks of the five flip-flops are connected to the outputs of all the buffers in the last stage, the number of flip-flops output to one buffer is multiplied by the number of flip-flops in the first search. , 625 × 5, 125 × 5 in the second processing, 25 × 5 in the third processing, and 5 × 5 in the fourth processing.
The fifth time is five times. The total number of searches is 3905,
For this example, it is 1/125 compared to the conventional search method.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments.

Referring to FIGS. 1 and 2, first, a node for starting a search is set (step 11). here,
The clock terminal of the flip-flop is set as a search start node. For example, in FIG. 2, the clock terminal of the flip-flop 101 is set as a search start node. Next, the input side gate g1 of the clock terminal is searched (step 12, searching for the gate 110 in FIG. 2). Then, all the output sides of the gate g1 are searched (step 13). The clock terminal of the flip-flops 101 and 102 shown in FIG. These are all clock terminals of the flip-flop (step 1).
4) Go to step 15. In step 15, since g1 is a buffer, a dummy gate is inserted on the input side of g1, that is, between the gate 109 and the gate 110 in FIG.

Similarly, when the above-described steps 11 to 18 are applied to the clock terminals of the other flip-flops shown in FIG. 7, dummy inputs are provided at the input side of the gate 111, the input side of the gate 113, and the input side of the gate 115. A gate is inserted. As a result, a dummy gate is inserted into the circuit shown in FIG. 2 as shown in FIG.

Next, a second process is performed on the circuit shown in FIG.

Referring to FIG. 4, in FIG. 3, the node at which the search is started is set to dummy gate dg1 (step 2).
1). The gate on the input side is searched, and the gate 10 is set as g2.
9 is retrieved (step 22). When all the gates on the output side of g2 are searched, dummy gates dg1 and dg1
Since g2 is searched, that is, all are determined to be dummy gates in step 24, the process proceeds from step 24 to step 25. Since the determination g2 in step 25 (reference numeral 109 in FIG. 3) is a buffer, the process proceeds from step 25 to step 27. And in step 27,
The dummy gates dg1 and dg2 that have already been inserted are deleted, and a new dummy gate dg is added to the input side of the gate 109.
Insert 1 '.

If the search is started from the dummy gate dg3, it is determined in step 24 that the gate 114 other than the buffer is connected in addition to the dummy gate dg3. Will be replaced by

Further, when the search is started from the dummy gate dg4, the gate 114 other than the buffer is searched in step 25. Therefore, the dummy gate dg4 is deleted in step 26, and the scan test control is applied to the output side of the gate 114. A gate will be inserted. As a result, FIG.
Is changed to the circuit shown in FIG.

Further, a third process is performed on the circuit shown in FIG.

Referring to FIGS. 4 and 5, the only remaining dummy gate at this point is dg1 '. In this case, in step 22, the input terminal is searched. The input terminal is regarded as a gate other than the buffer.
Replaces the scan test control gate, and all the dummy gates disappear. As a result, the circuit shown in FIG.
The circuit shown in FIG.

In the above embodiment, the insertion of the clock-based scan control gate has been described. However, the insertion of the set-based scan control gate is processed in the same manner.
In other words, after the processing shown in FIG. 7 (steps 31 to 38) is performed as the first processing, the processing shown in FIG. 8 (steps 41 to 48) is performed so that the circuit shown in FIG. The results shown in FIG.

Similarly, the process shown in FIG. 11 (steps 51-5)
8), the processing shown in FIG.
By performing 8), the result shown in FIG. 14 is obtained for the circuit shown in FIG.

[0030]

As described above, according to the present invention, when searching for an output destination of a gate, even if a buffer is searched, it is not necessary to search for the output destination of that gate. There is an effect that the insertion position of the can be searched.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an example of processing (first time) according to the present invention.

FIG. 2 is a diagram showing a circuit before processing is executed according to the present invention.

FIG. 3 is a diagram showing a circuit after the first processing according to the present invention has been performed on the circuit shown in FIG. 2;

FIG. 4 is a flowchart for explaining an embodiment of processing (second and subsequent times) according to the present invention.

FIG. 5 is a diagram showing a circuit after a second process according to the present invention has been performed on the circuit shown in FIG. 3;

6 is a diagram showing a circuit after a third process according to the present invention has been performed on the circuit shown in FIG. 5;

FIG. 7 is a flowchart for explaining another embodiment of the processing (first time) according to the present invention.

FIG. 8 is a flowchart for explaining another embodiment of the processing (second and subsequent times) according to the present invention.

FIG. 9 is a diagram showing a circuit before execution of processing according to the present invention.

FIG. 10 is a diagram showing a circuit after processing according to the present invention is performed.

FIG. 11 is a flowchart for explaining still another embodiment of the processing (first time) according to the present invention.

FIG. 12 is a flowchart for explaining still another embodiment of the processing (second time) according to the present invention.

FIG. 13 is a diagram showing a circuit before processing is executed according to the present invention.

FIG. 14 is a diagram showing a circuit after execution of processing according to the present invention.

FIG. 15 is a diagram showing a circuit before execution of a conventional process.

FIG. 16 is a diagram showing a circuit after execution of a conventional process.

[Explanation of symbols]

 101-108 Flip-flops 109-113, 115 Buffer 114 Gates other than buffers 201-208 Flip-flops 209-213, 215 Buffers 214 Gates other than buffers 301-308 Flip-flops 309-313, 315 Buffers 314 Gates other than buffers

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/50 G01R 31/28-31/30

Claims (3)

(57) [Claims] When a scan control gate is inserted into circuit connection information in a circuit operating with a multi-clock,
A first step of setting a clock terminal of a first flip-flop for starting a search and setting the clock terminal as a set clock terminal; and retrieving a gate connected to the input side by retrieving the set clock terminal to an input side. A second step of forming a search gate; and when the search gate is a buffer and all outputs thereof are connected to clock terminals of a flip-flop group, a first clock system is connected to the input side of the search gate. A third step of inserting a dummy gate;
When a gate other than the clock terminal of the flip-flop group is connected to the output side of the search gate, a first clock system scan test control gate is provided only between the search gate and the clock terminal of the flip-flop group. And if the search gate is a gate other than a buffer and all of its outputs are connected to the clock terminals of the flip-flop group, the second side is connected to the output side of the search gate. A fifth step of inserting a clock-system scan test control gate of
A sixth step of setting the first clock system dummy gate inserted in the third step as a gate to start a search after applying the fifth step to the fifth step to all circuit connection information; A seventh step of retrieving an input terminal of the first clock system dummy gate and searching for a second gate, wherein the second gate is a buffer, and all outputs are input signals of the first clock system dummy gate. An eighth step of deleting all the first clock-system dummy gates and inserting a second clock-system dummy gate at the input side of the buffer, if the second gate is connected to a terminal; If a gate other than the input terminal of the first clock system dummy gate is connected to the output side of the first clock system dummy gate, the second clock system dummy gate is connected to the third clock system. A ninth step of replacing with a system scan test control gate; and when the second gate is a gate other than a buffer, and all the outputs are connected to the input terminal of the first clock system dummy gate, A tenth step of inserting a fourth clock-system scan test control gate at the output side of the second gate and deleting all of the second clock-system dummy gates; and a clock-system dummy gate from the circuit connection information. And an eleventh step of repeatedly executing the seventh step to the tenth step until all are eliminated. 2. The scan test control gate insertion system according to claim 1, wherein a set terminal is set instead of said clock terminal, and a set system is set instead of said clock system dummy gate and said clock system scan test control gate. A scan test control gate insertion method, wherein a dummy gate and a set scan test control gate are used. 3. The scan test control gate insertion method according to claim 1, wherein a reset terminal is set instead of said clock terminal, and a reset system is set instead of said clock system dummy gate and said clock system scan test control gate. A scan test control gate insertion method, wherein a dummy gate and a reset scan test control gate are used.