JP2967761B2 - Logic synthesis method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a logic synthesizing method and apparatus, and more particularly to a logic synthesizing method for synthesizing a synchronous reset circuit and a logic synthesizing apparatus for synthesizing a synchronous reset circuit.

[0002]

2. Description of the Related Art A conventional logic synthesis method and apparatus of this kind are based on a logic circuit described in a hardware description original language.
Used to generate logic circuits described at the gate level.

First, a conventional logic synthesis apparatus will be described.

FIG. 10 shows a schematic configuration of a logic synthesizing apparatus that generates a logic circuit described at a gate level from a logic circuit described in a conventional hardware description language (Hardware Description Language; referred to as “HDL”). FIG.

Referring to FIG. 10, a conventional logic synthesizer includes (a) a data input unit 1 for reading a hardware description file composed of a logic circuit described in a hardware description language, and (b) a data input unit 1. An input data analysis unit 2 for inputting output data from the system and analyzing the structure of the data;
A logic optimizing unit 3 for optimizing output data from the input data analyzing unit 2 at a logical level, and (d) a circuit optimizing unit 4 for optimizing output data from the logic optimizing unit 3 at a circuit level
(E) an output format conversion unit 5 for converting output data from the circuit optimization unit 4 into a netlist described at a gate level, and (f) outputting the netlist from the output format conversion unit 5 to the outside. A data output unit 6.

The data input unit 1 reads a hardware description file composed of a logic circuit described in a hardware description language from outside the logic synthesis device into the logic synthesis device.

The input data analysis unit 2 analyzes the contents of the data read by the data input unit 1, and analyzes the types of registers described in the hardware description language and restrictions on logic synthesis.

The logic optimization unit 3 performs optimization at a logic level based on the analysis result from the input data analysis unit 2. Especially,
The optimization of the form in the arithmetic unit, for example, the selection of the ripple adder type and the carry look ahead type in the adder, and the optimization of the combinational logic are performed.

The circuit optimizing unit 4 optimizes output data from the logic optimizing unit 3 at a circuit level. In particular, an optimum gate is selected in accordance with the timing and output load capacitance given to the circuit.

The output format conversion unit 5 converts the synthesis result of the circuit optimization unit 4 into an EDIF described at a gate level.
(Electric design interchange format)
Convert to netlist in erilog HDL format.

The data output unit 6 outputs the netlist from the output format conversion unit 5 to outside the logic synthesis device.

FIG. 11 is a diagram for explaining the prior art, and is a diagram showing a processing flow at the time of logic synthesis. FIG. 1 shows the operation of logic synthesis in a conventional logic synthesis device.
This will be described in detail with reference to FIG.

The data input unit 1 reads a hardware description file including a logic circuit described in a hardware description language from outside the logic synthesis device into the logic synthesis device.

A hardware description file is read from the input data section 1, data is converted into a format that can be processed inside the apparatus, and supplied to the input data analysis section 2 (step A).
1).

The contents of the read data are analyzed, and the types of registers described in the hardware description language and the restrictions on logic synthesis are analyzed. Supply (Step A
2).

The optimization is performed at the logical level based on the analysis result from the input data analysis unit 2. In particular, the optimization of the form in the arithmetic unit and the optimization of the combinational logic are performed, and the result of the optimization at the logic level is supplied to the optimization unit 4 at the circuit level (step A5).

The output data from the logic optimizing unit 3 is optimized at a circuit level. Gates to be used are allocated to the circuit so that the timing and area are optimized while observing the design rules such as the maximum output capacity depending on the target technology (step A6).

In the case where the constraints such as the timing of the target circuit are changed due to the change of the peripheral circuit or the like with respect to the result of the logic synthesis and the logic synthesis is required again, or when the circuit is further optimized, the logic level is reduced. The synthesis result is supplied to the optimizing unit 3, and the optimization at the logic level and the optimization at the circuit level are repeated. When the re-synthesis is not necessary, the result of the logic synthesis is supplied to the output format converter 5 (step A7).

When re-synthesis is not necessary, the synthesis result is written in EDIF format or verilog described at the gate level.
The data is converted into a netlist in a format and supplied to the data output unit 6 (step A16).

The netlist of the target circuit is output to the outside of the device, and the process ends (step A17).

Next, a processing flow at the time of conventional logic synthesis will be described in detail with reference to an example in which a flip-flop with synchronous reset is described in a hardware description language.

First, the reset circuit will be described. L
One of the methods for initializing an internal circuit of the SI is to use a reset signal to initialize a register.

The method of initializing the register by the reset signal includes a synchronous reset and an asynchronous reset depending on the timing of the initialization with respect to the clock.

In the synchronous reset operation, when the reset signal becomes active, the output data of the register becomes a logical value 0 in response to the clock signal. For example, when a synchronous reset is applied to a flip-flop of a rising edge operation of a clock signal, when the reset signal becomes active, the logical value of the clock signal becomes 0.
The output data of the flip-flop outputs a logical value of 0 in synchronization with the transition of the logical value to 1 from.

On the other hand, in the asynchronous reset operation, when the reset signal becomes active, the output data of the register becomes a logical value 0 without depending on the clock signal. For example, when an asynchronous reset is applied to a flip-flop of a rising edge operation of a clock signal, when the reset signal becomes active, the output data of the flip-flop becomes a logical value 0 without depending on the timing of the clock signal. Is output.

Next, the hardware description language of the flip-flop with synchronous reset will be described. FIG. 4 is a diagram illustrating an example in which a flip-flop with a synchronous reset of a rising edge operation of a clock signal is described in a hardware description language.

When the reset signal RESET has a logical value of 1, the output data Q of the flip-flop outputs a logical value of 0 in synchronization with the transition of the logical value of the clock signal CLOCK from 0 to a logical value of 1. When the reset signal RESET has the logical value 0, the input data D of the flip-flop is transmitted to the output data Q in synchronization with the transition of the logical value of the clock signal CLOCK from 0 to 1.

In the hardware description language shown in FIG. 4, "// synthesis" described as a comment line is described.
“synchronous_reset RESET” is a constraint used during logic synthesis, and indicates that the signal RESET is a reset signal and that this register is a synchronous reset register.

Next, a description will be given, with reference to a flowchart shown in FIG. 11, of a case where logic synthesis is performed based on the hardware description file shown in FIG.

First, the above-described hardware description file is read (step A1).

Next, the read hardware description file is analyzed (step A2). The reset signal is RES
ET is analyzed to be a synchronous reset flip-flop corresponding to the rising edge of the CLOCK signal.

Next, the logic level is optimized based on the analysis result of the hardware description (step A5), and then the circuit level is optimized (step A6).

FIG. 5 is a circuit diagram showing an example of a result of logic synthesis corresponding to the description of the above hardware description language.

The configuration of the unit M1 includes a terminal RESET.
, Terminal CLOCK, and flip-flop Q0reg
, Two-input NOR gate G11, and inverter gate G
12 are included.

The wiring D is connected to the input terminal of the inverter gate G12, and the wiring n12 is connected to the output terminal. 2 inputs N
The wiring from the terminal RESET and the wiring n12 are connected to the input terminal of the OR gate G11, and the wiring n11 is connected to the output terminal.

The flip-flop Q0reg includes a clock input terminal IN1, a data input terminal IN2, and a data output terminal OUT. Flip-flop Q0r
The wiring from the terminal CLOCK of the unit M1 is connected to the clock input terminal IN1 of the data input terminal I.
The wiring n11 is connected to N2, and the data output terminal OU
The wiring Q is connected to T.

The reset operation of the circuit shown in FIG. 5 will be described.

Immediately after the start of the function verification, the logical values of the terminals CLOCK and RESET of the unit M1 can be determined, but the internal signal D is not fixed to the logical value 0 or 1, but is in an undefined state. The wiring n12 that propagates the signal D in the undefined state from the inverter gate G12 also has an undefined logic value. The logic of the wiring n11 is different from the wiring n12 connected to the input terminal of the two-input NOR gate G11 and the signal RESET.
Is determined by the logical value of When the logic value of the signal RESET is 0, the output value of the two-input NOR gate is undefined because the logic value of the wiring n12 is undefined. When the logical value of RESET is 1, regardless of the logical value of the wiring n12, 2
The output value of the input NOR gate G11 has the logical value 0.

The logic value of the output of the flip-flop Q0reg is undefined when the logic value of the wiring n11 is undefined. Since the logical value of the signal RESET changes to 1 and the logical value of the wiring n11 is determined to be 0, the logical value of the output of the flip-flop Q0reg is determined to be 0 in synchronization with the rise of the clock. As described above, the initialization of the register is executed.

Next, referring to FIG. 10, a conditional branch is made depending on whether or not re-logic synthesis is necessary (step A7).

When performing the logic synthesis again, the logic level optimization process (step A5) is performed again, and then the circuit level logic synthesis (step A6) is performed.

Finally, if no re-synthesis is necessary, the net list is output and the process is terminated (step A16).

FIG. 12 is a circuit diagram showing an example of the result of performing the logic synthesis again.

The circuit shown in FIG. 12 is easily formed especially when the setup value of the reset signal for the register is sufficiently satisfied or when the hold value of the data signal for the register is severe.

The configuration of the unit M1 includes a terminal RESET.
, A terminal CLOCK, a flip-flop Q0reg,
A four-input / output AND / NOR gate G13, an AND gate G14, and an inverter gate G15 are included.

The wiring D is connected to the input terminal of the inverter gate G15, and the wiring n15 is connected to the output terminal. 4 inputs A
The input terminal of one AND gate of the ND NOR gate (composite gate composed of two 2-input AND gates and one NOR gate) G13 is connected to the wiring from the terminal RESET and the wiring n15, and to the input terminal of the other AND gate. , Terminal RE
The wiring from the SET is connected to the wiring D, and the wiring n13 is connected to the output terminal.

A wiring n13 and a wiring D are connected to the input terminal of the two-input AND gate G14, and n1 is connected to the output terminal.
4 are connected.

The flip-flop Q0reg includes a clock input terminal IN1, a data input terminal IN2, and a data output terminal OUT. Flip-flop Q0r
The wiring from the terminal CLOCK of the unit M1 is connected to the clock input terminal IN1 of the data input terminal I.
The wiring n14 is connected to N2, and the data output terminal OU
The wiring Q is connected to T.

The operation of the circuit shown in FIG. 12 will be outlined. Hereinafter, particularly, the logic of the wiring n14 will be described.

When the wiring D is determined, the wiring D, the signal RESET, the inverter gate G15 and the composite gate G
The logic including 13 is equivalent to the propagation of the inverted logic of RESET to the wiring n13. That is, when the wiring D is determined, the RESET signal and the wiring D shown in FIG.
4 to the input terminal IN2 of the flip-flop Q0reg are equivalent to the RESET signal and the logic from the wiring D to the input terminal IN2 of the flip-flop Q0reg shown in FIG.

The reset operation in the function verification of the circuit shown in FIG. 12 will be described in detail.

Immediately after the start of the function verification, the logical values of the terminals CLOCK and RESET of the unit M1 can be determined, but the internal signal D is not fixed to the logical value 0 or 1, but is in an undefined state. The wiring n15 that propagates the signal D in an undefined state from the inverter gate G15 also has an undefined logic value. The logic of the wiring n13 is determined by the logical values of the wiring D and n15 connected to the input terminal of the composite gate and the signal RESET.

When the logical value of the signal RESET is 1, the logical values of the wirings D and n15 are undefined, so that the composite gate G13
Is indefinite. When the logical value of RESET is 0, the logical value of the output of the composite gate G13 becomes logical value 1 regardless of the logical values of the wirings D and n15. 2-input A
The logical value of the output of the ND gate G14 is determined by the wirings n13 and D connected to the input terminal. Signal RE
Only when SET has the logical value 0, the logical value of the wiring n13 connected to the composite gate G13 is determined to be 1;
Is undefined, the output of the two-input AND gate G14 is undefined.

When the logical value of the signal RESET is 1, the logical value of the wiring n13 connected to the composite gate G13 and the logical value of the signal D are undefined, so that the two-input AN
The output of D gate G14 is undefined. Therefore, the wiring n
The logical value of 14 is always undefined. Flip-flop Q
The logical value of the output of 0reg is always undefined without depending on the logical values of the signals RESET and CLOCK because the logical value of the wiring n14 is always undefined. Therefore, the initialization of the register is not performed.

[0055]

As described above, the conventional logic synthesis apparatus and method have the following problems.

(1) The first problem is that at the time of re-logic synthesis,
This means that a synchronous reset circuit in which register initialization is not performed in function verification, for example, a circuit as shown in FIG. 12 may be logically synthesized. Since the logic of the input signal of the register cannot be determined by the reset signal, the register cannot be initialized and the function cannot be verified.

The reason for this is that the optimization of the logic level of the synchronous reset circuit is not prohibited at the time of re-logic synthesis, so that the logic structure of the initialization priority is changed.

(2) The second problem is that the constraint on the synchronous reset added to the hardware description language is valid at the first logic synthesis, but becomes invalid after the first logic synthesis. ,That's what it means.

The reason is that before the logic synthesis, a constraint on the synchronous reset is added to the logic level, but after the logic synthesis, it is converted to the gate level, so that the above constraint is inherited. No, it depends.

(3) The third problem is that a constraint of logic synthesis directly added to a gate cannot be added before logic synthesis.

The reason is that the gate is determined for the first time during logic synthesis.

Accordingly, the present invention has been made in view of the above-mentioned problems, and its object is to re-synthesize, etc.
It is an object of the present invention to provide a method and an apparatus capable of reliably performing logic synthesis of a synchronous reset circuit whose function can be verified even when logic synthesis is repeated.

Another object of the present invention is to provide a method and an apparatus for automatically extracting gates related to a synchronous reset circuit and automatically adding a constraint for logic synthesis at the time of resynthesis.

[0064]

In order to achieve the above object, the logic synthesizing device of the present invention has means for protecting the logic of the synchronous reset of the result of the first logic synthesis. More specifically, reset path detection means for detecting a path from a reset terminal to a synchronous reset register in a first logic synthesis result, and prohibiting logic level reoptimization for a gate on the path. Reset protection constraint generation means for generating a constraint.

In the logic synthesis method of the present invention, a path from a reset terminal to a synchronous reset register is detected in a first logic synthesis result, and a logic level is reoptimized for a gate on the path. Generating a prohibited constraint.

In the logic synthesizing device of the present invention, the reset path detecting means receives the analysis result of the hardware description file and the result of the first logic synthesis, and sets a gate on a path from a reset signal for the synchronous reset circuit to the register. Is detected.

The reset protection constraint generation means generates a constraint for prohibiting the optimization of the logic level of the detected gate.

[0068]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing the configuration of the logic synthesis device according to the first embodiment of the present invention. Referring to FIG. 1, the logic synthesis device according to the first embodiment of the present invention includes (a) a hardware description language (Hardware Description Language;
A data input unit 1 for reading a hardware description file composed of a logic circuit described in “HDL”;
(b) an input data analysis unit 2 for inputting output data from the data input unit 1 and analyzing the data structure; and (c) a logic optimization for optimizing the output data from the input data analysis unit 2 at a logic level. Unit 3, (d) a circuit optimizing unit 4 for optimizing output data from the logic optimizing unit 3 at a circuit level, and (e) a net describing the output data from the circuit optimizing unit 4 at a gate level. Output format converter 5 for converting to a list
(F) a data output unit 6 for outputting a netlist from the output format conversion unit 5 to the outside, and (g) an output data from the circuit optimization unit 4 and an output data from the input data analysis unit 2. And (h) generating a constraint related to reset before re-synthesis from the output data of the reset path detection unit 7 and outputting the data to the logic optimization unit 3. And a reset protection constraint generation unit 8 that outputs The above (a)
Each of (h) to (h) can be implemented by a program executed by an information processing device such as a computer.

The data input unit 1 reads a hardware description file composed of a logic circuit described in a hardware description language from outside the logic synthesis device into the logic synthesis device.

The input data analysis unit 2 analyzes the contents of the data read by the data input unit 1 to analyze the types of registers described in the hardware description language and restrictions on logic synthesis.

The logic optimization unit 3 optimizes at the logic level based on the analysis result from the input data analysis unit 2. Performs optimization of shapes in arithmetic units and optimization of combinational logic.

The circuit optimizing unit 4 optimizes output data from the logic optimizing unit 3 at a circuit level. An optimal gate is selected according to the timing and the output load capacitance given to the circuit.

The output format conversion unit 5 converts the synthesis result of the circuit optimization unit 4 into a netlist in EDIF format or verilog format described at the gate level.

The data output unit 6 outputs the netlist from the output format conversion unit 5 to outside the logic synthesis device.

The reset path detecting section 7 includes a circuit optimizing section 4
In the output circuit, the gate on the path from the reset signal to the register is detected for the register with synchronous reset based on the analysis data from the input data analysis unit 2.

The reset protection constraint generation unit 8 generates a constraint for prohibiting the optimization of the logic at the time of re-synthesis for the gate detected by the reset path detection unit 7.
Output the constraint to.

FIGS. 2 and 3 are diagrams for explaining the operation of the embodiment of the present invention, and are diagrams showing a processing flow at the time of logic synthesis. Regarding the operation of the embodiment of the present invention,
This will be described in detail below with reference to FIGS.
It should be noted that FIGS. 2 and 3 are merely separated for convenience of drawing.

The data input unit 1 reads a hardware description file including a logic circuit described in a hardware description language from outside the logic synthesis device into the logic synthesis device.

A hardware description file (HDL) is read from the input data section 1, converted into a format that can be processed inside the apparatus, and supplied to the input data analysis section 2 (step A1).

The contents of the read data are analyzed to analyze the types of registers described in the hardware description language and restrictions on logic synthesis, and supply the connection information and the restrictions to the logic level optimization unit 3. (Step A2).

It is checked whether or not a synchronous reset logic is included (step A3). If a register with a synchronous reset is included, a temporary register name and a reset signal name assigned internally are sent to the reset path detecting section 7. Supply (Step A4).

Based on the analysis result from the input data analysis unit 2, optimization is performed at a logical level. In particular, the optimization of the form in the arithmetic unit and the optimization of the combinational logic are performed, and the result of the optimization at the logic level is supplied to the optimization unit 4 at the circuit level (step A5).

The output data from the logic optimizing unit 3 is optimized at the circuit level. Gates to be used are allocated to the circuit so that the timing and area are optimized while observing the design rules such as the maximum output capacity depending on the target technology (step A6).

It is determined whether re-synthesis is necessary for the result of the logic synthesis (step A7). In other words, when the constraints such as the timing of the target circuit are changed due to a change in a peripheral circuit or the like with respect to a result of the logic synthesis and the logic synthesis is required again,
Alternatively, when further optimizing the circuit, the synthesis result is supplied to the reset path detection unit 7. If re-synthesis is not necessary, the result of the logic synthesis is supplied to the output format converter 5 (no branch in step A7).

If resynthesis is necessary (yes branch in step A7), it is determined whether or not the target circuit has a register with a synchronous reset (step A8). Based on the register name and the reset signal name, a path from the reset signal to the register is detected for the circuit resulting from the logic synthesis (step A).
9).

The names of the gates on the detected path are listed up and supplied to the reset protection constraint generator 8 (step A).
10).

For the extracted gate name, a constraint for prohibiting logic optimization during resynthesis is generated, and the logic optimization unit 3
Is supplied to the optimization unit 3 at the logic level (step A11 and step A1).
2).

The logic level optimization is performed again only on the part of the target circuit to which the constraint for prohibiting logic optimization is not added, and the result is supplied to the circuit level optimization unit 4 (step A13).

The circuit-level optimization is performed again for the entire target circuit (step A14).

If the result of the second logic synthesis requires further logic synthesis (yes branch in step A15), data is supplied to the logic level optimization unit 3 (step A1).
Return to 3).

If the logic synthesis is not necessary again (no branch in step A15), the result is supplied to the output format converter 5.

If re-synthesis is not necessary, the synthesis result is converted into an EDIF format or verilog format netlist described at the gate level and supplied to the data output unit 6 (step A16).

The netlist of the target circuit is output to the outside of the device, and the process ends (step A17).

Next, the operation and effect of the embodiment of the present invention will be described.

In the embodiment of the present invention, the constraint of prohibiting the optimization of the logic level is added to the logic of the reset signal input to the register of the synchronous reset based on the result of the first logic synthesis. In addition, even when the logic level is optimized for the second time or later, the expected synchronous reset circuit that can easily perform the reset operation at the time of function verification can be held.

Further, except for the necessary parts related to the reset,
Since the optimization at the logic level can be performed again, the structure of the arithmetic unit and the like can be optimized again.

Further, the prohibition of the re-optimization of the reset circuit is limited to only the logic level. Therefore, the entire target circuit is subjected to the optimization at the circuit level, and the circuit whose timing and area are more optimized is improved. Can be logically synthesized.

[0099]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the embodiment of the present invention will be described in detail in order to explain the above-mentioned embodiment of the present invention with a more detailed concrete example. Note that the configuration itself of an embodiment of the present invention is the same as the configuration of the above-described embodiment shown in FIG. 1, and FIG. 2 and FIG. 3 are referred to for the processing.

FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIG.
FIG. 3 is a diagram for explaining an embodiment of the present invention.

Referring to FIGS. 2 to 9, the processing of the logic synthesis system according to one embodiment of the present invention will be described in detail.

[1] First, a hardware description file is read into the logic synthesis device from outside the logic synthesis device (step A1).

FIG. 4 is a diagram showing an example in which a flip-flop with a synchronous reset of a rising edge operation of a clock signal is described in a hardware description language. When the reset signal RESET becomes a logical value 1, the clock signal CLO
In synchronization with the transition of the logical value of CK from 0 to 1
The output data Q of the flip-flop outputs a logical value 0. When the reset signal RESET has the logical value 0, the input data D of the flip-flop is transmitted to the output data Q in synchronization with the transition of the logical value of the clock signal CLOCK from 0 to 1.

[2] Next, the contents of the read data are analyzed (step A2). It analyzes that the register described in the hardware description language is the operation description of the flip-flop synchronized with the rising edge of the clock, and that the synchronous reset operation in which the reset signal is RESET is added.

Also, "// sy" described as a comment line
nthesis synchronous_reset RESET ”is a constraint used during logic synthesis. The signal RESET is used during logic synthesis.
Is generated as a reset signal to generate a synchronous reset register logic.

[3] Next, since a register of a synchronous reset is included (step A3), a temporary register name Q0reg and a reset signal name RESET assigned internally are detected (step A4).

FIG. 6 is a list showing an example of the detected data. “M1 Q0reg FF synchrono”
"us_reset RESET" means that in the unit M1, the register Q0reg is a synchronous reset flip-flop using the signal RESET as a reset signal.

[4] Next, optimization is performed at the logical level for synthesizing the synchronous reset based on the analysis result of the hardware description file (step A5).

[5] Next, circuit-level optimization is performed so that timing and area are optimized while observing design rules such as the maximum output capacity depending on the target technology (step A6).

FIG. 5 is a circuit diagram showing an example of a result of logic synthesis corresponding to the description of the above-described hardware description language. The configuration of the unit M1 includes a terminal RESET and a terminal C.
LOCK, flip-flop Q0reg, 2-input N
An OR gate G11 and an inverter gate G12 are included. Wiring D is connected to the input terminal of the inverter gate G12.
The wiring n12 is connected to the output terminal. 2-input NOR
The wiring from the terminal RESET and the wiring n12 are connected to the input terminal of the gate G11, and the wiring n11 is connected to the output terminal.

The flip-flop Q0reg comprises a clock input terminal IN1, a data input terminal IN2, and a data output terminal OUT. Flip-flop Q0r
The wiring from the terminal CLOCK of the unit M1 is connected to the clock input terminal IN1 of the data input terminal I.
The wiring n11 is connected to N2, and the data output terminal OU
The wiring Q is connected to T.

Immediately after the start of the function verification, the logical values of the terminals CLOCK and RESET of the unit M1 can be determined, but the internal signal D is not fixed to the logical value 0 or 1, but is in an undefined state. The wiring n12 for transmitting the signal D1 in the undefined state from the inverter gate G12 also has an undefined logic value. The logic of the wiring n11 is different from the wiring n12 connected to the input terminal of the two-input NOR gate G11 and the signal RESET.
Is determined by the logical value of When the logic value of the signal RESET is 0, the output value of the two-input NOR gate G11 is undefined because the logic value of the wiring n12 is undefined.

When the logical value of the signal RESET is 1, regardless of the logical value of the wiring n12, the two-input NOR gate G1
The output value of 1 becomes the logical value 0. Flip-flop Q0
The logical value of the output of reg is undefined when the logical value of the wiring n11 is undefined. Since the logical value of the signal RESET transits to 1 and the logical value of the wiring n11 is determined to be 0, the logical value of the output of the flip-flop Q0reg becomes
Determined to be 0 in synchronization with the rise of the clock. As described above, a circuit for executing the initialization of the register is synthesized.

[6] Next, the operation when re-synthesis is necessary will be described. Since the target circuit M1 has the flip-flop Q0reg with a synchronous reset, based on the register name Q0reg and the reset signal name RESET shown in FIG.
A reset signal RESET is applied to the circuit resulting from the logic synthesis.
From the register Q0reg to the register Q0reg (step A9). FIG. 7 is a list showing the detected data.

In FIG. 7, “start M1 / RESET” is
The start of the detected path is determined by the signal RESET of the unit M1.
It is shown that.

"M1 / G11 (nor)" indicates that the next stage of the start point is the NOR gate G11 in the unit M1.

Further, “end M1 / Q0reg (FF)” indicates that the end point of the path is the flip-flop Q0reg in the unit M1.
It is shown that.

[7] Next, the gate on the detected path is extracted (step A10).

FIG. 8 is a list showing the extracted gate information.

In FIG. 8, "M1 Q0reg G11" indicates that the extracted gate is the gate G11 in the unit M1 and relates to the register Q0reg.

[8] Next, for the extracted gate G11, a constraint for prohibiting logic optimization at the time of re-synthesis is generated (step A11). FIG. 9 shows a constraint indicating that the optimization of logic is prohibited during resynthesis.

In FIG. 9, “current_module = M1” is a constraint indicating that the target unit is M1 at the time of synthesis.

"Circuit_op_only G11" is the gate G
Reference numeral 11 denotes a constraint indicating that only optimization at the circuit level is performed, and optimization at the logic level is not performed.

[9] Next, the above constraint is applied to the result of logic synthesis (step A12).

[10] Next, in the target circuit M1, the logic level is re-optimized for a portion to which the constraint for prohibiting the logic optimization is not added, that is, for the gates other than the gate G11 (step A13). .

The result of this logic level reoptimization is shown in FIG.
The logic of the path input from the RESET terminal to the flip-flop Q0reg via the NOR gate G11 is not changed.

Due to the influence of the peripheral circuit of the unit M1, etc.
If the constraint on the unit M1 such as the timing is changed from the previous logic synthesis, the logic other than the gate G11 may be changed.

[11] Next, circuit-level optimization is performed again on the entire target circuit M1 (step A1).
4). The gates optimized for the driving capability of the gates including the gate G11 by changing the constraint such as the timing are:
Selected. However, no change in logic is made.

[12] Next, in the result of the second logic synthesis,
If further logic synthesis is required, optimization at the logic level (step A13) and optimization at the circuit level (step 14) are repeated. In this case, the constraint for inhibiting the optimization of the logic at the time of re-synthesis already added to the gate G11 is effective. Therefore, there is no rearrangement of the logic of the reset circuit when the logic level is reoptimized.

[13] Next, if re-logic synthesis is not required, the synthesis result is converted into an EDIF format or verilog format netlist described at the gate level (step A15).

[14] Finally, the net list is output and the logic synthesis process ends (step A16).

As described above, the logic relating to the reset of the output netlist is constituted by the logic transmitted from the terminal RESET to the NOR gate and input to the register. Can be logically synthesized.

In the above embodiment, the method and apparatus for synthesizing the logic of the synchronous reset circuit have been described. However, the present invention can also be applied to the logic synthesis of the synchronous set circuit and the synchronous set reset circuit. The target register may be a latch.
Furthermore, the target circuit can be handled even if it has a hierarchical composition.

[0134]

As described above, according to the present invention, the following effects can be obtained.

(1) A first effect of the present invention is that a synchronous reset circuit capable of initializing a register in function verification can be surely synthesized even during re-logic synthesis. As a result, the function verification can be easily started, and the man-hour for the function verification can be reduced.

The reason is that, in the present invention, before the re-logic synthesis, the gate related to the synchronous reset circuit
This is because a constraint that prohibits optimization at the logic level is added.

(2) A second effect of the present invention is that the constraint on the synchronous reset described in the hardware description can be automatically added to the corresponding gate. As a result, the number of design steps for adding a constraint to the gate circuit after logic synthesis can be reduced, and the logic of the reset circuit can be reliably maintained even after re-synthesis.

The reason is that, in the present invention, the reset signal name and the register name are automatically extracted from the result of analyzing the hardware description, and the gate between the corresponding reset signal and the register is automatically extracted from the first synthesis result. This is for extracting and automatically adding the constraint on the synchronous reset to the extracted gate.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining an embodiment of the present invention, and is a block diagram showing a schematic configuration.

FIG. 2 is a flowchart for explaining a processing flow according to the embodiment of the present invention.

FIG. 3 is a flowchart for explaining a processing flow according to the embodiment of the present invention;

FIG. 4 is a diagram illustrating an example described in a hardware description language.

5 is a diagram illustrating an example of a design target logic circuit corresponding to the description of the hardware description language illustrated in FIG. 4;

FIG. 6 is a diagram for explaining one embodiment of the present invention;
It is an example showing a list of synchronous reset flip-flops.

FIG. 7 is a diagram for explaining one embodiment of the present invention;
FIG. 7 is a diagram illustrating an example of a path list related to reset.

FIG. 8 is a diagram for explaining one embodiment of the present invention;
FIG. 9 is a diagram illustrating an example of a gate list regarding reset.

FIG. 9 is a diagram for explaining one embodiment of the present invention;
FIG. 3 is a diagram illustrating an example of protection restrictions of a reset circuit.

FIG. 10 is a diagram showing a schematic configuration of a conventional logic synthesizer.

FIG. 11 is a flowchart for explaining a processing flow of a conventional logic synthesis apparatus.

12 is a diagram illustrating an example of a logic circuit to be designed according to the related art, which corresponds to the description of the hardware description language illustrated in FIG. 4, and is a diagram illustrating a circuit for logic synthesis after the second time;

[Explanation of symbols]

n11, n12, n13, n14, n15 Inter-gate wiring CLOCK Clock signal D Data input signal G11 Two-input NOR gate G12, G15 Inverter gate G13 Composite gate G14 Two-input AND gate M1 Unit Q Data output signal Q0reg Flip-flop RESET Reset signal 1 Input unit 2 Input data analysis unit 3 Logic level optimization unit 4 Circuit level optimization unit 5 Output format conversion unit 6 Output device 7 Reset path detection unit 8 Reset protection constraint generation unit 100 Logic synthesis system

Claims (6)

(57) [Claims] 1. A reset path detecting means for detecting a path from a reset terminal to a synchronous reset register in a first logic synthesis result, and prohibiting a logic level reoptimization for a gate on the path. A logic synthesis device comprising: a reset protection constraint generation unit that generates a constraint. 2. A logic optimizing means for optimizing at a logic level, a circuit optimizing means for optimizing output data from the logic optimizing means at a circuit level, and a first logic from the circuit optimizing means. From the synthesis result,
Reset path detecting means for detecting a path from a reset terminal to a synchronous reset register before re-synthesizing logic; and a path from the output data of the reset path detecting means to the reset terminal and the synchronous reset register. Reset protection constraint generation means for generating a constraint for prohibiting logic level optimization for the above gate, and supplying the data with the constraint to the logic optimization means before re-synthesis. A logic synthesizing device, wherein at the time of logic re-synthesis, the logic optimizing means performs a logic-level optimization on a gate of a portion to which a constraint for prohibiting the logic optimization is not added. 3. A data input means for reading a hardware description file comprising a logic circuit described in a hardware description language, and an input data analysis means for inputting output data from the data input means and analyzing a data structure. Logic optimization means for optimizing output data from the input data analysis means at a logic level; circuit optimization means for optimizing output data from the logic optimization means at a circuit level; Output format conversion means for converting output data from the means into a netlist described at a gate level, data output means for outputting the netlist from the output format conversion means to the outside, and output from the circuit optimization means The first logic synthesis result and the output data from the input data analysis means are input and the logic A reset path detecting means for detecting a path from a reset terminal to a synchronous reset register; and a gate on a path from the output data of the reset path detecting means to the reset terminal and the synchronous reset register. And a reset protection constraint generation means for generating a constraint for prohibiting logic level optimization and supplying the data with the constraint to the logic optimization means before re-synthesis. At the time of re-synthesis, the logic optimization means performs logic-level optimization on a gate of a portion to which a constraint for prohibiting logic optimization is not added. A synchronous reset circuit capable of initializing a logic circuit. 4. A path from a reset terminal to a synchronous reset register is detected in a result of the first logic synthesis, and a constraint for prohibiting reoptimization of a logic level is generated for a gate on the path. A logic synthesis method characterized in that: 5. A method of automatically extracting a reset signal name and a register name of a synchronous reset method from a result of analyzing a hardware description language, and automatically extracting a corresponding reset signal and a gate between registers from a first logic synthesis result. And automatically adding a constraint on the synchronous reset to the extracted gate. 6. A logic optimizing means for optimizing at a logic level, a circuit optimizing means for optimizing output data from the logic optimizing means at a circuit level, and a first logic from the circuit optimizing means. From the synthesis result,
Reset path detecting means for detecting a path from a reset terminal to a synchronous reset register before re-synthesizing logic; and a path from the output data of the reset path detecting means to the reset terminal and the synchronous reset register. Reset protection constraint generation means for generating a constraint for prohibiting logic level optimization for the above gate, and supplying the data with the constraint to the logic optimization means before re-synthesis. The logic optimizing means performs logic-level optimization on a part of a gate to which a constraint for prohibiting logic optimization is not added at the time of logic re-synthesis. A recording medium on which a program for causing an information processing device to function is recorded.