JP3047884B2 - Logic synthesis method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a logic synthesizing apparatus and method in circuit design, and more particularly, to a data synthesizing method between two flip-flops in which an arbitrary signal not specified by a clock is input to a clock pin. It is an object of the present invention to provide a logic synthesizing device and a method capable of automatically generating a circuit for guaranteeing the hold of the data without special operation.

[0002]

2. Description of the Related Art The current design automation technology by a computer uses a hardware operation such as HDL (Hardware).
This is performed by describing and verifying in a description language (Description Language), and then performing logical synthesis using a synthesis tool. Currently, the HDL description that can be synthesized is
In most cases, RTL (Register Transfer L) that clearly defines register locations and clocks
evel).

When a synchronous sequential circuit is designed by such an automatic design technique, when the same clock is input to two cells which are flip-flops as shown in FIG. If the minimum delay time during the following stage is shorter than the hold time of the next stage F / F, a circuit that causes a “fall through” of data at the next stage F / F, that is, a hold timing error occurs. It will be designed. In such a case, there is a problem that a manual correction of inserting a delay element between the F / F is required.

In order to avoid such a problem, in the conventional logic synthesis, as shown in FIG. 2, a circuit is generated in a procedure of inputting HDL, executing synthesis, and outputting a netlist. In the above, in a flip-flop in which a clock-specified signal is input to a clock pin, a minimum delay between flip-flops is guaranteed.

[0005] In the above procedure, the minimum delay is guaranteed at the position where the maximum delay is specified. Here, the maximum delay is the time when the input arrives and the signal value which is the output of the F / F is determined. In order for the synchronous sequential circuit to operate correctly,
The minimum delay must be greater than the hold time of the F / F (minimum delay constraint), and the maximum delay must be less than the clock period minus the setup time of the F / F (maximum delay constraint). The prior art of FIG. 2 assumes that the maximum delay has already been met.

The problem of the hold timing error is described in Japanese Patent Application Laid-Open No. 9-54796, entitled "Logic Circuit Layout Data Creation Apparatus". According to the technique described in this publication, a logic synthesis device (logic circuit layout data creation device) determines whether or not a hold timing error occurs based on each extracted delay information,
The above problem is solved by increasing the amount of delay of the clock signal supplied to the clock input terminal of / F.

[0007]

In the prior art described with reference to FIG. 2, it is assumed that a signal designated by a clock is input to a clock pin of a flip-flop.
Therefore, when an arbitrary signal not specified by the clock is input to the clock pin, the minimum delay is not guaranteed, and a circuit in which a hold timing error occurs is synthesized.

The technique described in the above-mentioned Japanese Patent Application Laid-Open No. 9-54796 is based on the premise that a clock-designated signal is input to the clock pin of the F / F.
Therefore, even in this method, the delay amount cannot be increased for an arbitrary signal whose clock is not specified.

Therefore, according to the conventional technique, an arbitrary signal not designated by the clock is supplied to the F / F input to the clock pin.
The minimum delay guarantee of F requires that the synthesis executor intentionally add a minimum delay constraint for each necessary part before synthesis. In the case where the minimum delay constraint is not added, a circuit in which data dropout occurs is synthesized by the subsequent F / F. In such a case, manual correction of inserting a delay element between the F / F is still required.

It is an object of the present invention to provide a logic synthesizing method and apparatus for automatically guaranteeing a minimum delay of a flip-flop in which a signal whose clock is not specified is input to a clock pin.

Another object of the present invention is to provide a recording medium on which a program for executing a logic synthesis method is recorded.

[0012]

A logic synthesis method for automatically generating a circuit for guaranteeing data hold between two flip-flops in which an arbitrary signal whose clock is not specified is input to a clock pin. Reading the HDL description, executing logic synthesis based on the maximum delay constraint, and outputting a netlist; detecting all two cascade-connected flip-flops from the output netlist; When the clock terminals of the flip-flops are connected to the same net, a step of adding a minimum delay constraint between the two flip-flops so as to satisfy the hold time of the next-stage flip-flop; Re-synthesizing by constraints and minimum delay constraints, and outputting a netlist.

Further, the present invention is a logic synthesizing apparatus for automatically generating a circuit for guaranteeing data hold between two flip-flops in which an arbitrary signal whose clock is not specified is input to a clock pin. An HDL reading unit that reads the HDL description, a first logic synthesis unit that executes a logic synthesis based on the maximum delay constraint in the read HDL and outputs a netlist, and a cascade connection from the output netlist. If all the two flip-flops are detected and the clock terminals of the two flip-flops are connected to the same net, the hold time of the next flip-flop is set between the two flip-flops. A minimum delay addition unit that adds a minimum delay constraint so as to satisfy Characterized in that it comprises a second logic synthesizing section for outputting the list.

[0014]

FIG. 3 is a functional block diagram of a logic synthesizing apparatus according to the present invention. This logic synthesizing device comprises an RTL reading unit 10, a logic synthesizing unit 12 using a maximum delay, a minimum delay constraint adding unit 14, a logic synthesizing unit 16 using a maximum delay constraint and a minimum delay constraint, and a netlist output unit 18. .

The minimum delay constraint adding unit 14 includes an F / F detection unit 20, a net detection unit 22, a F / F clock pin destination, and a F / F clock pin.
Net data detector 24 at the F data pin destination, F / F at the net destination
It comprises a detection unit 26, a delay measurement unit 28, a net detection unit 30 at the F / F clock pin destination, a net comparison unit 32, and a minimum delay constraint generation unit 34.

The processing by the logic synthesizing apparatus will be described with reference to the flowcharts of FIGS. 4 and 5 and the schematic diagrams of FIGS.

The RTL reading unit 10 reads an HDL description prepared at the RTL level that embodies the required function (step S1), and executes the logic synthesis unit 1 based on the maximum delay constraint.
Send to 2.

The logic synthesizing unit 12 executes logic synthesis under the maximum delay constraint (step S2), and sends the created netlist to the minimum delay constraint adding unit 14.

F / F detecting section 2 of minimum delay constraint adding section 14
0 extracts all cells that are F / F from the given netlist (step S3). All extracted F
/ F of two cascaded F / Fs (CELL1,
CELL2) is schematically shown in FIG.

The F / F detecting section 20 further detects all F / Fs.
One of the Fs is selected (step S4) and given to the net detector 22 at the F / F clock pin destination and the net detector 24 at the F / F data pin destination. In this embodiment, the CE
Assuming that the F / F of the LL1 is selected, the selected CELL1 is shown by a thick line in FIG.

In the net detecting section 22, the given F / F
The net c1 connected to the clock terminal ClockIN of (CELL1) is detected (step S5) and given to the net comparison unit 32. FIG. 8 schematically shows the net c1.

On the other hand, in the net detecting section 24, the data output terminal DataOUT of the given F / F (CELL1)
Is detected (step S)
6), to the F / F detector 26 at the end of the net. In FIG.
The net n1 is schematically shown.

The F / F detector 26 detects a cell (CELL2) connected to the net n1 (step S).
7). FIG. 10 shows the detected CELL2 by a thick line.
It is determined whether or not the detected cell is F / F (step S8). If the detected cell is an F / F, the net detector 30 at the F / F clock pin destination detects the detected F / F (C
ELL2), the net c2 connected to the clock terminal ClockIN is detected (step S9), and given to the net comparison unit 32. FIG. 11 schematically shows a state where the net c2 is detected.

The net comparing unit 32 compares the nets c1 and c2 and determines whether the nets c1 and c2 are equal (step S10). If they are equal, an instruction is given to the minimum delay constraint generator 34.

In the minimum delay generation section 34, CELL (F /
F) Data output terminal DataOUT of 1 and F / F of the next stage
Between the data input terminal DataIN and CEL
A minimum delay constraint is added so as to satisfy the hold time of L (F / F) 2 (step S11). FIG. 12 shows a state where the minimum delay constraint is added.

In the next step S12, it is determined whether or not there is any other F / F to be selected among the F / Fs extracted in step S3, and if so, the flow returns to step S4.

In step S8, if the cell 2 connected to the net n1 is not an F / F, the F / F detecting section 26 at the end of the net performs the F / F (CELL3) of the next stage.
The path up to is extracted (step S13).

The delay measuring section 28 calculates the start point F / F (C
The delay time between the ELL1) and the end point F / F (CELL3) is measured (step S14), and (CELL1 and CE)
It is determined whether (hold time of CELL3) is greater than (delay time with LL3) (step S15).
If the delay time is smaller than the hold time, it is determined that the minimum delay constraint is not satisfied, and the process proceeds to step S9. If the delay time is longer than the hold time, it is determined that the minimum delay constraint is satisfied, and the process proceeds to step S12. Step S1
If there are no more F / Fs to select in 2, the logic synthesis unit 16
Performs re-logic synthesis under the maximum delay constraint and the minimum delay constraint (step S16). The netlist output unit 18
Output the netlist that is the result of the synthesis (step S
17). In the output netlist, as shown in FIG. 13, delay elements are inserted between the two cells so as to satisfy the minimum delay constraint.

[0029]

According to the present invention, after combining the first maximum delay, a point where flip-flops to which the same signal is input to the clock pin is directly connected to each other regardless of the clock signal is detected and the flip-flop is detected. Since a circuit that guarantees the minimum delay during re-synthesis is generated by providing a constraint to guarantee the minimum delay between them, the flip-flop that inputs an arbitrary signal whose clock is not specified to the clock pin is generated. It is possible to automatically synthesize a circuit that does not cause slip-through.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating two F / Fs to which the same clock is input.

FIG. 2 is a diagram showing a conventional technique.

FIG. 3 is a functional block diagram of a logic synthesis device according to the present invention.

FIG. 4 is a flowchart illustrating a process performed by the logic synthesis apparatus.

FIG. 5 is a flowchart illustrating a process performed by the logic synthesis device.

FIG. 6 shows two cascade-connected F / Fs (CELL1, CELL
ELL2).

FIG. 7 is a diagram illustrating selected CELL1 by a bold line.

FIG. 8 is a diagram schematically showing a net c1.

FIG. 9 is a diagram schematically showing a net n1.

FIG. 10 is a diagram showing detected CELL2 by a thick line.

FIG. 11 is a diagram schematically illustrating a state in which a net c2 is detected.

FIG. 12 is a diagram illustrating a state where a minimum delay constraint is added.

FIG. 13 is a diagram showing a state where a delay element is inserted between two F / Fs.

[Explanation of symbols]

 Reference Signs List 10 RTL reading unit 12 Logic synthesis unit based on maximum delay 14 Minimum delay constraint addition unit 16 Logic synthesis unit based on maximum delay constraint and minimum delay constraint 18 Netlist output unit 20 F / F detection unit 22 Net detection of F / F clock pin destination Unit 24 F / F data pin destination net detection unit 26 net destination F / F detection unit 28 delay measurement unit 30 F / F clock pin destination net detection unit 32 net comparison unit 34 minimum delay constraint generation unit

Claims (9)

(57) [Claims] 1. A logic synthesis method for automatically generating a circuit for guaranteeing data hold between two flip-flops in which an arbitrary signal whose clock is not specified is input to a clock pin, comprising: And executing logic synthesis based on the maximum delay constraint to output a netlist. From the output netlist, detect all two cascade-connected flip-flops and detect the clocks of the two flip-flops. When the terminals are connected to the same net, a step of adding a minimum delay constraint between these two flip-flops so as to satisfy the hold time of the next-stage flip-flop; Re-synthesizing by constraints and outputting a netlist. 2. The step of adding the minimum delay constraint,
(A) extracting all cells that are flip-flops from a given netlist; (b) selecting one of all extracted flip-flops; and (c) selecting the selected flip-flop. Detecting a first net connected to the clock terminal of the first flip-flop; and (d) detecting a second net connected to the data output terminal of the selected flip-flop; (E) detecting a cell connected to the second net; (f) determining whether the detected cell is a flip-flop; and (g).
Detecting the third net connected to the clock terminal of the detected second flip-flop if the detected cell is a flip-flop; and (h) detecting the first net and the third net. And determining whether the first net and the third net are equal; and
(I) when the first net is equal to the third net, the hold time of the second flip-flop is set between the output of the first flip-flop and the input of the second flip-flop. 2. The method according to claim 1, further comprising: adding a minimum delay constraint so as to satisfy the condition; and (j) repeating the steps (b) to (i).
Logic synthesis method as described. 3. If the cell detected in the step (f) is not a flip-flop, extracting a path to a next-stage third flip-flop; and the first flip-flop and the third flip-flop. Measuring the delay time between the third flip-flop and the third flip-flop if the delay time is smaller than the hold time of the third flip-flop, and determining that the minimum delay constraint is not satisfied. 3. The method according to claim 2, further comprising the step of: g). 4. A logic synthesizer for automatically generating a circuit for guaranteeing data hold between two flip-flops to which an arbitrary signal whose clock is not specified is input to a clock pin, comprising: An HDL reading unit that reads a HDL, a first logic synthesis unit that executes a logic synthesis based on a maximum delay constraint using the read HDL, and outputs a netlist, and two cascade-connected units of the output netlist. Are detected, and if the clock terminals of the two flip-flops are connected to the same net, the time between these two flip-flops is set so as to satisfy the hold time of the next flip-flop. Performs re-synthesis using the minimum delay addition unit that adds the minimum delay constraint and the maximum delay constraint and the minimum delay constraint, and outputs a netlist And a second logic synthesizing unit. 5. A first flip-flop for extracting all cells that are flip-flops from an output netlist and selecting one of the extracted flip-flops from the output netlist. A first net detector for detecting a first net connected to the clock terminal of the selected first flip-flop; and a first net detector connected to the data output terminal of the selected flip-flop. A second net detection unit for detecting a second net; a second flip-flop detection unit for detecting a cell connected to the second net and determining whether the detected cell is a flip-flop And a third net for detecting a third net connected to the clock terminal of the detected second flip-flop if the detected cell is a flip-flop. Comparing the preparative detector, and the first net and said third net, first
A net comparing unit that determines whether or not the first net is equal to the third net; and, when the first net and the third net are equal, the output of the first flip-flop and the second net. 5. The logic synthesis device according to claim 4, further comprising: a minimum delay constraint generation unit that adds a minimum delay constraint so as to satisfy a hold time of the second flip-flop between the input of the flip-flop and the input of the flip-flop. . 6. If the cell detected by the second flip-flop detector is not a flip-flop, a path to a next third flip-flop is extracted, and the first flip-flop and the third flip-flop are extracted. A delay measuring unit for measuring a delay time between the third flip-flop and the third flip-flop; if the delay time is smaller than a hold time of the third flip-flop, it is determined that the minimum delay constraint is not satisfied; 6. The logic synthesis device according to claim 5, wherein the third net detector detects a net connected to a clock terminal of a third flip-flop. 7. A program for executing a logic synthesis method for automatically generating a circuit for guaranteeing data hold between two flip-flops to which an arbitrary signal whose clock is not specified is input to a clock pin. Reading the HDL description, executing logic synthesis under the maximum delay constraint, and outputting a netlist; and detecting all two cascaded flip-flops from the output netlist. If the clock terminals of the two flip-flops are connected to the same net, a minimum delay constraint is added between the two flip-flops so as to satisfy the hold time of the next flip-flop. Steps for performing re-synthesis with maximum delay constraint and minimum delay constraint and outputting a netlist Recording medium, which comprises a. 8. The step of adding the minimum delay constraint,
(A) extracting all cells that are flip-flops from a given netlist; (b) selecting one of all extracted flip-flops; and (c) selecting the selected flip-flop. Detecting a first net connected to the clock terminal of the first flip-flop; and (d) detecting a second net connected to the data output terminal of the selected flip-flop; (E) detecting a cell connected to the second net; (f) determining whether the detected cell is a flip-flop; and (g).
Detecting the third net connected to the clock terminal of the detected second flip-flop if the detected cell is a flip-flop; and (h) detecting the first net and the third net. And determining whether the first net and the third net are equal; and
(I) when the first net is equal to the third net, the hold time of the second flip-flop is set between the output of the first flip-flop and the input of the second flip-flop. 8. The method according to claim 7, further comprising: adding a minimum delay constraint so as to satisfy the condition; and (j) repeating the steps (b) to (i).
The recording medium according to the above. 9. If the cell detected in the step (f) is not a flip-flop, extracting a path to a next third flip-flop; and the first flip-flop and the third flip-flop. Measuring the delay time between the third flip-flop and the third flip-flop if the delay time is smaller than the hold time of the third flip-flop, and determining that the minimum delay constraint is not satisfied. 9. The recording medium according to claim 8, further comprising: g).