JP2845478B2 - Logic circuit delay time analyzer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to an apparatus for analyzing a delay time of a logic circuit of a digital system, in particular, when the delay time of the logic circuit is larger than an expected value. The present invention relates to a delay time analysis device for a logic circuit that detects a circuit portion described as follows.

(Prior Art) In the design of a logic circuit, it is necessary to design not only a logical function but also a design constraint on a delay time (hereinafter referred to as a timing constraint).
For this reason, verification of whether or not the designed logic circuit operates correctly generally includes not only function verification by logic simulation or the like but also timing verification for verifying whether timing constraints are satisfied. Items to be verified in the timing verification include expectation that the setup time and hold time of the flip-flop are satisfied, that there is no hazard in the clock signal, and that the maximum delay time of the combinational circuit is the clock cycle. The following description relates to the timing verification of the maximum delay time of the combinational circuit portion (hereinafter referred to as delay time analysis).

Conventionally, path enumeration (eg, MAWo
by ld: “Design Verification and Performance Analys
is ", 15th Design Automation Conference, p264−270,19
78) and methods based on PERT (eg, RBHitchcock et al .: "Timing Analysis of Computer Hardware", IBM J.
RES. DEVELOP., Vol. 26 no. 1, p100-105, 1982), etc., to calculate the delay time of the combinational circuit. As a result, if there is a signal path whose delay time exceeds the expected value (such a signal path is hereinafter referred to as a critical path), the designer analyzes the logic on the critical path and determines that the delay time is less than the expected value. The logic circuit has been modified (hereinafter referred to as “timing modification”).

The timing correction can be generally solved by finding a partial circuit causing the criticality and correcting the partial circuit so that the circuit operates at higher speed. However, in the delay time analysis using the conventional delay time calculation tool, the partial circuit cannot be automatically detected. Therefore, it is necessary for the designer to analyze the logic on the critical path to find the partial circuit. When the number of stages is large, it is difficult to analyze the logic on the critical path and find the partial circuit that is causing the critical path, and as a result, there is a problem that it takes a long time to correct the timing.

(Problems to be Solved by the Invention) As described above, the conventional delay time analysis apparatus cannot automatically detect a partial circuit that causes a critical path, and thus places a heavy burden on a designer.

The present invention has been made in view of the above problems,
When a critical path exists in the delay time analysis, it is possible to easily find a partial circuit that causes the critical path and improve the design efficiency.

[Configuration of the invention]

(Means for Solving the Problems) A delay time analysis device according to the present invention is a delay time analysis device having delay time calculation means for obtaining a signal propagation path in a logic circuit and its delay time. When there are a plurality of critical paths larger than the expected value, a path number calculating unit that calculates the number of paths of the critical path including the element for each element,
A path number specifying unit that specifies a range of the number of paths; and an element detecting unit that detects an element whose number of paths calculated by the path number calculating unit is included in the range of the number of paths specified by the path number specifying unit. It is characterized by:

(Operation) In the present invention having the above configuration, when a plurality of critical paths exist whose delay time is longer than an expected value,
First, the number-of-paths calculating means calculates the number of critical paths (the number of paths) for each element in the logic circuit including the element, and then the element detecting means calculates the path of each element calculated by the number-of-paths calculating means. Whether the number is included in the range of the number of paths specified by the number-of-paths specifying means is compared, and elements included in the range of the number of paths are detected and output.

In this manner, by automatically detecting a partial circuit candidate that causes a critical path, the time required for timing correction can be reduced, and design efficiency can be improved.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a delay time analyzing apparatus according to the present embodiment. This device includes a delay time calculating unit 1
, A path number calculation unit 2, a path number designation unit 3, an element detection unit 4, a logic circuit data storage unit 5, and a critical path data storage unit 6. The logic circuit to be subjected to the delay time analysis is stored in the logic circuit data storage unit 5. The delay time calculation unit 1 calculates the delay time of each signal path in the logic circuit data, and if there is a critical path as a result of the delay time calculation, stores the signal path and the delay time in the critical path data storage unit. 6 is stored. When a plurality of critical paths exist as a result of the delay time calculation, the number-of-paths calculation unit 2 calculates the number of critical paths (the number of paths) for each element in the logic circuit that includes the element, and It is stored in the circuit data storage unit 5. The number-of-paths designation unit 3 receives designation information of the number of paths from an input device such as a keyboard and stores the information. Element detector 4
Compares the number of paths of each logic element calculated by the number-of-paths calculation unit 2 stored in the logic-circuit-data storage unit 5 with the specification information of the number of paths stored in the number-of-paths specification unit 3, and Is in the range specified by the path number specification information, the element name of the logical element is output.

Now, a case where the delay time analysis of the logic circuit shown in FIG. 2 is performed will be described as an example. In FIG. 2, G1 to G12 are element names, S
1 to S19 indicate signal line names, and A to H indicate input / output terminals. Here, elements G1 to G4 are NOT gates, and element G5
Is a NOR gate, elements G6 to G10 are AND gates, element G11 is NAND
The gate, element G12, is an EXOR gate. The logic circuit data is stored in the logic circuit data storage unit 5 in the format shown in FIGS. Here, the logic circuit data includes an element table and a signal table. The element table stores element names, element types, terminals, and names of signal lines connected to the terminals for each logical element.
The signal table stores, for each signal, a signal line name, an element name and terminal of a source (start point of a signal line), and an element name and terminal of a destination (end point of a signal line). In addition, an area for storing the calculated number of paths is secured in the element table.

The processing for the logic circuit data is performed as follows. The delay time calculation unit 1 calculates the delay time of each signal path in the logic circuit data by the path enumeration method, and if a critical path exists as a result of the delay time calculation, compares the signal path and the delay time with the critical path. .Data storage unit 6
To be stored. (Hereinafter, for the sake of simplicity, the delay time associated with the capacitance of the signal line is ignored.) The delay time of each logic element is given as shown in FIG. 4, and the allowable delay time is 20 [ns].
, The critical path data is calculated as shown in FIG. If there are a plurality of critical paths as a result of the delay time calculation, the number-of-paths calculating unit 2 determines the number of critical paths (including the element) for each element in the logic circuit according to the processing flow shown in FIG. (The number of routes). FIG. 7 shows the contents of the number of paths in the element table of the resulting logic circuit data storage unit 5.

Next, assuming that the number of paths is 5 or more as the range of the number of paths, the number-of-paths specifying unit 3 stores “GE.5” and outputs it to the element detecting unit 4. The element detecting unit 4 compares each element (excluding the input terminal and the output terminal) in the element table shown in FIG. The element name of is output. In this case, “G3, G6, G7, G
8, G9, G10, G11 ". Among these, the elements other than G10 constitute a partial circuit, and therefore, this partial circuit (second
It can be guessed that it is the cause of the critical path. By adjusting the timing by focusing on the broken line portion of the logic circuit shown in FIG. 2, for example, by modifying the logic circuit as shown in FIG. 8, it is possible to exclude the critical path.

The present invention is not limited to the embodiments described above. For example, in the above embodiment, the element name is output when the candidate of the partial circuit causing the critical path is detected. However, this partial circuit is indicated on the circuit diagram using the logic circuit diagram editor. You may do it.

〔The invention's effect〕

As described above, according to the present invention, in the logic circuit timing verification, when a critical path exists, a partial circuit candidate causing the critical path can be automatically detected, and the timing correction work can be performed efficiently. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram of a delay time analyzing apparatus according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a logic circuit for performing delay time analysis, and FIG. 3 is a logic diagram of the logic circuit shown in FIG. FIG. 4 is a diagram showing circuit data, FIG. 4 is a diagram showing a delay time of each element,
FIG. 5 is a diagram showing a result of calculating a delay time for each signal path of the logic circuit shown in FIG. 2 to obtain a critical path, FIG. 6 is a processing flow of a path number calculation unit, and FIG. FIG. 8 is a diagram showing the number of paths as a processing result of the number-of-paths calculating section. FIG. 8 is a logic circuit diagram of a result obtained by performing timing correction on a partial circuit obtained as an output result of the element detecting section. DESCRIPTION OF SYMBOLS 1 ... Delay time calculation part, 2 ... Number of paths calculation part 3 ... Number of paths designation part, 4 ... Element detection part 5 ... Logic circuit data storage part 6 ... Critical path data storage part

Claims (1)

(57) [Claims] 1. A delay time analyzing apparatus having a delay time calculating means for obtaining a signal propagation path in a logic circuit and a delay time thereof, wherein there are a plurality of critical paths in which the delay time of the logic circuit is larger than an expected value. If you have
Path number calculating means for calculating the number of paths of the critical path including the element for each element; path number specifying means for specifying the range of the number of paths; An element detecting means for detecting an element included in the range of the number of paths designated by the number designating means.