JP2896315B2 - Logic simulation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method.

[0002]

2. Description of the Related Art In the design of a digital circuit, the operation of a circuit module or its internal structure is described using a hardware description language, a simulation is performed using a logic simulation device, and it is verified that the above circuit description is correct. Is used.

Here, in verification of a circuit description by simulation, trace processing is often used. The trace processing is a function in which a simulator specifies a signal to be observed by a designer in the circuit description, and the simulator outputs the value of the signal at a time when a simulation time or a simulation cycle is updated. The designer can look at the traced signal value or
By comparing with the simulation expected value data, it is confirmed whether or not a desired simulation result is obtained. If the trace result is different from the expected value, the designer adds another signal that may cause an error as a signal to be traced, and executes the simulation again until the time when the signal value becomes abnormal. Identify an error in the circuit description.

[0004] The collection of traces is disclosed in Japanese Patent No. 1665055.
The signal whose value has changed, as shown by the symbol,
In general, a method of storing and outputting a signal identifier and a signal value as a pair is common. According to this method, a signal value at a later time can be obtained at high speed from a trace result and a signal at a specific time value, and the amount of data to be traced can be reduced.

On the other hand, in debugging a circuit description, a function is provided in which a simulation is interrupted at a certain time, and a signal value of interest is observed at that time, and when the signal value is different from an expected value, the signal value is looked back one time at a time. For example, it is possible to know from which time the signal value abnormality has occurred, and it can be expected to improve the efficiency of the debugging work.

However, in the above trace collection method, if the signal value of interest does not change at the time to be confirmed, the last updated time before that time and the value at that time must be searched. In addition, there is a problem that it is not possible to immediately go back one time at a time from the simulation interruption time to the previous value.

Further, the trace processing has a large effect on the simulation speed, and the simulation speed becomes slower as the amount of trace output increases. Therefore, a method for further reducing the amount of trace output is required.

[0008]

As described above, in the conventional logic simulation method, in order to obtain a value of a signal of interest at a time desired to be confirmed from a simulation result, a change occurs in the signal value at that time. Otherwise, the last updated time before that time and the value at that time had to be searched, and the signal value at the desired time could not be obtained at high speed.

The present invention has been made in view of the above circumstances, and in verification of a circuit description by a logic simulation, a trace result and a signal value at a time preceding a specific time value of a signal to a time earlier than the specific time value. It is an object of the present invention to provide a logic simulation method capable of obtaining a high speed. Another object of the present invention is to reduce the amount of trace output.

[0010]

Means for Solving the Problems The present invention (claim 1) provides:
First buffer means for temporarily storing a first signal value, second buffer means for temporarily storing a second signal value, and the first and second signals from the first and second buffer means. Comparing means for comparing the signal value, trace information obtained from the output result of the comparing means, storing means for storing the trace information, and third buffer means for temporarily storing the signal value at a specific simulation time. A logic simulation method comprising: restoring means for restoring to the immediately preceding signal value based on a signal value and the trace information, and repeatedly executing a logic simulation by a predetermined simulation unit time based on information describing a logic circuit. A simulation result comprising at least a simulation time and each signal value from an output result of the comparing means. Outputting, and when at least one signal value of the simulation results obtained in the step has changed from the value in the immediately preceding simulation result, identifying the changed signal in accordance with the simulation time in the simulation result. And storing the difference information between the signal value before the change and the signal value at the current time in the storage means as the trace information, based on the trace information stored in the step. Restoring the signal value at the immediately preceding simulation time from the signal value at the simulation time by the restoring means. The present invention (Claim 2)
Comprises a first buffer means for temporarily storing a first signal value, a second buffer means for temporarily storing a second signal value, and the first and second signals from the first and second buffer means. A comparing means for calculating a remainder obtained by dividing a difference between the signal values of the two in the signal value range, a trace information obtained from an output result of the comparing means, and a storage means for storing the trace information; A third buffer unit for temporarily storing signal values, and a table storing difference information between the first signal value and the second signal value, and referring to the table based on the trace information, Restoring means for restoring from a signal value at a specific simulation time to a signal value immediately before, and executing a logic simulation in a predetermined simulation unit time based on information describing a logic circuit. A logic simulation method that is repeatedly executed while proceeding, wherein a step of outputting a simulation result comprising at least a simulation time and each signal value from an output result of the comparing means; and a step of outputting a simulation result obtained in the step. When at least one signal value changes from the value in the immediately preceding simulation result, corresponding to the simulation time in the simulation result,
The storage means as the trace information, wherein information for specifying a changed signal and difference information obtained from a remainder obtained by dividing a difference between a signal value before the change and a signal value at the current time for the changed signal by a signal value range. And restoring the signal value at the immediately preceding simulation time from the signal value at a specific simulation time by the restoration means with reference to the table from the trace information stored in the step. It is characterized by the following.

On the other hand, the present invention provides a logic simulation apparatus for simulating a logic circuit, wherein a simulation time at which at least one signal value has changed, and each signal whose value has changed at the simulation time are before and after the change. And a restoring means for restoring the signal value at the immediately preceding time from the signal value at a specific time by using the difference from the signal value at a specific time.

Preferably, the tracing result output means outputs an offset corresponding to the signal whose value has changed and a difference corresponding to the signal. Also,
Preferably, the trace output means outputs the offset corresponding to the signal whose value has changed, the number of the difference that continues from the offset, and the difference continuously from the offset by the number.

[0013] Preferably, the trace output means includes:
An identifier corresponding to the signal whose value has changed and a difference corresponding to the signal are output. Preferably, the trace output means outputs a difference between a bitmap indicating presence / absence of a signal value change for each signal and a signal whose value has changed. Preferably, the trace output means outputs a difference between the signal whose value has changed and an identifier sequence of a signal having a difference corresponding to the difference.

[0014]

According to the present invention, in the trace collection at the time of the logic simulation, the difference value of the signal value at each simulation time is trace-collected for a signal whose value has changed, and when the simulation has advanced to a certain simulation time. Thus, the previous value of the signal can be restored using the difference between the signal values included in the trace result and the signal value at that time.

Therefore, the process of searching for the last updated time and the value at that time, as in the conventional case, is completely eliminated, so that the signal value at the immediately preceding time can be obtained at high speed.

Further, by following the difference between the signal values included in the trace result, it is possible to easily and quickly obtain a signal value at a desired time. In addition, by changing the trace output format that specifies which of the signals to be traced has changed during trace collection, the trace amount can be further reduced as compared with the conventional method, and the trace processing can be suppressed. Can be performed at high speed, and the simulation can be performed at higher speed.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) First, a first embodiment of the present invention will be described.

(Main Configuration and Operation of the First Embodiment) The logic simulation apparatus according to the present embodiment comprises a simulation time at which at least one signal value changes, and a signal at each value whose value changes at the simulation time. A trace result output unit that outputs an exclusive OR (XOR) of the signal values before and after the change as a trace result, and a unit that restores the immediately preceding signal value from the signal value at a specific time using the difference. Have.

According to this embodiment, at the time when the simulation has proceeded to a certain simulation time, the immediately preceding value of the signal is restored using the XOR of the signal value output by the trace result output means and the signal value at that time. Becomes possible.

Further, by changing the trace output format, it is possible to reduce the amount of trace output and reduce the decrease in simulation execution speed. (Effect of First Embodiment) In the conventional trace collection method,
Although the identification value of the signal whose value has changed and the signal value are output as a pair, there is a disadvantage that when the simulation execution is interrupted and the signal value at the previous time is desired to be observed, the value cannot be obtained immediately. Was. In this embodiment, by using the XOR of the signal value of the previous time at each simulation time as trace information, it is possible to calculate the signal value retrospectively.

(Specific Description of First Embodiment) FIG. 1 is a diagram showing a schematic configuration of a logic simulation apparatus according to this embodiment.

The simulation executing section 11 executes a simulation of a logic circuit. Trace control unit 12
Receives the signal value of the trace target from the simulation execution unit 11 and controls the storage destination of the signal value.

First buffer 13 and second buffer 14
Temporarily holds the signal value output from the trace control unit 12. The trace information output unit 15
The comparison unit 151 compares the signal values held by the units 3 and 14 to calculate an XOR value, and the determination unit 152 determines whether the XOR value is 0.

The trace information storage section 16 stores a trace output from the trace control section 12 or the trace information output section 15. The signal value restoring unit 17 restores the signal value in the past simulation cycle by going back to the simulation cycle after the simulation execution is stopped, and the third buffer 171 holding the restored signal value.
And a signal calculation unit 172 that calculates a signal value going back one time.

In this embodiment, the signal has four values (0, 1, X,
Z). It is assumed that one signal is represented by one byte. That is, the signal values 0, 1, X, and Z are “00000000”, “00000001”, “00000010”, and “0000”, respectively.
0011 ". For simplicity, signal values are written as 0, 1, X, and Z. In the following, 16 signal values from A to P correspond to simulation cycle 0. In the case where these signals take values as shown in FIG. 2 from FIG.

These signals are represented in the above byte representation,
It is represented as These 16 signals are represented by 4 words. Here, when a trace is collected by a conventional method of storing a signal identifier and a signal value as a pair for a signal whose value has changed as shown in Japanese Patent No. 1665055, the trace information is stored in the trace information storage unit 16. The trace result is as shown in FIG. In the simulation cycle 0, all signal values are stored. For example, in the simulation cycle 1, the signals E, which have changed from 0 to 1,
J information is stored.

In this embodiment, the XOR value of the current value of the signal at each time and the signal value at the previous time is used for collecting trace information. FIG. 5 shows an XOR for the signal of FIG.
Indicates a value.

The processing flow of the trace processing in this embodiment will be described with reference to FIG. First, in a simulation start cycle, a simulation cycle i is set to 0 and a signal value “0001000100010100” is written to the buffer 13 and the trace information storage unit 16 in step S61. Next, in step S62, the simulation cycle i is 1
Proceed to. In steps S63 and S64, the signal value “00011001010101” in the simulation cycle 1 is stored in the buffer 14.
Next, in step S66, the comparison unit 151 compares the signal values held in the buffers 13 and 14 and enters the XOR value “0000100001000000” in S ′. 'Is 0
Therefore, the answer is NO, and the process proceeds to step S68, where S ′
Only the signal value corresponding to the word that has changed in is stored. Specifically, the offset in the buffer and the contents of the XOR of the word are output to the trace information storage unit 16.
That is, as shown in FIG. 7, the data is output in a format in which an integer of one word indicating the offset in the buffer of the changed word and the XOR value of the part of the word are set. In the case of the simulation cycle 1, since there is a change in the first word and the second word, the XOR value of the first and first words, 2, 2
It outputs in the order of the XOR value of the word. That is, 00000000000000000000000000000001 00000001000000000000000000000000 00000000000000000000000000000010 00000000000000010000000000000000. In the following description, the offset portion is represented by a decimal number, and the word XOR value portion is represented by the four values of 0, 1, X, and Z described above, such as “1 1000 2 0100”. The display of the trace output result shown in FIG. 8 is also based on this expression. In the subsequent simulation cycle, the processing from step S62 to step S68 is similarly performed. Here, as in the trace simulation cycle 3 as shown in FIG. 8, when there is no change in the value from the previous cycle, the XOR value is 0 in step S66, so that the result in step S67 is YES, and there is no trace information. Do not output.

Here, it is assumed that the simulation execution is stopped in the simulation cycle 4 and debugging is attempted based on the signal value in the immediately preceding cycle 3. Although the signals of I and P are updated in the simulation cycle 4,
In order to obtain the value of the signal P in the cycle 3 from the signal value and the trace information in the cycle 4, in the above-described conventional method, the signal P must be traced back to the last cycle 0 in which the signal P was updated before the cycle 4. . That is, in order to obtain the signal value of the immediately preceding cycle, not only the signal value and the trace information at the present time but also the signal value and the trace information of the cycle earlier than the cycle to be obtained are required.

On the other hand, in this method, when the simulation is stopped, the value Z of the signal P in the simulation cycle 4 stored in the trace control unit 12 is stored in the buffer 171 of the signal value restoration unit 17, and then the signal value calculation unit 172. The contents Z of the buffer 171 and the simulation cycle 4
The value 0 of the signal P in the simulation cycle 3 can be immediately obtained by calculating the XOR of the content Z of the XOR with the previous time of the signal P extracted from the trace information “2 X000 3 000Z” in the above.

That is, in this method, since the XOR value of the signal value at the previous time and the signal value at the current time is held as trace information,
When the simulation cycle goes back one time, first, it is determined whether or not the trace information of the signal of interest is output to the trace information storage unit 16. If the trace information storage unit 16 has the output, it is held in the buffer 171. The XOR of the current time value and the trace information stored in the trace information storage unit 16 is calculated by the signal value calculation unit 172. If there is no output in the trace information storage unit 16, the current value held in the buffer 171 is stored. If the signal value at the time is used as it is as the signal value at the previous time, the signal value at the previous time can be immediately extracted. Further, after the obtained signal value at the previous time is written back to the buffer 171, the above processing is repeated, whereby it is possible to sequentially go back to the previous value one time at a time.

Further, in the present system, since only the word at which the signal value at the current time and the value immediately before it change are used as trace information, it can be expected that the trace information will be less than in the conventional method. When such a signal is concentrated in a specific word, the effect is expected to be prominent.

In this embodiment, the trace is collected every hour, but the trace can be collected only every N times. For example, if the simulation cycle is 1 ns and the logic circuit of a clock cycle of 100 ns wants to know the signal value only when the clock changes, N
= 50. This means that the trace control unit 12
This can be easily realized by changing the output to the buffer for each time. In this case, the trace amount is 1 / N
become.

In this embodiment, trace collection is started from the simulation start cycle 0.
It is also possible to start the trace collection in the middle of the simulation. This can also be easily realized by changing the trace control unit 12.

In this manner, the reduction in the simulation speed can be further suppressed. (Modification 1 of the First Embodiment (Part 1)) The trace information output unit 15 in FIG. 1 uses, as information to be output to the trace information storage unit 16, an offset (an integer of one word) in a buffer after the simulation cycle 1. And the XO of that word
Instead of outputting the contents of R, the offset in the buffer (an integer of one word), the number of words (an integer of one word), and the XOR contents (32 bits × word) for the number of words in the format shown in FIG. (A bit string of several minutes) is output.

When the signal of FIG. 2 is to be traced, the output to the trace information storage section 16 is as shown in FIG. In the case of the simulation cycle 1, since there is a change of two words from the first word to the second word,
The number of words corresponding to the change (2), the XOR value of the first word, and the XOR value of the second word are output in this order. That is, 00000000000000000000000000000001 00000000000000000000000000000010 00000001000000000000000000000000 00000000000000010000000000000000 is output. In the following, the offset and the number of words are represented by a decimal number, and the XOR value of the word is represented by the four values of 0, 1, X, and Z described above, such as "1 2 1000 0100". The display of the trace output result in FIG. 10 is also based on this expression. When there is no change in the value from the previous cycle as in the simulation cycle 3, nothing is output as trace information as in the first embodiment.

In the present system, when signals whose values have changed are concentrated in continuous words, the effect of reducing trace information is considered to be significant. (Modification of First Embodiment (No. 2)) The trace information output unit 15 in FIG. 1 uses, as information to be output to the trace information storage unit 16, an offset (an integer of one word) in the buffer after the simulation cycle 1. And the XO of that word
Instead of outputting the contents of R, a bitmap (4 bits) indicating which word in the buffer has changed in the format shown in FIG. 11 and the contents of the XOR of the changed word (32 bits) are output. .

When the signal shown in FIG. 2 is to be traced, the output to the trace information storage section 16 is as shown in FIG. In simulation cycle 1, the first word and the second word
Since there is a change in the word, the bit map, the XOR value of the first word, and the XOR value of the second and second words are output in this order. The bit map is a 4-bit “0110” with “1” written in the upper first bit and the upper 2 bits.
0110 00000001000000000000000
000000000 00000000000000010000000000000000 is output. In the following, the bitmap portion is represented by a binary number, such as “0110 1000 0100”, and the word XOR value portion is represented by the four values of 0, 1, X, and Z described above.

The display of the trace output result in FIG. 12 is also based on this expression. When there is no change in the value from the previous cycle as in the simulation cycle 3, nothing is output as trace information as in the first embodiment.

In this method, the number of bits for designating the word whose value has changed is only required to be equal to the number of signal values, so that generally less trace information can be expected than in the above three methods.

In the description of this method, the bitmap is
Although the changed word is made to correspond to the bit from the high order, the changed word may be made to correspond to the bit from the low order.

(Modification of First Embodiment (Part 3)) FIG.
The trace information output unit 15 of the
Instead of outputting the offset (an integer of one word) in the buffer and the contents of the XOR of the word after the simulation cycle 1 as the information to be output, the identifier (character string) of the signal changed in the format shown in FIG. ) And the content of XOR of the signal (bit string).

When the signal of FIG. 2 is to be traced, the output to the trace information storage unit 16 is as shown in FIG. In simulation cycle 1, signal E and signal J
, The XOR value of E, E, the XOR of J, J
Output in order of value. That is, E 00000001 and J 00000001 are output to the trace information storage unit 16. In the following, the XOR value portion of the signal, such as "E1 J1", is represented by the four values of 0, 1, X, and Z described above (the identifier is represented by a character string as it is). The display of the trace output result in FIG. 14 is also based on this expression. As in simulation cycle 3, when there is no change in the value from the previous cycle,
Nothing is output as trace information as in the first embodiment.

In this method, the amount of trace information is
Although this is not different from the conventional method, it is a method that can immediately obtain the immediately preceding value, which is usually impossible in the conventional method.
Further, compared with the above four methods, since there is no trace information in word units, if the number of signals whose values change is extremely small, the four methods (conventional method, the first embodiment and its modifications ( It can be expected that the trace information is further reduced as compared to 1) and 2).

(Modification of First Embodiment (Part 4)) In the present system, the configuration of the trace information output unit 15 in FIG. 1 is such that the comparison unit 151 and the determination unit 152 determine the number of signals having the same XOR content. FIG. 15 with a counter 153 for counting
Is replaced by

The trace information output unit 15 shown in FIG. 15 outputs, as information to be output to the trace information storage unit 16, the offset in the buffer and the contents of the XOR of the word after the simulation cycle 1, instead of the contents shown in FIG. XOR that the signal to be traced can take in such a format
It outputs a value (bit string), the number of signals whose XOR content is equal to the value (an integer of one word), and an identifier (character string) of the signal.

The output to the trace information storage unit 16 when the signal in FIG. 2 is to be traced is as shown in FIG. In simulation cycle 1, signal E and signal J
, And their XOR values are both bit strings “00000001”, so that XOR values, 2, E, and J are output in that order. That is, 00000001 00000000000000000000000000000010 EJ is output to the trace information storage unit 16. In the following, the XOR value part of the signal is the four values of 0, 1, X, and Z described above and the signal number part is 10 like “1 2 EJ”.
Expressed as a base number (identifiers are expressed as strings as they are).

The display of the trace output result in FIG. 17 is also based on this expression. When there is no change in the value from the previous cycle as in the simulation cycle 3, nothing is output as trace information as in the first embodiment.

In this method, when a large number of the same difference values are included at the same time, the above five methods (conventional method,
It can be expected that the trace information is further reduced as compared with the first embodiment and its modifications (Nos. 1 to 3).

(Second Embodiment) Next, a second embodiment of the present invention will be described. (Main Configuration and Operation of the Second Embodiment) The logic simulation apparatus according to the present embodiment includes a simulation time when at least one signal value changes, and a signal before the change at each signal whose value changes at the simulation time. A trace result output means for outputting a difference between the signal value after the change and the signal value after the change as a trace result, and means for restoring the immediately preceding signal value from the signal value at a specific time using the difference. The difference here is a remainder obtained by subtracting the immediately preceding value from the latest value of the signal and dividing the result by the signal value range.

According to this embodiment, at the time when the simulation has proceeded to a certain simulation time, the immediately preceding value of the signal is restored using the XOR of the signal value output by the trace result output means and the signal value at that time. Becomes possible.

Further, by changing the trace output format, it is possible to reduce the amount of trace output and reduce the reduction in simulation execution speed. (Effect of the Second Embodiment) In the conventional trace collection method,
Although the identification value of the signal whose value has changed and the signal value are output as a pair, there is a disadvantage that when the simulation execution is interrupted and the signal value at the previous time is desired to be observed, the value cannot be obtained immediately. Was. In the present embodiment, by using the remainder at each simulation time as trace information, it is possible to calculate a signal value retrospectively.

(Specific Description of the Second Embodiment) FIG.
FIG. 2 is a diagram illustrating a schematic configuration of a logic simulation apparatus according to the embodiment. This embodiment is different from the first embodiment in that the signal value of the current simulation cycle is compared with the signal value of the previous simulation cycle to obtain difference information.

The simulation execution unit 181 shown in FIG.
The first buffer 183, the second buffer 184, and the trace information storage unit 186 are respectively the simulation execution unit 11, the first buffer 13, and the second buffer 1 of FIG.
4. Same as the trace information storage unit 16.

The trace information output unit 185 calculates a difference between the signal values held by the first buffer 183 and the second buffer 184 and calculates a remainder obtained by dividing the difference by a signal value range. A determination unit 1852 for determining whether or not the value calculated in 1851 is 0.

The signal value restoring section 187 has a third buffer 1871 for holding the restored signal value at the time closest to the simulation cycle 0 at the time of restoration execution, and a signal value calculating section 1872 for calculating the signal value one time earlier. And a table storage unit 1873 that stores a table referred to by the signal value calculation unit 1872.

In this embodiment, a value represented by the following equation (1) is calculated from the signal value St at time t of the signal S and the signal value St-1 at the previous time, and the calculated value is used to collect trace information. Used for

(St−St−1) mod Rs (1) where Rs is a signal value range of the signal S. In this embodiment, Rs = 4 because a quaternary signal is used. FIG. 19 shows values obtained by Expression (1) for the signal values 0, 1, X, and Z. In the present embodiment, the table storage unit 187
3 stores the table shown in FIG.

In this embodiment, the signal to be traced is the first signal.
As in the case of the first embodiment, the 16 signals shown in FIG. FIG.
0 represents the calculation result of the equation (1) for the signal of FIG.

The processing flow of this embodiment follows FIG. 6, as in the first embodiment. In step S61, the simulation cycle i is set to 0, and the information to be output to the trace information storage unit 186 at the start cycle 0 of the simulation is the same as that of the first embodiment.
Sequence of 16 signal values from A to P at “0001000100010100”
(The value of each signal is represented by using 0, 1, X, and Z; the notation of the signal value sequence is the same hereinafter.)
Is the same.

Next, the simulation cycle i is set to 1 in step S62, and in the cycle 1 in steps S63 and S64, the signal value sequence "00" is stored in the buffer 184.
01100101010100 "is stored. In step S66, the calculation of the expression (1) is performed in the comparing unit 1851. In the case of the simulation cycle 1," 00001000 "
01000000 ". Here, in step S67, N
Since the result is O, the process proceeds to step S68, and only the signal value corresponding to the changed word is stored. Specifically, the offset (integer) in the buffer and the expression (1) of the word
Is output to the trace information storage unit 186.

That is, as shown in FIG. 21, an integer of one word representing the offset in the buffer of the changed word and the calculation result of the expression (1) of the word in that part are output as a set. In the case of the simulation cycle 1, there is a change in the first word and the second word.
As a result of expression (1) of the word, expression (1) of the second and second words
Output in the order of That is, 00000000000000000000000000000001 00000001000000000000000000000000 00000000000000000000000000000010 00000000000000010000000000000000. In the following, the offset part uses a decimal number, and the result part of the word equation (1) uses four values of 0, 1, X, and Z described above, such as "1 1000 2 0100". Expressed in hexadecimal. The display of the trace output result shown in FIG. 22 is also based on this expression. In the subsequent simulation cycle, the processing from step S62 to step S68 is similarly performed. Here, as in the trace simulation cycle 3 as shown in FIG. 22, when there is no change in the value from the previous cycle, since the result of the equation (1) is 0 in step S66, the result is YES in step S67, and the trace information Does not output anything.

In this method, the signal value one time before the time of interest can be obtained as follows. For example, the simulation execution is stopped in the simulation cycle 4 and the signal I in the immediately preceding simulation cycle 3 is stopped.
Consider the case of finding the value of First, the trace information storage unit 1
It is determined whether there is an output to the signal 86 or not, and if there is an output in the trace information storage unit 186, the signal value calculation unit 1872 refers to the table storage unit 1873 that stores the table of FIG. The item of x corresponding to the portion of the latest value in the table is equal to the latest value, and the item of (xy) mod 4 corresponding to the portion of Expression (1) is output to the trace information storage unit 186. When an entry equal to the value of the expression (1) is found, the value of y of the entry is set as the immediately preceding value, and when there is no output in the trace information storage unit 186, the signal value of the current time held in the buffer 1871 is used as it is. The immediately preceding value can be obtained immediately by setting the signal value at the time.

In this case, using the value 1 of the signal I in the simulation cycle 4 and the output value X to the trace information storage unit 186, the item x in the table of FIG. Equal to one,
In addition, an entry in which the item of (xy) mod 4 is equal to the output value X to the trace information storage unit 186 is found, and the value of the signal I in the simulation cycle 3 can be immediately obtained from y = Z.

Note that it is easy to perform trace collection only at every N times as in the first embodiment, or to change the trace control unit 182 so as to start trace collection in the middle of a simulation. By doing so, the decrease in the simulation speed can be further suppressed.

(Modification of the Second Embodiment (Part 1))
In the third embodiment, the trace information output format is modified in the same manner as the first modification of the first embodiment.

(Modification of Second Embodiment (Part 2))
In the third embodiment, the trace information output format is modified in the same manner as the modification (part 2) of the first embodiment.

(Modification of Second Embodiment (Part 3))
In the third embodiment, the trace information output format is modified in the same manner as the modification (part 3) of the first embodiment.

(Modification of the Second Embodiment (Part 4))
In the embodiment, the trace information output format is modified in the same manner as the modification (part 4) of the first embodiment. Further, the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the scope of the invention.

[0070]

As described above, according to the present invention, in the trace collection at the time of the logic simulation, the difference value of the signal value at each simulation time is trace-collected, so that the logic value is calculated from the signal value at a specific time. This makes it easier to debug the circuit.

Further, by changing the method of designating which of the signals to be traced has changed during trace collection, the amount of trace can be further reduced as compared with the conventional method. Can be performed at high speed, and the simulation can be performed at higher speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a signal to be traced;

FIG. 3 shows a byte representation of the signal values of FIG. 2;

FIG. 4 is a diagram showing trace information for the signal values of FIG. 2 according to a conventional method.

FIG. 5 is a diagram showing an XOR value of a signal value of FIG. 2 with a previous cycle.

FIG. 6 is a flowchart showing a flow of processing for outputting trace information;

FIG. 7 is a diagram showing a trace output format according to the first embodiment;

FIG. 8 is a diagram showing trace information for the signal values of FIG. 2 based on the first embodiment.

FIG. 9 is a diagram showing a trace output format in a modification (part 1) of the first embodiment;

FIG. 10 is a diagram showing trace information with respect to the signal values of FIG. 2 based on a modification (No. 1);

FIG. 11 is a diagram showing a trace output format in a modified example (part 2) of the first embodiment;

FIG. 12 is a diagram showing trace information for the signal values of FIG. 2 based on a modification (No. 2);

FIG. 13 is a diagram showing a trace output format in a modified example (part 3) of the first embodiment;

FIG. 14 is a diagram showing trace information for the signal values of FIG. 2 based on a modification (No. 3);

FIG. 15 is a block diagram showing a configuration of a trace information output unit according to a modification (part 4) of the first embodiment;

FIG. 16 is a diagram showing a trace output format in a modified example (4).

FIG. 17 is a diagram showing trace information for the signal values in FIG. 2 based on a modification (No. 4);

FIG. 18 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 19 is a diagram illustrating a combination of difference values output to a trace information storage unit corresponding to possible signal values in the second embodiment.

20 is a diagram showing a difference value between a signal at a previous time and a signal calculated in a comparison unit of the trace information output unit in FIG. 18 in the second embodiment.

FIG. 21 is a diagram showing a trace output format in the second embodiment.

FIG. 22 is a diagram showing trace information for the signal values of FIG. 2 based on the second embodiment.

[Explanation of symbols]

11, 181: simulation execution unit, 12, 182
... Trace control unit, 13, 14, 183, 184. Buffer, 15, 185. Trace information output unit, 151, 1
851 comparison section, 152, 1852 determination section, 153
Counter, 16, 186... Trace information storage unit, 17,
187: signal value restoring unit; 171, 1871: buffer;
172, 1872: signal calculation unit, 1873: table storage unit

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Shozo Isobe 1 Toshiba, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture (56) References JP-A-59-154374 (JP, A) JP-A-4-293167 (JP, A) JP-A-5-151305 (JP, A) JP-A-6-68192 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 17/50 JICST file (JOIS)

Claims (2)

(57) [Claims] A first buffer for temporarily storing a first signal value;
And a second buffer for temporarily storing a second signal value
Means from said first and second buffer means.
Comparing means for comparing first and second signal values;
Trace information is obtained from the output result of the stage, and the trace information is obtained.
Information storing means, and a specific simulation time
From the third buffer means for temporarily storing the signal value at
Of the immediately preceding signal based on the signal value of
And a restoring means for restoring the logic value, and the logic circuit is described.
Based on the information, a logic simulation can be performed
Logic that executes repeatedly while moving forward by unit time
A simulation method, wherein at least a simulation is performed based on an output result of the comparing means.
Simulation results consisting of the
And outputting a simulation result obtained in the step
In other words, at least one signal value is
If it changes from the value in the result,
Corresponding to the simulation time in the
Information specifying the changed signal and the changed signal
The difference information between the signal value before the change and the signal value at the current time is stored in the
A step of storing the information as race information in the storage means, and specifying the information based on the trace information stored in the step.
From the signal value at the simulation time
The signal value at the time of
Logic stains comprising the steps of:
Method. 2. A first buffer for temporarily storing a first signal value.
And a second buffer for temporarily storing a second signal value
Means from said first and second buffer means.
Calculate the remainder obtained by dividing the difference between the first and second signal values by the signal value range
And a comparison means for comparing
Find trace information and store the trace information
Means and the signal value at a particular simulation time
Third buffer means for temporarily storing the first signal value;
Yes a table memorize the differential information of the second signal value
And refer to the table based on the trace information.
From the signal value at the specific simulation time
Restoration means for restoring to the immediately preceding signal value,
Based on the described information, perform a logic simulation
Repeated execution while proceeding by simulation unit time
A logic simulation method based on an output result of the comparing means.
Simulation results consisting of the
And outputting a simulation result obtained in the step
In other words, at least one signal value is
If it changes from the value in the result,
Corresponding to the simulation time in the
Information specifying the changed signal and the changed signal
The difference between the signal value before the change and the signal value at the current time in the signal value range
The difference information obtained from the divided remainder and the trace information
Wherein the step of storing in the storage means, the table from the trace information stored in the step as
File at the specified simulation time
From the signal value at the previous simulation time
Restoring by restoring means.
A featured logic simulation method.