JP2806459B2 - A logic simulation device that can evaluate flip-flops - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

In recent years, the importance of a logic simulation system has been recognized in the design of logic circuit devices such as computers with the improvement of development quality and shortening of the design period. Is desired. For this reason, various methods have been devised, but a flip-flop, a latch, and a memory (RA) are included in basic logic elements such as AND / OR used as basic design units in the past.
Although a logic element having an internal state (hereinafter referred to as an FF circuit) such as an M or a ROM is used as a basic logic element in the design of a logic circuit, the evaluation of the FF circuit is performed by a special process in the simulation. At present.

[0002] The present invention relates to a logic simulation apparatus capable of simulating the operation of a circuit having the above-described FF in a logic circuit simulation and capable of evaluating a flip-flop.

[0003]

2. Description of the Related Art In a simulation of a logic element,
The target logical element is a normal logical element (for example, such a logical element such as an AND / OR element or the like) for which one type of output value is always determined when an input to the logical element is determined. ), And an FF circuit in which not only the value of the input of the logic element but also the value of the internal state of the logic element must be considered.

Conventionally, the following method has been used to evaluate the above FF circuit. Evaluation of FF circuits using a logic simulation device for evaluating normal logic elements. Generally, an FF circuit can be represented by a combination of normal logic elements having feedback. Therefore, if the FF circuit is expanded to a basic logic element composed of a normal logic element as described above,
It can be evaluated by a logic simulation device for evaluating a normal logic element.

FIG. 4 is a diagram showing a conventional logic simulation apparatus for evaluating the above-described ordinary logic elements (eg, AND / OR elements). In FIG.
12, 314, 315, and 317 are registers; a register 311 is a register that holds an attribute of a logical element; a register 312 is a register that holds an external input to the logical element; a register 314 is a register that holds a logical operation result value; A register 315 for holding a value before evaluation;
The register 317 is a register for holding the evaluation result.
Reference numeral 313 is an arithmetic mechanism, and 316 is an evaluation mechanism.

In FIG. 1, when evaluating a normal logic element, an attribute (eg, an AND element, a 0R element, etc.) of the logic element is input from a register 311 to an operation mechanism 313, and an external input (eg, an AND element) is input from a register 312. ,
"1", "0", etc.). The arithmetic mechanism 313 includes:
For example, a logical operation result is obtained by a truth table, wired logic, software, or the like, based on the attribute of the logic element provided from the register 311 and the external input value provided from the register 312.

[0007] The logical operation result calculated by the operation mechanism 313 is held in the register 314, and is compared in the evaluation mechanism 316 with the value before evaluation held in the register 315. If the logical operation result held in the register 314 is different from the value before evaluation held in the register 315, the evaluation mechanism 316 stores the event data in the register 31.
7 and the result of the logical operation is stored in the register 315 as a value before the next evaluation of this logical element.
Is held.

If the result of the logical operation held in the register 314 is the same as the value before evaluation held in the register 315, no event data is output, and the values of the registers 315 and 317 are changed to the previous values. Hold the value. When an FF circuit is evaluated using the logic simulation apparatus of FIG. 4, for example, R as shown in FIG.
The S type FF circuit has a NAN as shown in FIG.
Since it can be expressed using the D element, FIG.
The FF circuit can be evaluated by evaluating the logic circuit composed of the NAND elements shown in FIG. 1 using the logic simulation apparatus shown in FIG. Evaluation of an FF circuit by a simulation apparatus provided with a dedicated arithmetic mechanism for evaluating an FF circuit in addition to an arithmetic mechanism for evaluating a normal logic element.

FIG. 6 is a diagram showing an example of a logic simulation apparatus provided with an operation mechanism dedicated to the FF circuit for evaluating the FF circuit. In FIG. 6, 411, 412, 414, 4
15, 417, 418, and 420 are registers; a register 411 is a register for holding an attribute of a logical element; a register 412 is a register for holding an external input to the logical element; a register 414 is a register for holding a logical operation result value; A register 415 holds a value before the evaluation,
A register 417 is a register for holding an evaluation result, a register 418 is a register for holding an internal state value, and a register 4
Reference numeral 20 denotes a register for holding a logical operation result of the FF circuit; 413, an operation mechanism; 416, an evaluation mechanism;
Reference numeral 9 denotes an operation mechanism dedicated to the FF circuit, and reference numeral 421 denotes a selector.

In FIG. 1, a register 411 for holding an attribute of a logic element, a register 412 for holding an external input to the logic element, an operation mechanism 413, a register 414 for holding a logical operation result value, and a value before evaluation are held. Register 41
5, evaluation mechanism 416, register 41 for holding the evaluation result
7 is the same as that of the simulation apparatus shown in FIG. 4. In this example, in addition to the simulation apparatus shown in FIG.
8, an operation mechanism 419 for exclusive use of the FF circuit, a register 420 for holding a logical operation result of the FF element, and a selector 421 are added.

In FIG. 6, the fact that the logical element attribute to be evaluated is an FF element is input from a register 411,
When an external input value to the FF circuit is input from the register 412, the dedicated FF circuit operation mechanism 419 reads the internal state value of the FF circuit from the memory 418 that stores the internal state value of the FF circuit. Next, the FF circuit-dedicated operation mechanism 419 includes, for example, a truth table, wired logic,
Based on the internal state value stored in the memory 418 and the external input value provided from the register 312, a logical operation result is obtained by software or the like, and the logical operation result is provided to the register 420.

When the attribute of the logic element is the FF circuit, the selector 421 is switched to the register 420 side.
The logical operation result held in the register 420 is
21 to the evaluator 416 and the memory 415
This is compared with the value before the evaluation read out. If the value before the evaluation is different from the logical operation result, the event data is output to the register 417 and the logical operation result is stored in the memory 415.

[0013]

In the above-described conventional FF circuit evaluation method, the evaluation method described in (1) requires that a logic circuit to be simulated be expressed only by ordinary logic elements for simulation. Therefore, a special simulation model needs to be created, and the number of logic elements to be evaluated increases, which hinders the speeding up of the simulation.

In the evaluation method described above, it is not necessary to expand the FF circuit into normal logic elements, and a simulation model can be created without increasing the number of logic elements of a logic circuit to be simulated. In addition to a logical operation mechanism for evaluating a normal logic element, a special logical operation mechanism dedicated to FF circuit evaluation needs to be incorporated in the simulation device.

In addition, the special logic operation mechanism dedicated to the evaluation of the FF circuit requires a mechanism for storing the internal state separately, and controls / uses not only the input of the FF circuit but also the value of the held internal state. FF circuit has a mechanism to perform logical operation, so the simulation device becomes huge,
This can be complicated. SUMMARY OF THE INVENTION The present invention has been made to improve the above-described disadvantages of the related art.
Provided is a logic simulation device capable of realizing a circuit operation mechanism with a device similar to a normal logic element evaluation mechanism, having a simple configuration, and capable of evaluating a flip-flop capable of performing high-speed simulation. The purpose is to:

[0016]

FIGS. 1 (a) and 1 (b) are diagrams showing the principle of the present invention. FIG. 1 (a) is a basic configuration diagram, and FIG. 1 (b) is a diagram showing the same principle. FIG. 6 is a diagram showing a mode of division of a register 5 for holding a logical value before evaluation in FIG. In order to solve the above-mentioned problem, the present invention is configured as shown in FIG. 1 (a), and comprises an operation mechanism 3 for obtaining a logical operation result 4 based on an attribute 1 of a logical element and an external input value 2; Register 5 that holds the logical value of the target logical element before evaluation
And an evaluation mechanism 6 for comparing the logical operation result 4 obtained by the operation mechanism 3 with the logical value before evaluation held in the register 5
The evaluation unit 6 compares the logical operation result 4 obtained by the operation unit 3 with the logical value before evaluation held in the register 5, and outputs event data if they do not match. When evaluating a logic element having an internal state, such as a flip-flop, a latch, or a memory, the n-bit of the register 5 that holds the logic value before the evaluation of the logic element is evaluated in FIG.
As shown in (b), k bits and m bits (n ≧ k + m)
Divided into two, one of which holds an internal state value of a logic element having an internal state, and the other of which holds a logic value before evaluation of a logic element to be evaluated,
The internal state value held in the register 5 is input to the operation mechanism 3 as an external input signal.

[0017]

When the attribute 1 of the logic element and the external input value 2 are given to the arithmetic unit 3, the arithmetic unit 3 sets the k representing the internal state value of the FF circuit among the n-bit data held in the register 5. Alternatively, m bits are read, a logical operation is performed based on the read internal state value, the attribute 1 of the logical element, and the external input value 2, and a logical operation result 4 is output.

On the other hand, of the n-bit data stored in the register 5, m or k, which are values before the evaluation of the FF circuit,
The bit data is read from the register 5 and compared with the logical operation result 4 in the evaluation mechanism 6. If the logical operation result 4 is different from the pre-evaluation value held in the register 5, the evaluation mechanism 6 outputs the event data, and evaluates the logical operation result 4 and then this logical element. The value is stored in the register 5 as the value before the evaluation.

[0019]

FIG. 2 is a diagram showing an embodiment of the present invention. In FIG. 2, reference numerals 21, 22, 24 and 27 are registers, a register 21 is a register for holding the attribute of a logical element, and a register 22 is a register. A register holding an external input to the logic element, a register 24 is a register holding a logical operation result value, a register 25 is a register holding a value before evaluation and an internal state value in evaluation of the FF circuit, and a register 27.
Is a register for holding the evaluation result, 23 is an operation mechanism, 23a is a preprocessing / address generation mechanism, 23b is a memory storing a truth table, and 26 is an evaluation mechanism.

In FIG. 1, a register 21 for storing the attribute of a logic element is a 25-bit register.
22 bits represent the attribute of the logic element, and the remaining 2 bits are used as parity. The register 22 for holding the external input is an 18-bit register, and one bit of one external input signal is represented by four bits, and four external input signals are held in all. That is, 16 bits are used for the external input signal, and the remaining 2 bits are used as parity.

In order to represent one external input signal,
It requires four states “0”, “1”, “X”, and “Z” and a total of eight strengths, that is, four bits. Here, “X” represents unknown, and “Z” represents a high impedance state. The pre-processing / address generation mechanism 23a in the arithmetic mechanism 23 performs pre-processing such as inversion processing of input data, rearrangement of data, and the like, and attribute information of the logic element held in the register 21 and external input information held in the register 22. This is a means for generating an address of the truth table 23b based on the above, and the truth table 23b stores, for each logic element, an internal state value and a logical operation result with respect to an external input signal.

The register 25 for holding the value before the evaluation is a 4-bit register. In a logical operation of a normal logic element, as described above, "0", "1", "X",
There are four states of "Z" and eight states in total, that is,
The value before the evaluation is held by using 4 bits, and in the case of the logical operation of the FF circuit, the value before the evaluation is held by 2 bits of the 4 bits without holding the strength signal ("" 0 ",
Only the states of "1", "X", and "Z" are held), and the remaining two bits hold the internal state of the FF circuit.

FIG. 3 shows a register 25 for holding a value before evaluation.
FIG. 3 is a diagram showing a mode of data division in FIG. 3. As shown in FIG. 4, the register 25 is a 4-bit register, and when a normal logic element is evaluated, FIG.
As shown in FIG. 7, one signal is represented by four bits, and F
When evaluating the F circuit, as shown in FIG.
The value before evaluation is held in part A, and the internal state of the FF circuit is held in part B.

That is, since a signal indicating the strength of an external input signal is not normally required in an FF circuit, two bits out of four bits are required as a value before evaluation in a register 25 for holding a value before evaluation. However, in this embodiment, the internal state of the FF circuit is held using these two bits. The evaluation mechanism 26 is a means for comparing the value before evaluation held in the register 25 with the result of the logical operation held in the register 24, as described with reference to FIGS. If the values are different, the event data is output to the register 27, and the value of the register 25 holding the value before the evaluation is updated with the result of the logical operation.

Next, the operation of the embodiment shown in FIG. 2 will be described. When evaluating a normal logic element, the arithmetic mechanism 23 is provided with the attribute of the logic element from the register 21 storing the attribute of the logic element, and is supplied with up to four external input signals from the register 22 holding the external input. And the preprocessing / address generation mechanism 23a in the arithmetic mechanism 23 rearranges the order of the external input signal, performs preprocessing such as signal inversion processing, and then performs a truth value based on the attribute information of the logic element and the external input signal. Generate the address in Table 23b.

As described above, the truth table 23b stores, for each logic element, a logical operation result with respect to an internal state value and an external input signal. When an address corresponding to information and an external input signal is input, a 4-bit logical operation result corresponding to the address is output. The logical operation result obtained from the truth table 23b is held in the register 24 and compared with the value before evaluation held in the register 25 in the evaluation mechanism 26, as described in the conventional example.

If the result of the logical operation held in the register 24 is different from the value before evaluation held in the register 25, the evaluation mechanism 26 stores the event data in the register 27.
And the result of the logical operation is held in the register 25 as a value before the next evaluation of the logical element. In addition, by the simulation device of FIG.
When the FF circuit is evaluated, when the attribute of the logic element (the attribute in the case of the FF circuit) and the external input signal are given to the arithmetic unit 23, the preprocessing /
The address generation mechanism 23a rearranges the order of the external input signal and performs preprocessing such as signal inversion.

Next, the preprocessing / address generation mechanism 23a
Reads out 2 bits of the internal state value of the FF circuit from the 4-bit data held in the register 25, and reads the read internal state value and the attribute of the logical element held in the registers 21 and 22. The address of the truth table 23b is generated based on the information and the external input signal. As described above, since the truth table 23b stores the logical operation result for the internal state value and the external input signal for each logic element, when an address is input from the preprocessing / address generation mechanism 23a, The logical operation result corresponding to the address is output, and the logical operation result is held in the register 24.

On the other hand, of the 4-bit data stored in the register 25, 2-bit data, which is the value before the evaluation of the FF circuit, is read out from the register 25 and held in the register 24 in the evaluation mechanism 26. This is compared with the result of the logical operation. When the result of the logical operation held in the register 24 is different from the value before the evaluation held in the register 25 as in the case of the evaluation of the normal logic element, the evaluation mechanism 26 sends the event data to the register 27. In addition to the output, the result of the logical operation is held in the register 25 as a value before the next evaluation of the logical element.

As described above, in this embodiment, the FF
When evaluating a circuit, the result of the logical operation of the FF circuit should be 2
A 4-bit register 25 that represents the internal state of the FF circuit with 2 bits and stores the value before evaluation.
Are used to hold the internal state value when evaluating the FF circuit, and when performing the logical operation of the FF circuit, the two-bit internal state value of the data held in the register 25 is separated and calculated. Since the configuration is such that the input is given to the mechanism 23 as an external input, the FF circuit is developed into a normal logic element for evaluation, and without providing an arithmetic mechanism dedicated to the FF circuit,
The evaluation of the FF circuit can be performed.

In the above embodiment, the register 21 for storing the attribute of the logic element is a 25-bit register,
An 18-bit register is used as the register 22 for holding the external input.
Although an example in which the internal state value of the circuit is represented by 2 bits has been described, the present invention is not limited to the above-described embodiment, and may have an arbitrary number of bits as needed.

Further, in the above-described embodiment, an example in which a truth table is used as means for obtaining a logical operation result has been described. However, the present invention is not limited to the above-described embodiment, and a wired logic The result of the logical operation can be obtained by software or the like.

[0033]

As is apparent from the above description,
In the present invention, the register holding the value before the evaluation is 2
Since the internal state value in the FF circuit is held in one of them and the above-mentioned internal state value is input to the operation mechanism in the evaluation of the FF circuit and the logical operation is performed, the following effects can be obtained. Can be. In simulating the FF circuit, the simulation apparatus can be configured without having a calculation mechanism dedicated to the FF circuit or a mechanism such as a memory that holds only the internal state value of the FF circuit in the simulation apparatus, thereby simplifying the configuration of the apparatus. And its reliability can be improved. Since it is not necessary to expand the FF circuit in the circuit to be simulated into a normal logic element, the simulation can be performed without increasing the number of simulated logic elements, and the simulation can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing a mode of division of a register holding a logical value before evaluation.

FIG. 4 is a diagram showing a first conventional example.

FIG. 5 is a diagram showing an example in which an FF circuit is developed into a normal logic element.

FIG. 6 is a diagram showing a second conventional example.

[Explanation of symbols]

5, 21, 22, 24, 27 Register 3, 23 Arithmetic unit 23a Preprocessing / address generation unit 23b Memory storing truth table 6,26 Evaluation unit

Claims (1)

(57) [Claims] An operation mechanism (3) for obtaining a logical operation result (4) based on an attribute (1) of a logic element and an external input value (2), and a logic element before evaluation of a logic element to be evaluated. A register (5) that holds the value, a logical operation result (4) obtained by the arithmetic mechanism (3), and a register
Evaluation mechanism that compares the logical value before evaluation stored in (5)
(6), and the logical operation result (4) obtained by the operation mechanism (3) and the register
In the logic simulator configured to compare the logic value before evaluation held in (5) with the logic value before evaluation in the evaluation mechanism (6) and to output event data when the two do not match, the flip-flop, the latch, and the memory In evaluating a logic element having an internal state such as that described above, the register (5) for holding the logic value before the evaluation of the logic element is divided into two parts, and one of them is made to hold the internal state value of the logic element having the internal state. The other one holds the logical value of the logic element to be evaluated before the evaluation, and inputs the internal state value held in the register (5) to the arithmetic mechanism (3) as an external input signal. A logic simulation device capable of evaluating a flip-flop, wherein a logic element having an internal state value is evaluated.