JP2000105780A - Logical simulation system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logical simulation system for executing a quaternary simulation at a high speed. SOLUTION: The reading processing of circuit information is performed (a step 102), and a part to which it is necessary to perform an arithmetic operation is limited by using a high impudence value Z (a step 103). In this step, a gate, whose input values are the Z value and an indefinite value X and whose output values are the same, is retrieved, and a logic for converting the input of the gate from the Z value into the X value is inserted, and ternary simulation is operated to the gate, and quaternary simulation is operated to the other gates. Afterwards, a simulation code is generated (a step 105). The quaternary simulation is expressed by using each one bit of two words, and plural patterns are made correspond to each bit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a logic simulation system, and more particularly, to a logic simulation system using four values.

[0002]

2. Description of the Related Art Logic-designed large-scale semiconductor integrated circuits (L
Conventionally, a logic simulation is performed before actually manufacturing an LSI in order to test whether the SI operates normally as designed. In this logic simulation, it is desired to be able to perform particularly high-speed arithmetic processing in the operation test and the function test of an LSI which has been increasing in density and becoming multifunctional in recent years.

[0003] Therefore, a logic simulation method has been conventionally known in which accesses to various memories for storing state changes of input / output of each gate of a logic device to be simulated are parallelized and a processing pipeline is applied. (JP-A-59-3652). In this conventional logic simulation method, a new event memory, a new status memory, a fan-out memory, and an input state in which an input state to each gate of the new status memory is stored for each gate. A dictionary address memory in which relative values determined by the attributes of the vector memory, the address memory, and the gate are stored for each gate of the new status memory, and a position determined by the contents of the input vector memory and the dictionary address memory. And a dictionary memory in which a new output state of the gate is defined. Each of the memories is configured to be accessible in parallel, and a new status memory and a fan-out based on the contents of the new event memory are provided.・ Memory is referenced and input vector memo The contents of the dictionary memory determined by the contents of the input vector memory and the corresponding dictionary address memory become new gate outputs. This is a configuration to simulate.

[0004] In particular, as a logic simulation method for simulating quaternary values, FIG.
And (B) are usually used. That is,
In the case of a simulation using only two values of 0 and 1,
For example, in the case where the circuit is dropped into assembler code,
The AND gate could be simulated by direct conversion, such as by directly converting it to an AND instruction. However, in order to perform the quaternary operation accurately, the AND gate 1
Since it is very complicated to model one, four values are usually simulated by the method shown in FIGS. 14A and 14B or the method of assembling the same.

FIG. 14A shows a method of determining a condition so that an answer is obtained as soon as possible, and obtaining an answer. FIG.
(B) shows a method in which the values representing the codes of the signals a and b are added to the base address of each operation, and the output corresponding to the input logic is obtained from a table. In the logic simulation method shown in FIG. 14B, 00, 01, 10 and 11 are used for codes 0, 1, X and Z, respectively. The number is the address, the middle is the expression when the input code is concatenated, and the rightmost number indicates the answer. Here, 0 to 15
The truth table of the AND gate is shown up to the address, and the truth table of the OR gate is shown after 16.

[0006]

However, since the method of directly converting the operation of the AND gate into the AND instruction can only handle binary values, all combinations of the four values are required to perform a four-value simulation. However, even if code is generated so that a correct operation can be performed, the operation becomes very complicated, and a significant improvement in simulation speed cannot be obtained. Further, in the conventional logic simulation method shown in FIG. 14A, since bit values are compared, parallel simulation using the number of bits of one word is impossible, and there are many instruction codes. Since the branch using the value of the bit is used, there is a problem that it is not suitable for the operation in the pipeline CPU, the number of operations is large, and as a result, the simulation speed is not improved.

Further, in the conventional logic simulation method shown in FIG. 14B, since a table is searched using bit values, parallel simulation using the number of bits of one word is impossible. In addition, even in the case where assembling is performed most efficiently, four or more instructions of a shift operation, an OR operation, a sum operation, and a memory load are required.

In the conventional logic simulation method described in Japanese Patent Application Laid-Open No. 59-3652, an answer previously stored in a table is determined in order to determine a gate output based on the contents of an input vector memory and a dictionary address memory. Since this is a method of obtaining from an address position corresponding to an input value, there are a plurality of processors, simulation parts, and calculation parts, and parallel processing using them is possible, as shown in FIG. In the same manner as in the conventional method, only one operation unit of the computer is used (1.
Parallel simulation (using the number of bits in a word) is not possible.

[0009] The present invention has been made in view of the above points,
It is an object of the present invention to provide a logic simulation method capable of executing a four-valued simulation at high speed.

Another object of the present invention is to provide a logic simulation system capable of performing parallel processing using only one operation unit.

[0011]

In order to achieve the above object, the present invention provides a first step of reading information of a circuit to be quaternary-simulated, and a step of executing a quaternary simulation based on the read information of the circuit. A second step of separating into a circuit section to perform the three-value simulation and a third step of generating a simulation code for each of the circuit sections separated by the second step.
And a step of: In the present invention,
Rather than performing four-value simulation on all circuit units, circuit units capable of three-value simulation perform three-value simulation.

In the present invention, the second step has a high impedance value as an input value, and
A gate in which the input of the high impedance value and the input of the indefinite value are equivalent is a gate to which ternary values of 0, 1, and the indefinite value are input, and is a circuit unit for performing a ternary simulation.

The present invention relates to a case where a 0-delay or cycle-based simulation using four values is limited to three values of 0 and 1 indefinite values for a portion that can be simulated ignoring a high impedance value as an input value. Use a valid operation.

According to the present invention, in order to achieve the above object, the second step includes a first searching step of searching for a first gate which may have a high impedance value as an output, A first flag setting step of setting a first flag to a fan-out destination of the gate of
Search for a second gate with the flag set
And a third search step of searching for a third gate having the same output value as the input value of the high impedance value and the indefinite value of the second gate, and inputting the third gate from the high impedance value An insertion step of inserting logic for converting to an indefinite value, and a second flag setting step of setting a second flag indicating that the second gate which is not searched as a third gate is a gate for quaternary simulation. And a ternary simulation is performed on the third gate, and a quaternary simulation is performed on the other gates.

Further, in order to achieve the above object, the present invention provides a simulation code, wherein four values used in a simulation are converted into a total of two bits each consisting of one bit at the same position of a first word and a second word. It is characterized by being generated by being expressed by. According to the present invention, not all the circuit units are quaternary-simulated, but the circuit unit capable of ternary simulation can perform the ternary simulation, and the operation can be extremely simplified.

Further, according to the present invention, in order to achieve the above object, the M-th (M = 0, 1,... N) of the first and second words each consisting of N bits (N is an integer of 2 or more). −
The logic simulation is performed by expressing the value of the M-th pattern sequence among the N pattern sequences by using a total of 2 bits including 1 bit of 1). According to the present invention, the values of a plurality of patterns are put in one word of a computer to be used, and the simulation of a plurality of patterns can be executed simultaneously by executing one instruction.

Further, according to the present invention, each of the N pattern sequences has an L pattern (L is an integer of 2 or more), and for each of the L patterns, the M-th one bit of each of the first and second words. The logic simulation is performed in parallel by expressing the value of the M-th pattern sequence among the N pattern sequences using a total of 2 bits consisting of

[0018]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a flowchart of the whole process of one embodiment of the logic simulation system according to the present invention. In the figure, after the start of the processing (step 1
01) First, a circuit information reading process is performed (step 102), and a portion that needs to be operated using the high impedance value Z is limited (step 10).
3). Of the four values in the circuit, the portion where the operation must be performed using the high impedance value Z is limited, so the portion for performing the simulation in consideration of Z is limited.

Subsequently, an optional circuit optimization process is performed to optimize the operation code used for the simulation (step 104). Then, a simulation code is generated (step 105), and the process ends (step 106).

Next, the details of the process for limiting the Z operation necessary portion in step 103 will be described with reference to the flowchart of FIG. In FIG. 2, after the start of the limiting process for the Z operation necessary part (step 201), it is first determined whether all gates have been searched (step 202). If not, the gate to be processed outputs the value Z as the output value. It is determined whether or not the gate has the possibility of having the value Z (step 203). For the gate to be processed which may have the value Z as the output value, the fan-out (F / O) destination of the gate, that is, the output destination A process of setting a flag for the input is performed (step 204).
A gate that may have the value Z as an output value refers to, for example, a wired or transfer gate, and in some cases, an external input terminal.

For all the gates to be processed, it is determined whether or not the gate may have the value Z as an output value.
When a process is performed to set a flag for the input of the fan-out destination of the gate for a processing target gate which may have the output value of “1”, it is then determined whether all gates have been searched (step 205). If not, it is determined whether or not the gate to be processed is the gate for which the flag is set to input in step 204 (step 20).
6).

If the gate is a flag whose input is set (in this case, it means that the Z value is propagated to the input), the gate is determined whether the input Z is applied to the input or the indefinite value X Is given, it is determined whether or not the calculation results are equivalent (step 207). For example, CMOS
When a Z input is input to the AND gate of the configuration, a large through current may flow depending on the value of another input. However, the truth table is usually as shown in FIG.
Is replaced by X, the operation result is completely equivalent. Therefore, a logic (ZX converter) for converting a value from Z to X is inserted into the input of such a portion (step 209).
As a result, a simulation considering only three values is sufficient for this part.

However, if the operation of the Z input is different from the operation when the Z input is replaced with an indefinite value X, the gate needs to be simulated with four values, so that a flag indicating this is set in the gate. (Step 208). This process is repeated for all the gates, and when it is determined that the process for all the gates has been completed (step 205), the limitation process of the Z operation necessary part is ended (step 210).

As described above, in the present embodiment, a quaternary simulation is not prepared on the assumption that all four values are input, but a part where only ternary inputs appear is used. By performing the value calculation, the calculation process is speeded up.

Next, the result of application according to the method of the present invention will be described with reference to the circuit diagram of FIG. In the figure, input terminal 3
01 to 305 are connected to buffers 306 to 310, respectively. Buffers 306 and 307 are connected to a D-type flip-flop (hereinafter referred to as DFF) via a two-input AND circuit 311.
312) is connected to the data input terminal 312. Output terminals of the buffers 307 and 308 are DFFs 313 and 31
4 data input terminals. Each Q output terminal of the DFFs 312 and 313 is connected to the tristate buffer 3
16 and 317 are separately connected by a wired 318 and are connected to one input terminal of a two-input AND gate 319.

The Q output terminal of the DFF 314 is connected to the other input terminal of the AND gate 319 and one input terminal of the two-input AND gate 320, while being connected to the data input terminal of the DFF 324 via the inverter 321. The output terminals of the AND gates 319 and 320 are DFF3
22 and 323 are connected to the data input terminals. DF
Both Q output terminals of F322 and 323 are connected to the data input terminal of DFF 329 via a 2-input AND gate 327, and both Q output terminals of DFF 322 and 324 are connected to the data input terminal of DFF 331 via a 2-input OR gate 326. Have been. The Q output terminal of the DFF 322 is connected to the inverter 325,
5 and both output terminals of the OR gate 326 are connected to the data input terminal of the DFF 330 via a two-input AND gate 328.

The Q output terminals of the DFFs 329, 330 and 331 are connected to output terminals 335, 336 and 337 via buffers 332, 333 and 334.
The output terminals of the buffer 309 are DFF 312, 3
13, 314, 322, 323, 324, 329, 33
0 and 331 are commonly connected to respective clock input terminals. Further, the output terminal of the buffer 310 is connected to the control terminal of the tri-state buffer 316 and the other input terminal of the AND gate 320, while being connected to the control terminals of the tri-state buffers 317 and 334 via the inverter 315, respectively. ing.

Here, assuming that the high impedance value Z is not set to the external input terminals 301 to 305, in the case of a normal CMOS system configuration, the gate having the Z value at the output is the circuit shown in FIG. Here, only the tri-state buffers 316, 317 and 334 are provided. Also, usually
At the time of the simulation, if a plurality of output signals drive the wiring, a simulation operator such as wired is required on the wiring. Therefore, in the simulation, the wired 318 further has a Z value.

Therefore, in this circuit, a 4-value operation is required by the tri-state buffers 316, 317 and 334 and the wired 318, and the Z value is propagated to the fan-out destination, and the Z value is transmitted to the AND gate 319 and the output terminal 337. Although the Z value also propagates, the AND gate 319 normally operates as shown in FIG.
(B), the calculation result when the high impedance value Z is given as the input value is the same as the calculation result when the indefinite value X is given. By inserting the operator to be converted between the AND gates 319, the AND gate 319 may perform an AND operation on only three values.

Therefore, in this circuit, it is necessary to calculate four values in the tristate buffers 316, 317 and 334, the wired 318 and the output terminal 337, and the other parts can be calculated only in three values. Will be. If there is a possibility that a binary value will be input to the external input terminal, it is necessary to further insert a conversion operator from the Z value to the X value after the external input terminal. However, as will be described later, in the tri-state buffer as well, although it is necessary to distinguish the Z value as an output, there is usually no problem even if the Z value of the input value is treated equivalently to the X value. For this reason, in this circuit, the portion that needs to use the Z value as the input value is usually limited to the wired 318.

Next, a description will be given of how the codes are made to correspond to each other at the time of calculation and the calculation. This embodiment is characterized in that a quaternary value is not expressed using two bits of one word, but is expressed using one bit of two separate words, and an operation is performed. The value for each signal is represented by a memory area or a register and described as follows.

The value is expressed by dividing it into a first word and a second word. For example, when the correspondence shown in FIG. 4A is used, the value is represented by two bits, that is, the 0th bit of the first word a1 and the 0th bit of the second word a2, and the logic is obtained when a1 and a2 are 0 and 0, respectively. Represents the value 0 and a1 and a2 are 1 and 1 respectively
Represents a logical value 1, a1 and a2 represent an indefinite value X when 0 and 1, respectively, and a1 and a2 represent a high impedance value Z when a1 and a2 respectively represent 1 and 0. Details will be described later,
When performing parallel processing of two pattern sequences, for example,
The 0th bit of a1 and the 0th bit of a2 represent the value of the first pattern sequence, and the 1st bit of a1 and the 1st bit of a2 represent the value of the second pattern sequence.

That is, the value of the first pattern series is
It is represented by two bits, that is, the 0th bit of the word a1 and the 0th bit of the second word a2. When a1 and a2 are 0 and 0, respectively, the logical value is 0. When a1 and a2 are 1 and 1, respectively, the logical value is 1. When a1 and a2 are 0 and 1, respectively, it represents an indefinite value X, and when a1 and a2 are 1 and 0, respectively, it represents a high impedance value Z. The value of the second pattern sequence is represented by two bits, that is, the first bit of the first word a1 and the first bit of the second word a2.
And 0 represent a logical value 0, a1 and a2 represent a logical value 1 when they are 1 and 1, respectively, and a1 and a2 represent 0 and 1 respectively.
Represents an indefinite value X, and a1 and a2 represent a high impedance value Z when they are 1 and 0, respectively. In this way, when expressed, in the portion of the circuit where the Z value does not appear, each operation can be simplified as follows.

In the case of an AND operation, the operation can be performed as shown in FIG. That is, FIG. 5A shows an operation when an AND operation is performed on only three values in a four-value simulation, and is represented by c1 = a1 AND b1 c2 = a2 AND b2. In this notation, c1 indicates the result of the AND operation of a1 and b1, and c2 indicates the result of the AND operation of a2 and b2.

That is, the truth table of the ordinary AND gate is as shown in FIG. 5B, but when the operation shown in FIG. 5A is performed, the operation result as shown in FIG. can get. In FIG. 5 (C), the notation regarding a
1 and a2 on the right side. Also, b
As for, the left side represents b1 and the right side represents b2. As for the calculation result, the left side indicates c1 and the right side indicates c2. Hereinafter, the notation is the same as that of this table for the following similar tables.

When the operation result shown in FIG. 5C is converted into a logical value, it is shown in FIG. 5D. When the operation result shown in FIG. 5D is compared with the truth table of the ordinary AND gate shown in FIG. 5A, the operation result for the Z input is inaccurate, but 0, 1, and 3 of X It can be seen that an accurate operation result can be obtained for the operation limited to the input of the value.

As for the correspondence between the codes, the same result can be obtained even if X and Z correspond to each other in the opposite manner as shown in FIG. 4B. Also, as shown in FIG. 4C and FIG.
In the case of the opposite correspondence as in (B), it is necessary to use OR for the operation, but the number of operations remains two.
For example, when the correspondence of FIG. 4D is used, an AND operation with three values not including Z is as follows. C1 = a1 OR b1 c2 = a2 OR b2 In this notation, c1 is a1 and b1 OR operation result of
c2 indicates the result of the OR operation of a2 and b2.

FIG. 4A and FIG.
It is also possible to use other than (B), FIG. 4 (C) and FIG. 4 (D). For example, a commonly used method is to put a value in the first word, and when the second word is 0, it represents a fixed value, and when it is 1, it represents X or Z according to the value of the first word. In this case, for example, when the ternary AND operation is performed in the case where the correspondence of FIG. 4E is used, it is slightly complicated, but, for example, can be defined as follows.

C1 = a1 AND b1 c2 = (a1 EXOR b1) OR (a2 AN
D b2) In this notation, c1 is an AND operation result of a1 and b1, and c2 is an OR operation result of an exclusive OR of a1 and b1 and an AND of a2 and b2. Is shown. Basically, the present invention can be used for any code correspondence, but in the following, it will be performed using the correspondence of FIG.

In the case of the OR operation, when the correspondence of FIG. 4A is used, the operation can be as shown in FIG. 6A. That is, FIG. 6A shows an operation when an OR operation is performed on only three values in a four-value simulation, and is represented by c1 = a1 OR b1 c2 = a2 OR b2. In this notation, c1 is the result of the OR operation of a1 and b1, and c2 is the result of the OR operation of a2 and b2.

That is, the truth table of the ordinary OR gate is as shown in FIG. 6B, but when the operation shown in FIG. 6A is performed, the operation result as shown in FIG. can get.

When the operation result shown in FIG. 6C is converted into a logical value expression, it is shown in FIG. 6D. When the operation result shown in FIG. 6 (D) is compared with the truth table of the ordinary OR gate shown in FIG. 6 (A), the operation result for the Z input is inaccurate, but 0, 1, and 3 of X It can be seen that an accurate operation result can be obtained for the operation limited to the input of the value.

The inversion operation NOT, that is, the operation for the inverter, can be performed, for example, as shown in FIG. That is, FIG. 7A shows an arithmetic expression for performing NOT operation on only three values in a four-value simulation, that is, an operation for an inverter, where c1 = NOT a2 c2 = NOT a1. This applies the inversion of the value of the second word a2 of the input to the first word c1 of the output and the first word a1 of the input.
Is applied to the second word c2 of the output. In this notation, c1 is a negative operation result of a2,
c2 indicates that the result is the negative operation of a1.

Basically, by applying the above-described operation targeting only the three values to the part that can be simulated with the three values, a very simple operation can be performed, and the entire circuit can be realized. Simulation for four values can be performed.

Next, an embodiment of the parallel processing according to the present invention will be described. The value for one pattern operation is 2
Each word is represented by, for example, the same bit position. For example, the value of the first pattern is represented by the 0th bit of the first word a1 and the 0th bit of the second word a2, and the value of the second pattern is represented by the 1st bit of the first word a1 and the second bit.
Expressed by the first bit of word a2, the value of the third pattern is the second bit of first word a1 and the second bit of second word a2.
Expressed in bits. Expressed in the same way, at the maximum, a pattern corresponding to the number of bits constituting a word is expressed using two words.

The circuit shown in FIG. 8A is taken as an example of the application circuit. In FIG. 9A, an input terminal 801 (A)
Is connected to one input terminal of a two-input AND gate 806 (F) via an inverter 804 (D).
02 (B) and 803 (C) are 2-input OR gates 805
(E) is connected to the other input terminal of the AND gate 806 (F), and the output terminal of the AND gate 806 (F) is connected to the output terminal 807 (G).

Also, consider a four-series pattern as shown in FIG. 8B as an application pattern. The pattern length may be different, but in this case, it is 2 in each case. Now, it is assumed that the expression on the memory at the time of storing the value and the expression on the value of the register at the time of the operation are both expressed using two words. In addition, the way of associating the values used in the simulation with the codes at the time of calculation in the computer uses the example shown in FIG.

In this case, the manner of retaining the internal value for the first pattern and the calculation result are shown in FIG. FIG.
In (C), the LSB is on the left side, the value of the first sequence at bit 0, the value of the second sequence at bit 1, the value of the third sequence at bit 2, and the value of the fourth sequence at bit 3. And the fourth and subsequent bits are omitted from the notation. It is more efficient to collectively perform the operations of a plurality of gates on the register. Here, the internal values are shown for each operation for one gate. The internal representation of the terminal A at the time of calculation is represented by 831, the internal representation of B is represented by 832, and the internal representation of C is represented by 833.

For example, the values of the first pattern with respect to the terminal A are 0 for series 1, 0 for series 2, 1 for series 3, and X for series 4. These values are the first and second words. When the left is expressed as the first bit and the right is expressed as the second bit in the two bits of the value, the first stream is 00 and the second stream is the second stream from FIG.
Although the sequence is 00, the third sequence is 11, and the fourth sequence is 01, the value of A in FIG. Stored in order, A
2, only the value of the second bit is stored in order from the left.

The internal expressions of the operation results of the inverter D and the OR gate E when the operation result is obtained for each gate are shown by 834 and 835, respectively. The internal representation of the final operation result obtained by the AND gate F is represented by 836. Since the value of G is the same as that of F, it is omitted in the notation. Here, in 831-836, the respective values are A1 and A2, B1 and B2, and C, respectively, for the calculation results of A, B, C, and D, the calculation result of E, and the calculation result of F.
1 and C2, D1 and D2, E1 and E2, and F1 and F2. Based on this value representation, the inverter 804 (D) is connected to the OR gate 80 (FIG. 7A).
FIG. 6 (A), AND gate 806 (F) for 5 (E)
5 is applied to the calculation of FIG.

These operations are specifically performed as follows. For example, as shown in FIG. 5A, the operation of the AND gate 806 (F) is performed with F1 = D1 AND E1 F2 = D2 AND E2. In the first pattern, F1 = 1100 AND 0101 F2 = 11101 AND 0111 is obtained by one operation for each word.
As shown by 936 in (C), F1 = 0100 and F2 = 0101.

As described above, in the present embodiment, a desired operation result can be obtained only by performing the operation once for each gate instead of performing the operation four times for a pattern of four sequences. Similarly, the expression of the calculation result and the internal value of the second pattern is shown in FIG.

Actually, since it is not necessary to obtain the value of the intermediate gate, it is possible to use the entire logic for providing the G operation result as one operation unit and continue the operation on the register. The normal logic is shown in FIG. 8 (E), and this expression is basically a Boolean operation when A2, B1, and C1 are regarded as variables for G1, and for G2. ,
Since A1, B2, and C2 are Boolean operations when viewed as variables, an accurate answer can be obtained even if these are transformed using an optimization method of a Boolean expression.

Further, depending on the CPU, AND
In some cases, the operation of inverting one of the inputs and taking the AND can be executed in one instruction. An example of this is a CPU based on the Spark architecture. Using such instructions may further simplify the formula. FIG. 8F shows a simplified version of G using such an operation.
Shown in In the figure, “ANDN” is described as an operation that takes AND after inverting the value of the left operand.

Next, a description will be given of how to handle a part that needs to be simulated with four values. The part that needs to handle quaternary values is the
Apart from the D, OR, and NOT operations, it is also possible to apply an operation method such as the conventional method. However, like the AND, OR, and NOT operations described below,
An example in which the instruction directly corresponds to the instruction of the computer will be described.

9 (A), 9 (B) and 9 (C) show operations of wired elements, FIGS. 10 (A), 10 (B),
FIGS. 10C, 10D, and 10E show tristate buffer operations, and FIGS. 11A and 11B.
And FIG. 11C shows a Z-value to X-value converter to be inserted between an element having a quaternary output and an element having an operation for ternary input. Is shown. FIGS. 12A and 12B show an example in which a quaternary simulation is realized as a whole by combining a calculation using quaternary values and a calculation using ternary values. 13 (A), 13 (B) and 13 (C)
FIG. 9 is a diagram illustrating an example of a case where circuit models expressing combinations of operations using quaternary values and operations using ternary values are processed in parallel.

For example, an ordinary CMOS wired operation is shown in FIG. This requires a complete four-value operation, and when represented by a 2-bit code,
(C), which can be replaced by the operation of c1 = a1 AND b1 c2 = a2 OR b2 as shown in FIG. 9 (A).

Next, the operation of the tri-state buffer will be described. For a tristate buffer, FIG.
As shown in FIG. 10A, when the data input is set to a, the enable input is set to b, and the output is set to c, the calculation can be usually represented as shown in FIG. In this case, the output is expressed in four values. For the input, even if the Z value is replaced with the X value for a, the operation result is the same. Since the operation result is the same even if the value is replaced with the value, it is also possible to substitute an operation using three values as the input value.
As shown in (B), c1 = (a1 AND b1) OR (NOT (b1
OR b2)) c2 = (a1 AND b2) OR ((NOT b
1) AND b2). The calculation result in this case is as shown in FIG. 10D, and when expressed in four values, as shown in FIG. 10E. The operation result shown in FIG. 10 (D) is compared with the original operation result shown in FIG. 10 (C).
It can be seen that correct calculation results are obtained for the three values of 1 and X.

Next, the operation of the converter from Z to X will be described. In this converter, the operation shown in FIG. 11B needs to be performed, which is expressed as shown in FIG. 11C. This operation can be represented by the operation of c1 = a1 AND a2 c2 = a1 OR a2 as shown in FIG.

Next, an example of realizing a quaternary simulation by combining a calculation using quaternary values and a calculation using ternary values will be described with reference to the circuit of FIG. In FIG. 12A, input terminals 1201 and 1203 are shown.
Are connected to input terminals of tri-state buffers 1206 and 1207, and input terminals 1202 and 1204 are connected to
Reference numeral 8 is connected to the enable terminals of the tri-state buffers 1206 and 1207. Also, the input terminal 1205
Is connected to one input terminal of a two-input AND gate 1210.

The output terminals of the tri-state buffers 1206 and 1207 are connected to the other input terminal of the AND gate 1210 via a wired 1208 and a converter 1209. Here, the converter 1209 does not actually exist in the input circuit,
This is a Z-to-X converter inserted on the simulation model, which is required to realize a value simulation.

Basically, this operation is shown in FIG. The values shown next to the terminals are
These are input values corresponding to the input terminals 1201 to 1205.
For other elements, the calculation results are shown at the upper right of each element. That is, at this input, the outputs of the two tri-state buffers 1206 and 1207 are both Z, and the output of the wired 1208 is also Z. The Z value output from the wired 1208 is converted to an X value by a Z-to-X converter 1209 at an input side of an AND gate 1210 where a ternary operation is performed.
The D gate 1210 performs an AND operation of the value 1 and the X value from the input terminal 1205, and the AND gate 1210
And the value of the output terminal 1211 are X.

Next, FIG. 13 (A), FIG. 13 (B), FIG.
3 (C), a case will be described in which parallel processing is performed on a circuit model expressed by combining the operation using quaternary values and the operation using ternary values according to the method of the present invention. As an applied circuit model, a circuit equivalent to the circuit illustrated in FIG. In FIGS. 13B and 13C, symbols A,
B, C, D, E, F, G, H, J, K, and L are, respectively, 1201, 1202, and 1203 in FIG.
1204, 1205, 1206, 1207, 1208,
1209, 1210, and 1211 represent the same components.

FIG. 13A shows a pattern sequence to be applied. It is assumed that there are four pattern sequences to be applied, and each sequence is composed of two patterns. FIG. 13B shows the state of the simulation of the first pattern, and FIG. 13C shows the state of the simulation of the second pattern.

In FIG. 13B and FIG. 13C, the symbols indicating the elements and the numbers 1 and 2 are the first word and the second word of the simulation value of the element, respectively. Indicates the word. For example, A1 is the value of the first word of A, A
2 indicates the value of the second word of A. The value of each word indicates the value of series 1, the value of series 2, the value of series 3, and the value of series 4 from the left. In addition, the way of associating the values used in the simulation with the codes at the time of calculation in the computer uses the example shown in FIG.

The operation is performed with respect to the AND gate K in FIG.
(A), FIG. 9 (A) for wired H, FIG. 10 (B) for tri-state buffers F and G, and FIG. 11 (A) for converter J from Z to X. Since all of these operations are performed in units of words, by associating the values of each series with the bits of each word in this way, the operation for each element can be performed even in a circuit that needs to treat the Z value as a simulation value. , Four series are simulated simultaneously.

Therefore, according to the present embodiment, only one arithmetic unit of the computer is used for the same circuit (that is, a plurality of circuits and arithmetic parts are provided in parallel as in the conventional case). (Instead of processing), parallel processing of quaternary simulation using two words is possible.

[0068]

As described above, according to the present invention,
Instead of performing four-valued simulations on all circuit parts, circuit parts capable of three-valued simulation perform three-valued simulation. Although depending on the configuration, in a normal configuration, the arithmetic processing body can be suppressed to about twice as long as the binary simulation, and the arithmetic processing can be speeded up.

Further, according to the present invention, instead of expressing the quaternary value using two bits of one word, the four values are expressed using one bit of each of the first and second words, and the operation is performed. Since all the circuit sections are not quaternary-simulated, the circuit section capable of ternary simulation can not only perform the ternary simulation, but also can greatly simplify the arithmetic operation, and the arithmetic processing can be further accelerated. Can be

Further, according to the present invention, each of the M-th (M = 0, 1,... N−1) of the first and second words, each consisting of N bits (N is an integer of 2 or more), By performing a logic simulation by expressing the value of the M-th pattern sequence of the N pattern sequences with a total of two bits consisting of one bit, the values of a plurality of patterns are put in one word of a computer to be used, and one instruction is executed. , Simulations of a plurality of patterns can be executed at the same time, so that a plurality of patterns can be processed in parallel by one arithmetic unit for the same circuit. , And a speed 32 times higher than in the past can be obtained.

Further, according to the present invention, each of the N pattern sequences has L patterns (L is an integer of 2 or more),
For each of the L patterns, the value of the M-th pattern sequence among the N-pattern sequences is expressed by a total of two bits each consisting of the M-th one bit of the first and second words, and the logic simulation is performed in parallel. Since the processing is performed, it is possible to perform a four-value parallel simulation using the number of bits of one word for the same circuit without dividing the processor and the operation part.

[Brief description of the drawings]

FIG. 1 is a flowchart of an embodiment of the entire process of the present invention.

FIG. 2 is a flowchart for explaining in detail a limiting process of a Z operation necessary section in FIG. 1;

FIG. 3 is a circuit diagram of an example for explaining an application result of the present invention.

FIG. 4 is an explanatory diagram of each example of a method of associating a value used in a simulation of the present invention with a code of an arithmetic character in a computer.

FIG. 5 is an explanatory diagram of an arithmetic operation when an AND operation is performed on only three values in a four-value simulation according to the present invention.

FIG. 6 is an explanatory diagram of an operation when performing an OR operation on only three values during a four-value simulation according to the present invention.

FIG. 7 is an explanatory diagram of a calculation when a negation operation is performed only on three values in a four-value simulation according to the present invention.

FIG. 8 is a diagram illustrating an example of an applied circuit and an applied pattern example during parallel processing according to the present invention.

FIG. 9 is an explanatory diagram of a calculation when a wired calculation is performed on four values during a four-value simulation according to the present invention.

FIG. 10 is an explanatory diagram of a calculation when a tristate buffer calculation is performed on four values in a four-value simulation according to the present invention.

FIG. 11 is a graph showing Z in a four-value simulation according to the present invention;
FIG. 9 is an explanatory diagram of a conversion operation from a value to an X value.

FIG. 12 is a diagram showing an example in which a four-value simulation is realized as a whole by combining a calculation using four values and a calculation using three values.

FIG. 13 is an explanatory diagram in the case of parallel processing of an example of a circuit model expressed by combining an operation using four values and an operation using three values.

FIG. 14 is an explanatory diagram of each example of a conventional four-value simulation method.

[Explanation of symbols]

301-305, 801-803, 1201-1205
Input terminals 306 to 310, 332, 333 Buffers 311, 319, 320, 327, 328, 806, 1
210 2-input AND gates 312, 313, 314, 322, 323, 324, 3
29, 330, 331D flip-flop (DFF) 315, 321, 325, 804 Inverter 316, 317, 334, 1206, 1207 Tri-state buffer 318, 1208 Wired 326, 805 2-input OR gate 335-337, 807, 1211 Output Terminal 1209 ZX converter

Claims (6)

[Claims] A first step of reading information of a circuit for performing a quaternary simulation; and a circuit unit for performing a four-value simulation and a circuit unit for performing a three-value simulation of the circuit based on the read information of the circuit. A logic simulation method, comprising: a second step of separating; and a third step of generating a simulation code for each of the circuit sections separated by the second step. 2. The method according to claim 1, wherein the second step is to set a gate having a high impedance value as an input value and having a high impedance value input and an indefinite value input equivalent to 0 and 1 gates.
2. The logic simulation method according to claim 1, wherein a gate to which a ternary value is input is provided as a circuit unit for performing the ternary simulation. 3. The second step includes: a first search step of searching for a first gate which may have a high impedance value as an output; and a first gate in a fan-out destination of the first gate. A first flag setting step of setting a flag, a second step of searching for a second gate whose input has the first flag set, and an input value of the second gate being a high impedance value A third search step of searching for a third gate having the same output value as the third gate and an indefinite value; an insertion step of inserting logic for converting an input of the third gate from a high impedance value to an indefinite value; A second flag setting step of setting a second flag indicating that the second gate not searched as the third gate is a gate for performing a quaternary simulation, the third gate 3. The logic simulation method according to claim 1, wherein a ternary simulation is performed on the other gates, and a quaternary simulation is performed on the other gates. 4. The simulation code is generated by expressing quaternary values used in a simulation by a total of two bits each consisting of one bit at the same position of a first word and a second word. The logic simulation method according to claim 1, wherein 5. Each of N bits (N is an integer of 2 or more)
M-th (M = 0, M) of the first and second words consisting of
1,. . . 5. The logic simulation method according to claim 4, wherein the logic simulation is performed by expressing the value of the M-th pattern sequence among the N pattern sequences by using a total of 2 bits consisting of 1 bit of (N-1). . 6. The N pattern sequences each have an L pattern (L is an integer of 2 or more), and for each of the L patterns, each of the M-th 1 bit of the first and second words is 6. The logic simulation is performed in parallel by expressing the value of the M-th pattern sequence among the N pattern sequences using a total of 2 bits.
The described logic simulation method.