JP2729061B2 - Zero-delay operation processing method for simulation equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a zero-delay operation processing method of a simulation apparatus for determining an input value by a zero-delay primitive (input delay value zero) for operation and evaluation of an output value of a circuit model. Even if the circuit model has variable delay primitives, the purpose is to calculate the input value of the zero delay primitive at high speed. From the circuit model, there are two types with input / output connections of only the zero delay primitive and only the variable delay primitive Generate a new separated circuit model, and when an event occurs at zero delay, fan-out the model with input / output connection of only zero delay primitive according to the net value determination ordering, and simultaneously perform double registration prevention processing Store the zero-delay primitive in the dedicated queue and store it in the dedicated queue. Performs a logical operation on the zero-delay primitive to determine the output value, and further updates the net value if it is necessary to change the net value at the same simulation time,
Until the dedicated queue becomes empty, the fan-out expansion, storage of the dedicated queue, logical operation, and updating of the net value are repeated.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a zero-delay operation processing method of a simulation apparatus that executes an operation for determining an input value of a zero-delay primitive in order to evaluate a primitive output value of a simulation model.

CA that performs logical design of hardware such as computers
In the field of E (Computer Aided Engineering), a simulation device is used as a tool for verifying a created logical design model.

In such a simulation apparatus, a logic simulation and a timing simulation dealing with a detailed delay value are executed to verify the effectiveness and the like when a test pattern is created from a logic design model.

By the way, in such logic and timing simulation, processing for determining an input value is required when calculating and evaluating an output value of a circuit model. In order to determine this input value, zero delay processing and detailed delay processing are required. Processing is performed.

That is, the zero delay processing means that a dot primitive, a check primitive, or the like, which is the minimum unit of the arithmetic processing configuring the simulation circuit model, is treated as a zero delay element primitive having a total input delay value of zero. Is used to calculate and evaluate the output value when an event occurs on the input side of.

On the other hand, the detailed delay processing is to prepare a detailed delay value for an appropriate element primitive in consideration of an actual line length delay and an element logic delay, and use the detailed delay value for the occurrence of an input event to output an element primitive output value. This is for performing arithmetic evaluation.

In a general simulation circuit model, input primitives for performing zero delay processing and input primitives for performing detailed delay processing are mixed, and it is desirable to perform zero delay processing at high speed even with such a circuit model. It is.

[Prior Art] Conventionally, zero delay processing and detailed delay processing are mixed.
In the zero-delay calculation processing method for the path simulation processing (a method in which all net values with events are determined and then calculated), an event setting, a net value creation, and an update phase are performed for each discrete simulation time. And fan-out expansion, operation evaluation, event scheduling, and the like.

For this reason, at the same simulation time, there is a phase in which the net value is updated in accordance with the calculation order of the zero-delay primitive. For a zero-delay primitive whose net value is not determined, the calculation is repeated a plurality of times until the net value is determined. I have.

[Problems to be Solved by the Invention] However, in such a conventional zero-delay operation processing for determining a net value of a zero-delay primitive at the same simulation processing time, for a primitive whose net value is not determined, Until the net value is determined, the arithmetic processing must be repeated a plurality of times. Unnecessary arithmetic processing is performed until the net value is determined, and the calculation converges. Depending on the circuit model, there is a problem that the arithmetic processing time becomes longer. there were.

The present invention has been made in view of such a conventional problem, and it is possible to quickly calculate an input final value by a zero delay primitive even in a circuit model in which input delay primitives of zero delay and detailed delay are mixed. An object of the present invention is to provide a zero-delay operation processing method for a logic simulation device.

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention.

In FIG. 1, first, the present invention relates to a zero-delay operation of a simulation apparatus for executing an operation for determining an input value for evaluating an output value of a circuit model in which a zero-delay primitive and a variable-delay primitive are mixed at an input connection destination. Targets processing method.

According to the present invention as such a zero-delay operation processing method, first, based on the circuit model to be simulated, the model generation unit 10 only inputs a model connected to only the zero-delay primitive and only a variable-delay primitive. Generate a new circuit model separated from the input connected model.

The delay element having the input connection of only the zero delay primitive generated by the model generation unit 10 is identified, and the fan-out expansion processing unit 12 performs fan-out expansion in accordance with the net value.

When an event occurs in the zero delay net value, the zero delay primitive obtained by the access of the fan-out expansion processing unit 12 is stored in a dedicated queue of the zero delay queue storage unit 14.

When storing in the zero-delay queue storage unit 14, the double registration prevention processing unit 16 performs processing to prevent double registration when a simultaneous event occurs.

Based on the zero-delay primitives stored in the 16 dedicated queues of the zero-delay queue complete storage unit, the operation evaluation unit 18 performs an operation according to the function code to determine the output value of the zero-delay primitive.

Further, if there is a simultaneous event occurring in a plurality of zero-delay primitives at the same simulation time, the net value is updated by the net value update unit 20 in order to determine the output value of the next zero-delay primitive, and the fan-out is performed. The expansion processing unit 12 is accessed.

The sequential processing by the fan-out expansion processing unit 12, the zero delay queue storage unit 14, the double registration prevention unit 16, the operation evaluation unit 18, and the net value update unit 20 is performed by the zero delay queue storage unit 14.
Is configured to be repeated until the dedicated queue becomes empty.

[Operation] In the zero-delay operation processing method of the simulation apparatus according to the present invention having such a configuration, the mixed circuit model of the zero-delay primitive and the variable-delay primitive is separated into a model having the same type of input connection, On the separated zero-delay primitive side, the conventional zero-delay model is ordered due to sequence processing. This is automatically controlled by the method of the present invention, and the input sequence is automatically input to the dedicated queue, and the input delay value is determined at one simulation time. Thus, even in a circuit model in which a zero-delay primitive and a variable-delay primitive are mixed, an operation for determining a zero-delay-side input value used for operation evaluation of a circuit model output value can be performed at high speed.

[Embodiment] Fig. 2 is an embodiment configuration diagram showing one embodiment of the present invention.

In FIG. 2, reference numeral 10 denotes a model generation unit. Zero delay elements constituting a circuit model to be simulated are connection delay elements having only zero delay primitives and variable delay primitive connection only depending on the primitive type of the input / output connection destination. Delay elements are further classified as connection delay elements in which a zero delay primitive and a variable delay primitive are mixed.

That is, a circuit model composed of delay elements having three types of primitive connection types of fine side inputs shown in FIG. 3 is to be processed.

In FIG. 3, reference numeral 50 denotes a delay element in which all fine-side primitives have a zero-delay primitive "0" (the sum of input / output delay values is zero). Vd "(the sum of the input / output delay values is Vd), and reference numeral 52 denotes a mixed type in which the fine-side connection primitives include a zero delay primitive" 0 "and a variable delay primitive" Vd ".

FIG. 4 is an explanatory diagram showing an example of a circuit model to be simulated constituted by a primitive connection type for each fan-in connection destination of the zero delay element. The circuit model shown in FIG. This is set in the model generation unit 10 in FIG.

That is, in FIG. 4, all of the delay elements 53 to 59 treated as the zero delay are circuit models in which the fine side primitive is a mixture of the zero delay primitive “0” and the variable delay primitive “Vd”.

When such a circuit model shown in FIG. 4 is set in the model generation unit 10 of FIG. 2, the model generation unit 10 generates a new circuit model shown in FIG. 5 from the circuit model of FIG.

The circuit model of FIG. 5 is configured by separating the circuit model of only the fan-in side zero delay primitive “0” in the circuit model of FIG. 4 into delay elements 60, 62, 63 and 65. Only the variable delay primitive "Vd" indicated by Δ1 and Δ2 in FIG. 4 is divided into delay elements 61, 64 and 66 having fine-side input connections.

Further, the fan-out of delay elements 60, 62, 63 and 65, in which only the zero delay primitive is connected on the fine side, is
And a circuit model for determining the input value of the zero delay primitive to the delay element 69 at the last stage.

Of course, the fan-out of the delay elements 61, 64 and 66 in which only the variable delay primitive is connected to the fan-in side is the delay element 6
8 and is commonly connected to the delay element 69 at the final stage.

Referring to FIG. 2 again, the fourth
Generation of a circuit model separated from the circuit model shown in FIG. 5 by the input / output primitive types shown in FIG. 5 is performed in a pre-processing phase of the simulation apparatus, and the model generating unit 10 performs initialization processing in the pre-processing phase. The created file information of the circuit model shown in FIG. 5 is sequentially developed by the fan-out development processing unit 12 and stored in the memory.

The fan-out expansion processing unit 12 includes the memory access unit 10
1, a memory 102 for storing a fan-out pointer and the number of fan-outs, a memory access unit 103, a memory 104 for storing fan-out expansion data, a memory access unit 106 having a counter 105 and a fan-out net value, a rising input delay value, The memory 107 stores a falling input delay value and a zero delay flag.

That is, the fan-out expansion processing unit 12
When the circuit model in which the fan-in connection shown in FIG. 5 is separated into a model with only a zero-delay primitive and a model with only a variable-delay primitive is generated, the memory access unit is used for the generated circuit model. 101 stores the fan-out pointer and the fan-out number for the memory 102, and then stores the memory 1 in the memory 1 by the access unit 103.
02 stores fan-out expanded data in the memory 104 based on the fan-out pointer and the fan-out number, furthermore, fan-out expanded fan-out values in the memory 107 by the memory access unit 106, and rise and fall input delay values of delay elements And a zero delay flag for handling the input / output delay value as a zero delay.

For the fanout expansion processing unit 12, a double registration prevention unit 16 including a memory access unit 108 and a double registration prevention flag memory unit 109 is provided. Also, the queue access unit 11
The zero delay queue storage unit 14 is constituted by 0 and the zero delay queue memory unit 111. Furthermore, the stack access unit
The circuit unit that stores the variable delay primitive is configured by the 112 and the operation evaluation gate stack memory unit 113.

The zero delay primitive of the zero delay queue memory unit 111 read from the queue access unit 110 of the zero delay queue storage unit 14 or the operation evaluation gate read from the stack access unit 112 The detailed delay primitive of the stack memory unit 113 is the operation evaluation unit 18 and executes a logical operation according to the function code unit 119. Operation evaluation section 1
From the result of the logical operation by 8, the zero delay primitive needs to change the net value within the same simulation time, so the zero delay event result obtained by the operation evaluation unit 18 is output to the net value update unit 20 and determined. Update net values.

The net value update unit 20 includes a stack access unit 114, an updated net data stack memory 115, and a net value update control unit 11.
6. It is composed of a net value update memory 117.

Next, the operation of the zero-delay calculation processing of the present invention according to the embodiment of FIG. 2 will be described.

First, at the time of initialization, which is a pre-processing phase of the simulation apparatus, the model generation unit 10 performs, for example, a circuit model in which the fan-in side of the zero-delay primitive shown in FIG.
As shown in FIG. 5, a new circuit model is generated in which the fan-in side of the zero-delay primitive is composed of a model separated into only the zero-delay primitive and a model separated into only the variable-delay primitive.

Subsequently, for the circuit model newly generated by the model generation unit 10, the memory access unit 101 of the fan-out expansion processing unit 12 sets the fan-out pointer 19 and the fan-out number for the memory 102, and this fan-out Subsequently, based on the setting of the pointer and the number of fan-outs, the memory access unit 103 performs fan-out expansion on the memory 104.
Further, the memory access unit 106 sets a fan-out net number for the memory 107 based on the fan-out expansion information, stores the rising and falling input delay values based on the detailed delay value,
Further, a zero delay flag for treating the delay element as a zero delay is set.

Assuming that an event occurs in the zero delay net No. in the arithmetic processing by the arithmetic evaluation unit 18 in a state where the above initial settings have been completed, the memory access unit 101 of the fan-out expansion unit 12 accesses by the output of the arithmetic evaluation unit 18. Then, the fan-out pointer and the fan-out number of the memory 102 are read by the memory access unit 101, and the fan-out expansion information and the memory access unit 106 are read by the memory access unit 103 in accordance with the fan-out pointer and the fan-out number.
The fan-out net No., the rising and falling input delay values, and the zero-delay flag are read from the memory 107, and the fan-out expansion process is executed for each of the zero-delay primitives automatically ordered when the circuit model of FIG. 5 is generated. Then, the fan-out net No. of the memory 107 is output to the memory access unit 108 of the double registration prevention unit 16.

The memory access unit 108 has a double registration prevention flag memory 1
09 is accessed and zero-delay primitives are controlled so as not to be registered twice in the control queue of the zero-delay queue memory unit 111 when an event occurs at the same time, and zero-delay is performed by the queue access unit 110 under double registration prevention control. The zero-delay primitive fan-out expanded to the queue memory unit 111 is
Stored in automatically ordered order. Of course, the fan-out expansion result of the variable delay primitive is stored in the operation evaluation gate stack memory unit 113 by the stack access unit 112.

Here, since it is necessary to update the net value at the same simulation time, the function code 11
According to the function code of 9, the operation evaluator 18 performs an operation evaluation on the delay primitive stored in the zero delay queue memory unit 111 in an operation evaluation gate stack memory.
This is performed prior to 113, and the output value of the operation evaluation unit 18 is stored in the updated net data stack memory 115 by the stack access unit 14 provided in the net value updating unit 20. The net value update control unit 116 uses the update net data stored in the update net data stack memory 115 to
17 is updated to make the net value at the same time the latest value. By repeating the above process, the simulation process is automatically performed with the order of the fan-in side net value of the zero delay primitive determined as a determined value, and executed.
The process is repeated until the counter value of the counter 105 provided in the memory access unit 106 becomes zero.

That is, in the zero-delay operation processing of the present invention, when a circuit model including only the zero-delay primitive is created for each element for each connection destination on the fan-in side by the model generation unit 10, the operation order is automatically performed together with the occurrence of an event. A control queue is provided in a zero-delay primitive to determine an input definite value for evaluating an output value of a circuit model so that a zero-delay primitive is operated in accordance with an operation order, and simulations are sequentially performed at the same time. The net value is updated with time, and the operation of the zero-delay primitive can be performed with the determined value.

As a result, if the connection destination of the zero delay element is random with respect to the circuit model in which the zero delay primitive and the variable delay primitive are mixed in the logic simulation apparatus, it is necessary to update the Net value at the same time, and the order of the operation becomes poor. Come. Therefore, as in the conventional method, the final connection destination of the zero-delay primitive is searched, and the operation sequence is disregarded, so that the useless operation process at the stage of uncertain input value and the operation process until the input value is determined are repeated. And the like are not required, and the zero-delay operation processing speeded up as compared with the conventional method can be realized.

Of course, the circuit models shown in FIGS. 4 and 5 are merely examples, and the present invention determines the input value using a zero-delay primitive for logically evaluating the output value for an appropriate logic-designed circuit model. Can be processed at high speed.

[Effects of the Invention] As described above, according to the present invention, even if the connection destination on the fan-in side of the zero delay element is a circuit model in which a zero delay primitive and a variable delay primitive are mixed,
The arithmetic processing is performed after the input value by the zero delay primitive for arithmetically evaluating the output value is always determined, so that the arithmetic processing can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention; FIG. 2 is a diagram illustrating the configuration of an embodiment of the present invention; FIG. 3 is a diagram illustrating a fan-in side connection type of a zero-delay primitive; FIG. FIG. 5 is an explanatory diagram of a circuit model in which fan-in and fan-out of the present invention are separated into the same type. In the figure, 10: Model generation unit 12: Fan-out expansion processing unit 14: Zero delay queue storage unit 16: Double registration prevention unit 18: Operation evaluation unit 20: Net value update unit 50 to 69: Delay element (zero delay) 101, 103, 106, 108: Memory access unit 102, 104, 107: Memory 105: Counter 109: Double registration prevention flag memory 110: Queue access unit 111: Zero delay queue memory 112, 114: Stack access unit 113: Operation evaluation gate stack memory 115: Update net data stack memory 116 : Net value update controller 117: Net value update memory

Claims (1)

(57) [Claims] 1. A circuit model in which a zero delay primitive and a variable delay primitive are mixed at an input / output connection destination.
In a zero-delay operation processing method of a simulation apparatus for executing an operation for determining an input value by the zero-delay primitive in order to evaluate an output value of the circuit model, based on the circuit model, only a zero-delay primitive is input. A model generator (10) for generating a new circuit model separated into an output-connected model and a model connected only to the variable delay primitive, and a zero delay generated by the model generator (10) A fan-out expansion processing unit (12) for identifying a delay element having an input connection of only a primitive and expanding the fan-out in accordance with a net number; A zero-delay queue storage unit (14) for storing the zero-delay primitive obtained by the access in (12) in a dedicated queue; A double registration prevention unit (16) for preventing double registration when a simultaneous event occurs in a dedicated queue of the delay queue storage unit (14); and a zero delay stored in a dedicated queue of the zero delay queue storage unit (14). An operation evaluator (18) for performing an operation according to a functional code based on the primitive to determine an output value of the zero-delay or delay primitive; and when a plurality of zero-delay primitives have a simultaneous event at the same simulation time. A net value updating unit (20) for updating a net value to determine the output value of the next zero-delay primitive and accessing the fan-out expansion processing unit (12). (12), zero delay queue processing unit (14), double registration prevention unit (16), operation evaluation unit (18), and net value update unit (2
A zero-delay operation processing method for a simulation apparatus, wherein the sequential processing of 0) is repeated until the dedicated queue of the zero-delay queue processing unit (14) becomes empty.