JPH05346451A - Short circuit tester - Google Patents

Abstract

PURPOSE:To provide a short circuit tester which can perform short circuit test automatically with high work efficiency in a short time. CONSTITUTION:The short circuit tester comprises a switching circuit for switching between output signal from an internal circuit 11 and a test signal, a first exclusive OR circuit 22 for producing exclusive logical sum of two potentials on an upper side pin 12A and an adjacent pin 12B, and a second exclusive OR circuit 24 for producing exclusive logical sum of two potentials on a lower side pin 12C and an adjacent pin 12B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a short-circuit test circuit for performing a short-circuit test between LSI pins and generating short-circuit count information or short position information. Although a short circuit test between pins of an LSI already mounted on a printed circuit board is visually performed, this is inefficient in working and takes a long test time. It has been desired to develop a short test circuit that automatically performs a short test without human intervention.

[0002]

2. Description of the Related Art A conventional method for testing a short circuit between LSI pins is, for example, as shown in FIG. In FIG. 6, 1 is an LSI, and the LSI 1 has a large number of pins 2 and the pitch between the pins 2 is narrow.
The test operator uses the magnifying glass 3 to visually perform a short-circuit test between the pins 2 indicated by the arrow. In addition, 4 indicates a short-circuited portion.

[0003]

However, in such a conventional short-circuit test method, in the case of testing an LSI having a large number of pins or an LSI having a narrow pitch between pins, the work efficiency is poor and the test is performed. There was a problem that it took time. The present invention has been made in view of the above conventional problems, and an object of the present invention is to provide a short test circuit capable of automatically performing a short test in a short time with high work efficiency. ..

[0004]

FIG. 1 illustrates the principle of the present invention. In FIG. 1, 16 is an internal circuit 11 of the LSI.
And a pin 12 for switching between the output signal of the internal circuit 11 and the test signal, and a switching circuit 22 for exclusive-ORing the two potentials of the upper pin 12A and the pin 12B adjacent thereto. 1 is an exclusive OR circuit, and 24 is a second exclusive OR circuit which takes an exclusive OR of two potentials of the lower pin 12C and the pin 12B adjacent thereto.

[0005]

In the present invention, when the short circuit test between the pins of the LSI is performed, the short circuit test is performed by switching to the test signal by the switching circuit. In this case, when the output of the first exclusive OR circuit is, for example, "0", there is a short circuit with the upper pin when the exclusive OR of the two potentials of the upper pin and the pin adjacent thereto is taken. Judge, "1"
In case of, it is judged that there is no short circuit with the upper pin.

Further, when the output of the second exclusive OR circuit is, for example, "0", the lower pin and the pin adjacent to the lower pin are subjected to exclusive OR, and the lower pin is short-circuited. If it is “1”, it is determined that there is no short circuit with the lower pin. In this way, it is possible to automatically perform a short-circuit test between pins of an LSI without the intervention of human work. Therefore, the working efficiency can be improved and the test time can be shortened.

Further, it is possible to easily generate short-circuit number information or short-position information based on the obtained short information.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 5 are views showing an embodiment of the present invention.
In FIG. 2, 11 is an LSI internal circuit, 12 is a pin, and a plurality of short circuit test circuits 13 are provided between the pin 12 and the internal circuit 11.

Reference numeral 14 is an input buffer connected to the pin 12, and 15 is an output buffer connected to the pin 12.
Next, FIG. 3 shows an internal configuration of the short circuit test circuit 13.
In FIG. 3, reference numeral 16 is a multiplexer as a switching circuit. The multiplexer 16 is composed of a knot circuit 17, two AND circuits 18A and 18B, and a NOR circuit 19, and switches the output signal or the test signal from the internal circuit 11. I do. When "1" is input as the test signal, "1" is output from the multiplexer 16.

That is, when the short test circuit 13B is activated, the adjacent short test circuits 13A and 13A are
C is inactive. The output of the OR circuit 20 of the short circuit test circuit 13C is "0", and this output is the knot circuit 21.
Is inverted to become "1" and is input to the AND circuit 18B. Reference numeral 22 denotes a first exclusive OR circuit to which the output potential of the upper pin 12A and the output potential of the pin 12B are input.
The exclusive OR circuit 22 has pins 12A and 12B on the upper side.
"0" is output to the AND circuit 23 when short-circuited between them and "1" when not short-circuited.

Reference numeral 24 is a second exclusive OR circuit to which the output potential of the lower pin 12C and the output potential of the pin 12B are input. The second exclusive OR circuit 24 connects the lower pin 12C and the pin 12B. If there is a short circuit between them, "0" is output to the AND circuit 23, and if not, a "1" is output to the AND circuit 23. Therefore, the AND circuit 23 outputs "0" as a status signal when there is a short circuit and "1" when there is no short circuit. 14A to 14C are input buffers,
15A to 15C are output buffers, and 25 is a multiplexer of the short test circuit 13A.

Next, the short circuit number information generating circuit will be described with reference to FIG. Here, it is assumed that there are eight status signals indicating short-circuit information. 31 to 34 are 1-bit half adders, and 1-bit half adders 31 to 34 have 2
One status signal is input in 1-bit units, and these are added to output 0-2. 35 and 36 are 2-bit half adders, and the 2-bit half adders 35 and 36 have 1
The outputs of the bit half adders 31 to 34 are input, these are added, and 0 to 4 are output. Reference numeral 37 denotes a 3-bit half adder. The outputs of the 2-bit half adders 35 and 36 are input to the 3-bit half adder 37, and these are added to output 0 to 8. An output buffer 38 is connected to the 3-bit half adder 37.

For example, as a status signal, "1100
1111 ”is input, 1-bit half adders 31 to 3
Each output of 4 becomes "2", "0", "2", "2",
The outputs of the 2-bit half adders 35 and 36 are "2",
Becomes "4" and the output of the 3-bit half adder 37 is "6"
Becomes Therefore, the number of short circuits is 2 (8-6). In this way, the short-circuit number information is output to the LSI internal data bus.

Next, the short position information generating circuit will be described with reference to FIG. In FIG. 5, reference numeral 41 is an address decoder (decoding circuit) to which address data of an address bus inside the LSI is input. The address decoder 41 decodes the address data and outputs a switching signal to a multiplexer (switching circuit) 42. A plurality of status signals indicating short-circuit information are input to the multiplexer 42 on a bit-by-bit basis. Here, the status signals are divided and output according to the number of bits of the LSI internal data bus. That is, the status signal is 4 bits at a time, A0 to A3, B0 to B3,
It is divided into three parts, C0 to C3, and output. Each status signal indicates a short-circuited position between predetermined pins in advance.

The multiplexer 42 outputs the divided status signals A0 to A3, the status signals B0 to B3, or the status signals C0 to C3 based on the switching signal from the address decoder 41. For example, the status signal is “1100 1111 1111”, that is, A3 = 1, A2 = 1, A1 = 0, A0 = 0, B3.
= 1, B2 = 1, B1 = 1, B0 = 1, C3 = 1, C2
= 1, C1 = 1, C0 = 1, the switching signal from the address decoder 41 first outputs "1100", then "1111", and then "111".
1 ”is output. In this way, the short position information can be generated.

As described above, since the short circuit test between the pins of the LSI can be automatically performed without human intervention, the work efficiency can be improved and the test time can be shortened. Further, it is possible to easily obtain the short-circuit number information or the short position information.

[0017]

As described above, according to the present invention, the pin short circuit test of the LSI is automatically performed without the intervention of human work, so that the workability can be improved. The test time can be shortened.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention.

FIG. 2 is an overall configuration diagram showing an embodiment of the present invention.

FIG. 3 is a block diagram of a short circuit test circuit.

FIG. 4 is a diagram showing a short count information generation circuit.

FIG. 5 is a diagram showing a short position information generation circuit.

FIG. 6 is a diagram showing a conventional example.

[Explanation of symbols]

 11: Internal circuit 12, 12A to 12C: Pin 13, 13A to 13C: Short test circuit 14, 14A to 14C: Input buffer 15, 15A to 15C: Output buffer 16, 25: Multiplexer (switching circuit) 17, 21: Knot Circuit 18A, 18B, 23: AND circuit 19, 20: OR circuit 22: First exclusive OR circuit 24: Second exclusive OR circuit 31-34: 1-bit half adder 35, 36: 2-bit half addition 37: 3-bit half adder 38: Output buffer 41: Address decoder (decoding circuit) 42: Multiplexer (switching circuit)

Claims (3)

[Claims] 1. An internal circuit (11) and a pin (12) of an LSI.
A switching circuit (16) provided between the internal circuit (11) and the output signal of the internal circuit (11) to switch the test signal, and an upper pin (12A) and a pin (12B) adjacent thereto exclusive of two potentials. First exclusive OR circuit (22) that takes the logical sum
, The lower pin (12C) and the adjacent pin (12C)
A short test circuit comprising a second exclusive OR circuit (24) for taking an exclusive OR of the two potentials of B). 2. The input number of short information in bit units is n
N / 2 1-bit half adders (31 to 3)
4), n / 4 2-bit half adders (35), (3
6), a short number information generating circuit formed by combining half adders configured as n / 8 3-bit half adders (37) until the number of inputs becomes equal to n is provided. The short circuit test circuit according to claim 1. 3. A switching circuit (42) for dividing and outputting a plurality of short-circuit information input in bit units according to the number of bits of an LSI internal data bus, and an address data by decoding an address data of an address bus inside the LSI. A decoding circuit (41) for outputting a switching signal according to data to the switching circuit (42) and controlling the switching by dividing the switching circuit (42).
2. The short circuit test circuit according to claim 1, further comprising a short position information generating circuit.