JPH07121576A - Failure simulation device - Google Patents

Abstract

PURPOSE:To obtain a failure simulation device capable of automatically extacting a signal line having the probability of generating a short-circuit failure and executing failure simulation for the extracted signal line. CONSTITUTION:A wiring information extracting means 2 extracts wiring information from layout data 1. A short-circuit failure generating position specifying means 4 specifies a signal line whose short-circuit failure is to be detected based upon the extracted wiring information and a failure generation condition described in a failure generation condition file 3. A short-circuit simulation executing means 5 executes short-circuit failure simulation while supposing the generation of a shirt-circuit failure on the specified signal line. A short- circuit failure error information output means 6 outputs the simulation result as an error information list 7. Consequently a signal line to be failed can be specified by a uniform reference and the misinput of the signal line to be failed can be prevented. In addition, failure simulation execution time including preparation for the execution can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure simulation device for detecting a failure state of a logic circuit.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a conventional fault simulation apparatus. In the figure, 8 contains a netlist describing the gate function of the entire logic circuit to be simulated and the mutual connection relationship. A logic circuit diagram file, 9 is a logic circuit information extracting means for extracting a failure simulation execution netlist from the logic circuit diagram file 8, and 10 is a short circuit or open circuit fault for verifying whether a short circuit or an open circuit fault can be detected. A short circuit / open fault detection signal line setting file for setting a signal line that is expected to be a short circuit or an open fault is predicted from the netlist extracted by the logic circuit information extraction means 9 and the short circuit / open fault detection signal line setting file 11. Input signal line and execute the failure simulation to make short circuit / open circuit error. Failure simulation execution means for verifying whether or not it can be detected, 12 is failure error information output means for outputting error information detected by the failure simulation execution means 11, and 13 is an error information list output by the failure error information output means 12. is there.

Next, the operation will be described. First, the logic circuit information extracting means 9 extracts a failure simulation execution netlist from the netlist of the entire logic circuit of the logic circuit diagram file 8. Then, the logic circuit information extraction means 9 outputs the extracted netlist to the failure simulation execution means 11.

On the other hand, the signal line for which a short circuit or open circuit fault should be detected is manually set in the short circuit / open circuit fault detection signal line setting file 10. The fault simulation executing means 11 inputs the signal line to be simulated from the short circuit / open fault detection signal line setting file 10.

The fault simulation executing means 11 uses the fault simulation executing netlist to target only the signal lines set in the short circuit / open fault detection signal line setting file 10 or, if not set, all signals. The failure simulation is executed for.
A failure simulation is executed using a predetermined simulation pattern, and output data accompanying the simulation is obtained. If this output data does not match the data expected to be output when it is assumed that there is no failure, it is possible to detect that a failure has occurred according to a predetermined simulation pattern.

The failure error information output means 12 outputs, as an error information list 13, output data and the like output indicating that a failure has occurred, that is, information in which the failure simulation executing means 11 detects a short circuit / open failure as an error.

[0007]

Since the conventional failure simulation apparatus is configured as described above, the signal line for detecting a short circuit or an open failure should be considered in consideration of actual wiring.
Since it has to be set manually, it takes a lot of time to execute the failure simulation, and there are problems such as setting mistakes. In addition, when all signals are executed, there is a problem that failure simulation requires a lot of time.

The present invention has been made in order to solve the above problems, and it is possible to automatically extract a signal line which may cause a short circuit or an open circuit failure, and to perform a failure simulation on the extracted signal line. The purpose is to obtain a feasible failure simulation device.

[0009]

A failure simulation apparatus according to a first aspect of the present invention is a failure simulation apparatus for detecting a failure state of a logic circuit by using circuit information describing a gate function of the logic circuit and mutual connection relationships. In addition, a wiring information extraction means for extracting predetermined wiring information from the layout data, the circuit information and the wiring information are input, and a short-circuit fault is generated based on a comparison between the wiring information and a predetermined fault occurrence condition. A short-circuit fault occurrence location identifying means for identifying a location in the logic circuit where the short circuit fault is expected to occur on the circuit information, and the short circuit fault occurs at the location identified by the short-circuit failure occurrence location identifying means, and the circuit information is used. A failure simulation executing means for executing the failure simulation, and verifying whether the short-circuit failure can be detected as an error; It is configured in case it detects a short-circuit failure as an error in the simulation execution means and an error information output means for outputting the error information about the error.

A fault simulation apparatus according to a second aspect of the present invention is a fault simulation apparatus for detecting a fault state of a logic circuit by using circuit information in which gate functions of the logic circuit and mutual connection relationships are described. Wiring information extraction means for extracting predetermined wiring information from the
Open circuit fault occurrence that inputs the circuit information and the wiring information, and specifies on the circuit information the location in the logic circuit where the occurrence of the open fault is expected based on the comparison between the wiring information and a predetermined fault occurrence condition. In order to verify whether an open failure can be detected as an error by executing a failure simulation using the circuit information, assuming that an open failure has occurred in the location identifying means and the location identified by the open failure occurrence location identifying means. The failure simulation executing means and the failure error information output means for outputting error information related to the error when the open failure is detected as an error by the failure simulation executing means.

A failure simulation apparatus according to a third aspect of the present invention is a failure simulation apparatus for detecting a failure state of a logic circuit by using circuit information in which gate functions of the logic circuit and mutual connection relations are described. Short circuit failure based on a comparison between the circuit connection information and the wiring connection point information, and the wiring connection point information extraction means for extracting predetermined wiring connection point information from the circuit information and the predetermined failure occurrence condition. The short circuit fault occurrence point specifying means for specifying the point in the logic circuit where the occurrence of is expected on the circuit information, and the short circuit failure occurring at the point specified by the short circuit failure occurrence point specifying means, the circuit information A fault simulation executing means for performing a fault simulation using, and verifying whether the short-circuit fault can be detected as an error, When detecting a short-circuit failure as an error in the serial fault simulation execution means is configured to include a short-circuit failure error information output means for outputting the error information about the error.

A failure simulation apparatus according to a fourth aspect of the present invention is a failure simulation apparatus for detecting a failure state of a logic circuit by using circuit information in which gate functions of the logic circuit and mutual connection relationships are described. The wiring connection point information extracting means for extracting the predetermined wiring connection point information from the circuit, the circuit information and the wiring connection point information are input, and the open circuit failure is based on the comparison between the wiring connection point information and the predetermined failure occurrence condition. And an open fault occurrence location identifying means for identifying a location in the logic circuit in which the occurrence of is expected on the circuit information, and an open fault occurring at the location identified by the open failure occurrence location identifying means, the connection point Failure simulation executing means for executing a failure simulation using information, and verifying whether the open failure can be detected as an error. When detecting an open fault as an error in the fault simulation execution means is configured to include an open failure error information output means for outputting the error information about the error.

[0013]

The wiring information extracting means in the first aspect of the invention extracts predetermined wiring information from the layout data, for example, information relating to a short-circuit failure such as wiring interval and wiring distance.

Then, the short-circuit failure occurrence point specifying means specifies a point in the logic circuit where a short-circuit failure is expected to occur on the circuit information, based on a comparison between the wiring information and a predetermined failure occurrence condition. In other words, what part of the logic circuit is applicable to the short-circuit fault occurrence condition is recognized, and the circuit information of the logic circuit corresponding to that part is specified.

As described above, the wiring information extracting means and the short-circuit failure occurrence location identifying means identify the locations that meet the failure occurrence condition from the layout data, for example, the condition that the wiring interval is a predetermined value or less and the wiring distance is a predetermined value or more. It can be specified uniformly on the circuit information.

Then, the failure simulation executing means executes the failure simulation assuming that the short-circuit failure has occurred at the location specified by the short-circuit failure occurrence location identifying means,
It is possible to verify whether the short-circuit fault can be detected as an error by the output for the predetermined simulation pattern.

The wiring information extracting means in the second invention is
Predetermined wiring information, for example, information related to open circuit failure such as wiring width is extracted from the layout data.

Then, the open circuit failure occurrence point specifying means specifies, on the circuit information, the point in the logic circuit where the open circuit failure is expected to occur, based on the comparison between the wiring information and the predetermined failure occurrence condition. In other words, what part of the logic circuit is applicable to the open failure occurrence condition is recognized, and the circuit information of the logic circuit corresponding to that part is specified.

As described above, the wiring information extracting means and the open failure occurrence location identifying means uniformly uniformize the locations on the circuit information which meet the failure occurrence conditions from the layout data, for example, the condition that the wiring width is a predetermined value or less. Can be specified.

The failure simulation executing means executes the failure simulation assuming that the open failure has occurred at the location specified by the open failure occurrence location specifying means,
It is possible to verify whether or not the open failure can be detected as an error by the output for a predetermined simulation pattern.

The wiring connection point information extracting means in the third aspect of the invention extracts predetermined wiring connection point information from the layout data, for example, information relating to a short circuit fault of the wiring connection point such as the shape of the connection point.

Then, the short-circuit failure occurrence point identification means is based on a comparison between the wiring connection point information and a predetermined failure occurrence condition.
The location in the logic circuit where a short-circuit fault is expected to occur is specified on the circuit information. In other words, what part of the logic circuit is applicable to the short-circuit fault occurrence condition is recognized, and the circuit information of the logic circuit corresponding to that part is specified.

As described above, the wiring connection point information extracting means and the short-circuit failure occurrence point identifying means determine, on the circuit information, a failure condition from the layout data, for example, a point where the shape of the connection point is equal to or more than a predetermined value. Can be specified uniformly.

The failure simulation executing means is
It is possible to execute a failure simulation assuming that a short-circuit failure has occurred at the location specified by the short-circuit failure occurrence location identifying means, and verify whether or not the short-circuit failure can be detected as an error based on the output for a predetermined simulation pattern.

The wiring connection point information extracting means in the fourth aspect of the invention extracts predetermined wiring connection point information from the layout data, for example, information relating to open failure of the wiring connection point such as the shape of the connection point.

The open circuit failure occurrence location specifying means inputs the circuit information and the wiring connection point information, and based on the comparison between the wiring connection point information and a predetermined failure generation condition, a logic circuit in which an open circuit failure is expected to occur. The location inside is specified on the circuit information. In other words, what part of the logic circuit is applicable to the open failure occurrence condition is recognized, and the circuit information of the logic circuit corresponding to that part is specified.

As described above, the wiring connection point information extraction means and the open failure occurrence location specifying means uniformly match the failure occurrence condition from the layout data, for example, the location where the wiring width is equal to or less than a predetermined value on the circuit information. Specific.

The failure simulation executing means executes a failure simulation assuming that an open failure has occurred at the location identified by the open failure occurrence location identifying means, and whether or not the open failure can be detected as an error by the output for a predetermined simulation pattern. Can be verified.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIG. In FIG. 1, 1 is layout data in which information about arrangement and wiring of elements for creating a mask pattern of an integrated circuit expressed in a logic circuit diagram is described, and 2 is wiring interval, wiring distance and wiring based on the layout data 1. Wiring information extraction means for extracting type information, 3
Is a fault occurrence condition file that describes criteria for determining a short circuit fault with respect to the wiring interval, the wiring distance, and the wiring type, and 4 is the short circuit fault location based on the information extracted by the wiring information extracting means 2 and the fault occurrence condition file 3. Short circuit fault location specifying means 5 for identifying the short circuit fault occurrence location identifying means 4
A short-circuit fault simulation executing means for executing a fault simulation for the signal line specified by
Is a short circuit fault error information output means for outputting to the error information list 7 information relating to an error that occurred during execution of the short circuit fault simulation. Other parts having the same reference numerals as those in FIG. 7 are the same as or corresponding to the configuration of the prior art shown in FIG.

Next, the operation of the failure simulation device shown in FIG. 1 will be described.

First, the logic circuit information extracting means 9 extracts a netlist necessary for executing the fault simulation from the netlist of the logic circuit diagram file 8. In addition, the wiring information extraction means 2 uses the signal names from the layout data 1,
Wiring information regarding wiring intervals, wiring distances, and wiring types (metal, polysilicon, diffusion, well, etc.) is extracted. The short-circuit failure occurrence point identification means 4 inputs the conditions expected to cause a short-circuit failure from the failure occurrence condition file 3 set and inputted by the user in advance, and the wiring information and the netlist are respectively inputted to the wiring information extraction means 2 and the logic circuit. Input from the information extraction means 9.

Next, the short-circuit fault occurrence point identification means 4
It is judged whether the extracted wiring information satisfies the failure occurrence condition. For example, in the case of a certain wiring type (metal), it is determined whether the wiring distance Rd is a predetermined value X ₁ or less or the wiring distance Rl is a predetermined value X ₂ or more (Rd <X ₁ andR
l> X ₂ ). The short-circuit failure occurrence point identifying means 4 identifies a signal line satisfying the failure occurrence condition as a failure target signal line in the netlist and holds the information. The above work is performed until the information extracted by the wiring information extraction means 2 is completed.

The short-circuit fault simulation executing means 5 is
When a short-circuit failure has occurred in each signal line held by the short-circuit failure occurrence point identification means 4, a short-circuit failure simulation is executed, and if an output different from the expected value, that is, a failure error occurs, short-circuit failure error information output means The information is transmitted to 6. The short-circuit failure error information output means 6 is
The error information list 7 in which the information related to the error due to the short circuit failure is described is output. If the failure simulation has not been completed for all the signal lines held by the short-circuit failure occurrence point identification means 4, the above operation is repeated until it is completed.

When the failure simulation is performed as described above, the simulation can be executed without omission for all the wirings that meet the failure occurrence conditions.

In the above embodiment, as the wiring information,
Although the wiring interval, the wiring distance, and the wiring type are used, any one or two of them may be used, and other elements may be used, and the same effect as that of the above-described embodiment is obtained.

Further, in the above embodiment, the wiring interval and the wiring distance are judged independently, but the judgment is made by establishing a conditional expression using the wiring information as a parameter in consideration of the interaction of the wiring information such as the wiring interval and the wiring distance. It may be used as a reference.

Next, a second embodiment of the present invention will be described with reference to FIG.
Will be explained. In FIG. 2, reference numeral 2a is a wiring information extracting means for extracting information on the wiring width based on the layout data 1, 3a is a failure occurrence condition file describing criteria for judging an open failure with respect to the wiring width, and 4a is wiring information extraction. The open failure occurrence point specifying means 5 for specifying the open failure point based on the information extracted by the means 2a and the failure occurrence condition file 3a executes the failure simulation for the signal line specified by the open failure occurrence point specifying means 4a. The open-failure simulation executing means 6a is an open-failure error information output means for outputting information relating to an error occurring during execution of the open-failure simulation to the error information list 7a. In addition, other parts having the same reference numerals as those in FIG. 1 are the same or corresponding parts as those shown in FIG.

Next, the operation will be described. The operation of the failure simulation device shown in FIG. 2 will be described.

First, the logic circuit information extracting means 9 extracts a netlist necessary for executing the fault simulation from the netlist of the logic circuit diagram file 8. Further, the wiring information extracting means 2 a extracts wiring information regarding the signal name and the wiring width from the layout data 1. The open fault occurrence location specifying means 4a inputs the conditions expected to cause the open fault from the fault occurrence condition file 3a set and inputted by the user in advance, and the wiring information and the netlist are respectively inputted to the wiring information extracting means 2a and the logic circuit. Input from the information extraction means 9.

Next, the open failure occurrence location specifying means 4a
Determines whether the extracted wiring information satisfies the failure occurrence condition. For example, it is determined whether the wiring width Rw is a predetermined value X ₃ or less (Rw <X ₃ ). The open failure occurrence location identifying unit 4a holds information for identifying a signal line satisfying the failure occurrence condition as a failure target signal line in the netlist. The above work is performed until the information extracted by the wiring information extraction means 2a is completed.

Open failure simulation executing means 5a
Performs an open-circuit failure simulation assuming that an open-circuit failure has occurred in each of the signal lines held by the open-circuit failure occurrence point identification means 4a, and outputs different from the expected value, that is, open-circuit failure error information. The information is transmitted to the output means 6a. The open failure error information output means 6a outputs an error information list 7a in which information related to errors due to an open failure is described.

If the failure simulation has not been completed for all the signal lines held by the open failure occurrence location specifying means 4, the above operation is repeated until it is completed.

In the above embodiment, as the wiring information,
Although the wiring width is used, the wiring type or the like may be taken into consideration as another element, and any one or two of those elements may be used, and the same effect as that of the above embodiment is obtained.

Further, in the above-mentioned embodiment, the judgment is made based on the wiring width, but it is also possible to make a judgment criterion by establishing a conditional expression using the wiring information as a parameter in consideration of the interaction between the wiring width and other elements.

Next, a procedure for realizing the failure simulation apparatus shown in the first or second embodiment by using a computer will be described. FIG. 3 is a flowchart showing the procedure. When started, first, a failure simulation execution netlist is extracted from the netlist of the entire logic circuit (step ST1). Next, the wiring information is extracted from the layout data (step ST
2). The failure occurrence condition set and input by the user is input (step ST3). It is determined whether the wiring information extracted in step ST2 satisfies the failure occurrence condition input in step ST3 (step ST4). If the condition is satisfied, the information is held as the target signal line of the failure simulation (step ST5). If the extraction information has not been completed, the process is repeated from step ST2 (step ST6). A failure simulation is performed on the held signal line (step ST7), and when a failure error occurs (step ST8), it is output as an error information list 7 (step ST9). If the failure simulation is not completed, step ST7
From step ST10, and when it is finished, the failure simulation is finished (step ST1).
1).

In the first embodiment, the wiring information such as the wiring interval and the wiring distance is extracted from the layout data 1,
The case where the short circuit fault is detected by executing the fault simulation is shown.
Information such as wiring connection points such as through holes may be extracted and short-circuit failure simulation may be executed to detect the short-circuit failure. The configuration of the failure simulation device in that case is shown in FIG.
Shown in. In FIG. 4, 2b is a wiring connection information extracting means for extracting the wiring connection information of the connection points such as contacts and through holes based on the layout data 1, and 3b is the shape and connection type (metal, polysilicon, diffusion, well) of the connection points. Etc.), a fault occurrence condition file that describes criteria for determining that a short circuit fault will occur, 4b is a short circuit fault based on the information extracted by the wiring connection information extracting means 2b and the fault occurrence condition described in the fault occurrence condition file 3b. A short-circuit failure occurrence point specifying means for specifying a point, 7b is an error information list output from the short-circuit failure error information output means 6. In addition, other parts having the same reference numerals as those in FIG. 1 are the same or corresponding parts as those shown in FIG.

Also in the above embodiment, the failure occurrence condition is set appropriately according to the case.

In the second embodiment, the wiring information such as the wiring interval and the wiring distance is extracted from the layout data 1,
The case where the open failure is detected by executing the failure simulation is shown.
Information such as wiring connection points such as through-holes may be extracted and open-circuit failure simulation may be executed to detect the open-circuit failure. The configuration of the failure simulation device in that case is shown in FIG.
Shown in. In FIG. 5, 2c is a wiring connection information extracting means for extracting the wiring connection information of the connection points such as contacts and through holes based on the layout data 1, and 3c is the shape and connection type of the connection points (metal, polysilicon, diffusion, well). Etc.), a fault occurrence condition file describing criteria for judging that an open fault occurs 4c indicates an open fault based on the information extracted by the wiring connection information extracting means 2c and the fault occurrence condition described in the fault occurrence condition file 3c. An open-fault occurrence location identification means 7c for identifying a location is an error information list output from the open-fault error information output means 6a. Note that other parts having the same reference numerals as those in FIG. 2 are the same or corresponding parts as those shown in FIG.

Also in the above embodiment, the failure occurrence condition is appropriately set depending on the case.

FIG. 6 shows a procedure for identifying a failure occurrence location using the wiring connection information and implementing the failure simulation on a computer.

In each of the above-described embodiments, the case where the errors are sequentially output has been described, but they may be collectively output at the end of the failure simulation.

In each of the above-mentioned embodiments, the case where the failure simulation execution netlist is extracted from the logic circuit diagram file 8 may be extracted from the layout data 1, and the same effect as that of the above-described embodiments is obtained. Play.

[0053]

As described above, according to the failure simulation apparatus of the first aspect of the present invention, the wiring information extracting means for extracting the predetermined wiring information from the layout data, the circuit information and the wiring information are input, and wiring is performed. Based on a comparison between the information and a predetermined failure occurrence condition, a short circuit failure occurrence point specifying means for specifying a point in the logic circuit where a short circuit failure is expected to occur on the circuit information is configured, so that the layout In addition to automatically identifying the signal line that can cause a short-circuit fault from the data based on the short-circuit fault occurrence condition, it is possible to perform a fault simulation on the identified signal line and prevent input errors in the target signal line of the fault simulation. The advantage is that the time required for short-circuit failure simulation including execution preparation can be shortened.

According to the failure simulation apparatus of the second aspect of the invention, the wiring information extracting means for extracting the predetermined wiring information from the layout data, the circuit information and the wiring information are input, and the wiring information and the predetermined failure occurrence condition are input. On the basis of the comparison with the above, the open fault occurrence location identifying means for identifying the location in the logic circuit where the open failure is expected to occur on the circuit information is configured. The signal line to be obtained is automatically specified based on the open fault occurrence condition, and the failure simulation can be executed for the specified signal line to prevent the input error of the target signal line of the fault simulation and open fault including execution preparation. This has the effect of reducing the time required for simulation.

According to the failure simulation apparatus of the third aspect of the present invention, the wiring connection point information extracting means for extracting the predetermined wiring connection point information from the layout data and the circuit information and the wiring connection point information are input to perform the wiring connection. Based on the comparison between the point information and the predetermined failure occurrence condition, the short-circuit failure occurrence location specifying means for specifying the location in the logic circuit where the occurrence of the short-circuit failure is expected on the circuit information is configured, In addition to automatically identifying wiring connection points that may cause short-circuit faults from layout data based on short-circuit fault occurrence conditions,
There is an effect that a failure simulation can be executed for the specified wiring connection point, an input error of the target connection point of the failure simulation can be prevented, and a time required for a short-circuit failure simulation including execution preparation can be shortened.

According to the failure simulation apparatus of the fourth aspect of the present invention, the wiring connection point information extracting means for extracting the predetermined wiring connection point information from the layout data and the circuit information and the wiring connection point information are input to perform the wiring connection. Based on the comparison between the point information and a predetermined failure occurrence condition, the open failure occurrence point specifying means for specifying the point in the logic circuit where the occurrence of the open failure is expected on the circuit information is configured, Connection points where open failures can occur are automatically specified from layout data based on open failure occurrence conditions, and failure simulation can be executed for the specified connection points to prevent input mistakes at the target connection points for failure simulation. At the same time, there is an effect that the time required for the open failure simulation including the preparation for execution can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a failure simulation device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a failure simulation device according to a second embodiment of the present invention.

FIG. 3 is a flowchart showing a procedure for realizing a failure simulation device according to the first or second embodiment of the present invention using a computer.

FIG. 4 is a block diagram showing a configuration of a failure simulation device according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a failure simulation device according to a fourth embodiment of the present invention.

FIG. 6 is a flowchart showing a procedure for realizing a failure simulation device according to a third or a fourth embodiment of the present invention using a computer.

FIG. 7 is a block diagram showing a configuration of a conventional failure simulation device.

[Explanation of symbols]

 1 Layout Data 2 Wiring Information Extracting Means 3, 3a to 3c Fault Occurrence Condition File 4, 4b Short Circuit Fault Occurrence Location Identifying Means 4a, 4c Open Fault Occurrence Location Identifying Means 5, 5b Short Circuit Fault Simulation Execution Means 5a, 5c Open Fault Simulation Execution Means 6 Short-circuit failure error information output means 6a Open failure error information output means 7, 7a to 7c Error information list 8 Logic circuit diagram file 9 Logic circuit information extraction means

Claims (4)

[Claims] 1. A wiring simulator for extracting predetermined wiring information from layout data in a failure simulation device for detecting a failure state of a logic circuit by using circuit information describing a gate function of the logic circuit and mutual connection relationship. Means for inputting the circuit information and the wiring information, and based on a comparison between the wiring information and a predetermined failure occurrence condition, a location in the logic circuit where a short circuit failure is expected to occur is specified on the circuit information. Short-circuit failure occurrence point specifying means, and if a short-circuit failure occurs in the point specified by the short-circuit failure occurrence point specifying means, execute a failure simulation using the circuit information, whether the short-circuit failure can be detected as an error. Fault simulation executing means for verification, and the short circuit fault is detected as an error by the fault simulation executing means. And an error information output means for outputting the error information about the error in case, fault simulation apparatus. 2. A wiring simulator for extracting predetermined wiring information from layout data in a failure simulation device for detecting a failure state of the logic circuit by using circuit information describing the gate function of the logic circuit and mutual connection relationship. Means for inputting the circuit information and the wiring information, and based on a comparison between the wiring information and a predetermined failure occurrence condition, a location in the logic circuit where an open failure is expected to occur is specified on the circuit information. Open fault occurrence location identifying means, and if the open failure occurs in the location identified by the open failure occurrence location identifying means, execute a fault simulation using the circuit information, and determine whether the open fault can be detected as an error. Fault simulation executing means for verification, and the open fault is detected as an error by the fault simulation executing means. The case, and a failure error information output means for outputting the error information about the error, fault simulation apparatus. 3. A fault simulating device for detecting a fault state of a logic circuit by using circuit information describing a gate function of the logic circuit and mutual connection relation, and wiring for extracting predetermined wiring connection point information from layout data. Connection point information extraction means, input the circuit information and the wiring connection point information, based on the comparison between the wiring connection point information and a predetermined failure occurrence condition,
A short-circuit fault occurrence point identifying means for identifying a location in the logic circuit where a short-circuit failure is expected to occur on the circuit information, and a short-circuit fault occurring at the location specified by the short-circuit fault occurrence point identifying means, A fault simulation executing means for executing a fault simulation using circuit information and verifying whether the short-circuit fault can be detected as an error, and a short-circuit fault detected by the fault simulation executing means as an error, A fault simulation device comprising: a short-circuit fault error information output unit that outputs error information. 4. A fault simulating device for detecting a fault state of a logic circuit by using circuit information describing a gate function of the logic circuit and mutual connection relation, and wiring for extracting predetermined wiring connection point information from layout data. Connection point information extraction means, input the circuit information and the wiring connection point information, based on the comparison between the wiring connection point information and a predetermined failure occurrence condition,
An open-fault occurrence location identifying means for identifying a location in the logic circuit where an open-fault is expected to occur on the circuit information; and an open failure occurring at the location identified by the open-fault occurrence location identifying means, A failure simulation using the connection point information is executed, and a failure simulation executing means for verifying whether the open failure can be detected as an error; and when the open failure is detected as an error by the failure simulation executing means, the error And an open failure error information output means for outputting error information regarding the failure simulation apparatus.