JP3152205B2 - Logic simulation apparatus and method, and recording medium recording control program therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation apparatus and method, and a recording medium on which a control program is recorded. The present invention relates to a logic simulation device for detecting.

[0002]

2. Description of the Related Art Conventionally, in a logic simulator of this kind, an OS (Operat) is used by a logic simulator.
Executing a logic simulation of the device model using the ING System, creating a correct value of the logic simulation with the instruction level simulator, and comparing the execution results of the logic simulator and the instruction level simulator to verify the device model. I have.

[0003] That is, the above logic simulator, as shown in FIG.
, A comparison instruction unit 52, a simulation result output unit 53, a logic simulation execution unit 54, and an instruction level simulation result storage unit 55.

The simulation result comparing means 51 of the logic simulator 5 comprises a logic simulation executing means 5
4 is compared with the value held in the instruction level simulation result storage means 55.

[0005] The comparison instruction means 52 generates a comparison timing for the simulation result comparison means 51. When the simulation result output means 53 receives the comparison result indicating that there is a mismatch from the simulation result comparison means 51, the simulation result internal state history and the instruction level simulation result from the logic simulation execution means 54 are output to the simulation result output file 7. Output.

The logic simulation execution means 54 executes a logic simulation. The instruction level simulation result storage unit 55 stores an instruction level simulation result generated by the instruction level simulator 6 that performs a simulation at the instruction set level. The above logic simulator is disclosed in Japanese Patent Application Laid-Open No. 7-36332.

[0007]

In the conventional logic simulation method described above, the logic simulator and the instruction level are not used.
Device simulator is working properly,
From input / output devices connected to the model
Executable instruction sequence due to difference in synchronous interrupt generation timing
Differences in execution results make it difficult to compare execution results.
There is a title.

In the above-described logic simulation method, if an error is detected by comparing the execution results of the logic simulator and the instruction level simulator, it is difficult to determine the location where the error has occurred.

Accordingly, an object of the present invention is to provide a logic simulation apparatus and method capable of solving the above problems and improving the logic verification efficiency and the error analysis efficiency, and a recording medium recording a control program therefor. It is in.

[0010]

According to the logic simulation apparatus of the present invention, at least the input / output device has its own system.
Logic simulation of the device model connected to
A logic simulation apparatus for executing in a simulator, creating a correct answer value of the logic simulation in an instruction level simulator, and verifying the device model by comparing execution results of the logic simulator and the instruction level simulator, From the input / output device
Means for eliminating the difference between the instruction sequence of the logic simulator and the instruction sequence of the instruction level simulator caused by the difference in the timing of the occurrence of the asynchronous interrupt.
I have .

In another logic simulation apparatus according to the present invention, at least an input / output device is connected to its own system.
Logic simulator for device model logic simulation
A logic simulation device that executes the simulation with an instruction level simulator, creates a correct answer value of the logic simulation, and compares the execution results of the logic simulator and the instruction level simulator to verify the device model. First detecting means provided in and included in the logic simulator for detecting occurrence of an asynchronous interrupt from the input / output device during execution of the logic simulation by the logic simulator; A second detecting means for detecting an execution instruction sequence; and an asynchronous interrupt generation timing provided in the instruction level simulator and detected by the first detecting means. so Matching means for matching the timing of occurrence of the asynchronous interrupt; and said detecting means provided in the instruction level simulator and detecting a mismatch between the execution instruction string detected by the second detection means and the execution instruction string in the instruction level simulator. Comparing means for terminating the instruction level simulation.

A logic simulation method according to the present invention provides a logic simulator for executing a logic simulation of a device model in which at least an input / output device is connected to its own system, and an instruction level for creating a correct answer value of the logic simulation. A logic simulation method for verifying the device model using a simulator and a logic simulation device including means for comparing the execution result of the logic simulator and the execution result of the instruction level simulator, wherein Generation of asynchronous interrupt
A step of eliminating a difference between an execution instruction sequence of the logic simulator and an execution instruction sequence of the instruction level simulator caused by a difference in timing .

Another logic simulation method according to the present invention provides a logic simulator for executing a logic simulation of a device model in which at least an input / output device is connected to its own system, and an instruction for creating a correct answer value of the logic simulation. A logic simulation method for verifying the device model using a logic simulator including a level simulator and means for comparing an execution result of the logic simulator with an execution result of the instruction level simulator, wherein the logic simulator includes: Before executing the logic simulation by the logic simulator.
First to detect occurrence of asynchronous interrupt from entry / output device
And a second step of detecting an execution instruction sequence of a logic simulation by the logic simulator in the logic simulator; and the instruction level simulator based on the asynchronous interrupt detected in the first step in the instruction level simulator. A third step of matching the asynchronous interrupt generation timing in the logic simulator with the asynchronous interrupt generation timing in the logic simulator; and executing the instruction sequence detected by the second detection means in the instruction level simulator and the execution instruction sequence in the instruction level simulator. A fourth step of terminating the instruction level simulation when a mismatch with the execution instruction sequence is detected.

A recording medium on which a logic simulation control program according to the present invention is recorded has at least an input / output device
Simulation of equipment model connected to own system
Execution in a logic simulator, an instruction level simulator creates the correct value of the logic simulation,
Wherein a recording medium storing a logic simulation control program logic simulation apparatus for verifying the device model by comparing the execution result of the logic simulator and the instruction level simulator, the logic simulation control program the logic simulation
The logic device detects the occurrence of an asynchronous interrupt from the input / output device during execution of a logic simulation by the logic simulator, detects an execution instruction sequence of the logic simulation by the logic simulator, and detects the asynchronous interrupt detected by the logic simulator. The asynchronous interrupt generation timing in the instruction level simulator is matched with the asynchronous interrupt generation timing in the logic simulator based on the above, so that the execution instruction sequence detected by the logic simulator does not match the execution instruction sequence in the instruction level simulator. Is detected, the instruction level simulation is terminated.

That is, the logic simulation apparatus of the present invention uses an OS (Operating) in a logic simulator.
When a device model is verified by executing a logic simulation of the device model using System, creating a correct answer value of the logic simulation with an instruction level simulator, and comparing the execution results of the logic simulator and the instruction level simulator, Even if both the logic simulator and the instruction level simulator are operating correctly, the difference in the execution instruction sequence caused by the difference in the timing of the generation of the asynchronous interrupt from the input / output device connected to the system of the device model is eliminated and the execution is performed. This facilitates comparison of the results.

More specifically, a logic simulation device executes a logic simulation of a device model using an OS by a logic simulator. At this time, the asynchronous interrupt information recording unit detects the occurrence of an asynchronous interrupt from an input / output device or the like, and records it in the asynchronous interrupt information storage unit. The execution instruction sequence recording unit detects the execution instruction sequence and records it in the execution instruction sequence storage unit. Subsequently, an instruction level simulation is executed by the instruction level simulator to create a correct answer value for the logic simulation.

At this time, the asynchronous interrupt information matching unit refers to the asynchronous interrupt information storage unit, and matches the asynchronous interrupt generation timing in the instruction level simulator with the asynchronous interrupt generation timing in the logic simulator, thereby obtaining the asynchronous interrupt generation timing. The difference in the execution instruction sequence between the logic simulator and the instruction level simulator caused by the difference is eliminated.

Further, the execution instruction sequence comparison section compares the execution instruction sequence in the logic simulator with the execution instruction sequence in the instruction level simulator. If the two do not match, it is determined that an error has been detected and the instruction level simulation ends. . If the execution instruction sequence in the logic simulator and the execution instruction sequence in the instruction level simulator all match, the execution result in the logic simulator is assumed to be correct.

Thus, since the same instruction sequence is executed by the logic simulator and the instruction level simulator, the execution results can be easily compared, and the logic verification efficiency can be improved. Further, when an error is detected by comparing the execution results, it is easy to determine the location where the error has occurred, so that the error analysis efficiency can be improved.

[0020]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a logic simulation apparatus according to one embodiment of the present invention. Referring to FIG. 1, a logic simulation apparatus according to one embodiment of the present invention includes a logic simulator 1 for executing a logic simulation, an asynchronous interrupt information storage unit 2 for holding asynchronous interrupt information generated from an input / output device or the like during the logic simulation, An execution instruction string storage unit 3 for holding an instruction string executed during a simulation, and an instruction level simulator 4 for executing an instruction level simulation
It is composed of

The logic simulator 1 comprises a logic simulation execution unit 11, an asynchronous interrupt information recording unit 12, and an execution instruction sequence recording unit 13. The logic simulation execution unit 11 executes a logic simulation of the device model using the OS. Asynchronous interrupt information recording unit 1
Numeral 2 records an asynchronous interrupt generated from an input / output device or the like during the logic simulation in the asynchronous interrupt information storage unit 2. The execution instruction sequence recording unit 13 records the execution instruction sequence executed during the logic simulation in the execution instruction sequence storage unit 3.

The instruction level simulator 4 includes an asynchronous interrupt information matching unit 41, an execution instruction sequence comparing unit 42, and an instruction level simulation executing unit 43.
The asynchronous interrupt information matching unit 41 refers to the asynchronous interrupt information storage unit 2 and matches the asynchronous interrupt generation timing in the logic simulator 1 with the asynchronous interrupt generation timing in the instruction level simulator 4.

The execution instruction sequence comparison unit 42 refers to the execution instruction sequence storage unit 3 and compares the execution instruction sequence in the logic simulator 1 with the execution instruction sequence in the instruction level simulator 4. And the instruction level simulation is terminated. The instruction level simulation execution unit 43 executes an instruction level simulation.

FIG. 2 is a flowchart showing a logic simulation operation by the logic simulator 1 of FIG.
FIG. 3 is a flowchart showing an instruction level simulation operation by the instruction level simulator 4.

The operation of the logic simulation apparatus according to one embodiment of the present invention will be described with reference to FIGS. Here, the processing operations shown in FIGS. 2 and 3 are realized by the logic simulator 1 and the instruction level simulator 4 executing a program stored in a control memory (not shown), and the control memory is a ROM (read only memory). Or an IC (integrated circuit) memory, a floppy disk, or the like.

First, a logic simulation is performed by the logic simulator 1. The logic simulation execution unit 11 executes one clock of the logic simulation of the device model using the OS as a test case (step S1 in FIG. 2).
Here, it is assumed that the logic simulation execution unit 11 performs a logic simulation at the gate level.

The asynchronous interrupt information recording unit 12 checks whether an asynchronous interrupt has occurred at the clock (step S2 in FIG. 2). If the asynchronous interrupt information has been generated, the asynchronous interrupt information including the execution instruction of the interrupt destination is output to the asynchronous interrupt information storage unit 2 (step S3 in FIG. 2).

The execution instruction sequence recording unit 13 outputs 1
It is checked whether the execution of the instruction has been completed (step S in FIG. 2).
4). Executing one instruction in the logic simulator 1 requires several clocks to several tens of clocks. If the execution of one instruction has been completed, the instruction is output to the execution instruction string storage unit 3 (step S5 in FIG. 2).

The logic simulator 1 repeats the above-described operation to advance the logic simulation. When the logic simulation is executed for all the instructions in the test case (step S6 in FIG. 2), the logic simulation ends.

On the other hand, the instruction level simulator 4 executes an instruction level simulation for a test case equivalent to that of the logic simulator 1 and creates a correct value of the logic simulation in the logic simulator 1 and compares the execution results.

First, the asynchronous interrupt information matching unit 41 refers to the asynchronous interrupt information storage unit 2 and checks whether the asynchronous interrupt accompanying the next execution instruction has occurred during the logic simulation in the logic simulator 1 (step in FIG. 3). S1
1).

When an asynchronous interrupt occurs, a branch of an execution instruction sequence occurs. Therefore, if the asynchronous interrupt generation timing is different, the subsequent execution instruction sequence will be different. By matching the asynchronous interrupt generation timing in the logic simulator 1 with the asynchronous interrupt generation timing in the instruction level simulator 4, the execution instruction sequences of the logic simulator 1 and the instruction level simulator 4 are matched.

When an asynchronous interrupt for branching the next execution instruction has occurred in the logic simulator 1, first, it is checked whether any pending asynchronous interrupt matches the asynchronous interrupt generated in the logic simulator 1 (FIG. 7). 3 steps S12).

If there is a match with the pending asynchronous interrupt, the pending asynchronous interrupt is released (FIG. 3).
Step S13). On the other hand, when there is no match with the pending asynchronous interrupt, or when there is no match with the pending asynchronous interrupt, the process waits until the asynchronous interrupt is generated (step S1 in FIG. 3).
4). Thereafter, the asynchronous interrupt acquired by the above processing is accepted, and the next execution instruction is branched (step S15 in FIG. 3).

The execution instruction sequence comparison unit 42 refers to the execution instruction sequence storage unit 3 and checks whether the next execution instruction in the logic simulator 1 matches the next execution instruction in the instruction level simulator 4 (FIG. 3). Step S16). If the next execution instruction does not match, an error may be present in the execution result of the logic simulator 1 due to an incorrect device model. Therefore, the execution instruction or the like in which the error occurred is reported (FIG. 3).
Step S20), end the instruction level simulation.

If the next execution instructions match, the instruction level simulation execution unit 43 executes one instruction level simulation (step S17 in FIG. 3). here,
If an asynchronous interrupt has occurred, the asynchronous interrupt is not immediately accepted and held (step S18 in FIG. 3).

The instruction level simulator 4 repeats the above-described operation to advance the instruction level simulation. When the instruction level simulation is executed for all the instructions in the test case (step S19 in FIG. 3), the instruction level simulation ends.

When the execution instruction sequence in the logic simulator 1 and the execution instruction sequence in the instruction level simulator 4 all match, it is assumed that the execution result in the logic simulator 1 is correct, that is, the device model is correct.

As described above, by executing the same instruction sequence in the logic simulator 1 and the instruction level simulator 4, it is possible to easily compare the execution results and improve the logic verification efficiency.

When an error is detected by comparing the execution results of the logic simulator 1 and the instruction level simulator 4, the same instruction sequence is executed by the logic simulator 1 and the instruction level simulator 4. And the error analysis efficiency can be improved.

[0041]

As described above, according to the present invention, a logic simulation of a device model is executed by a logic simulator, a correct value of the logic simulation is created by an instruction level simulator, and the execution of the logic simulator and the instruction level simulator is executed. In a logic simulation device that verifies the device model by comparing the results,
Eliminating the difference between the instruction sequence of the logic simulator and the instruction sequence of the instruction level simulator due to the difference in the timing of the occurrence of the asynchronous interrupt has the effect of improving the logic verification efficiency and the error analysis efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a logic simulation apparatus according to one embodiment of the present invention.

FIG. 2 is a flowchart showing a logic simulation operation by the logic simulator of FIG. 1;

FIG. 3 is a flowchart showing an instruction level simulation operation by the instruction level simulator.

FIG. 4 is a block diagram showing a configuration of a conventional logic simulation apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Logic simulator 2 Asynchronous interrupt information storage part 3 Execution instruction string storage part 4 Instruction level simulator 11 Logic simulation execution part 12 Asynchronous interrupt information recording part 13 Execution instruction string recording part 41 Asynchronous interrupt information matching part 42 Execution instruction string comparison part 43 Instruction Level simulation execution unit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-31968 (JP, A) JP-A-1-209542 (JP, A) JP-A-3-33941 (JP, A) JP-A-7- 36732 (JP, A) JP-A-7-182202 (JP, A) JP-A-8-110919 (JP, A) JP-A-8-180080 (JP, A) JP-A 8-287123 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 17/50 662-674

Claims (8)

(57) [Claims] At least an input / output device is connected to its own system.
Logic simulation of the equipment model
A logic simulator for executing the logic simulator, creating a correct answer value of the logic simulation with an instruction level simulator, and comparing the execution results of the logic simulator and the instruction level simulator to verify the device model, Asynchronous from the input / output device
A logic simulation apparatus comprising means for eliminating a difference between an execution instruction sequence of the logic simulator and an execution instruction sequence of the instruction level simulator caused by a difference in generation timing of a period interrupt . 2. An apparatus wherein at least an input / output device is connected to its own system.
Logic simulation of the equipment model
A logic simulator for executing the logic simulator, creating a correct answer value of the logic simulation with an instruction level simulator, and comparing the execution results of the logic simulator and the instruction level simulator to verify the device model, First detecting means provided in and included in the logic simulator for detecting occurrence of an asynchronous interrupt from the input / output device during execution of the logic simulation by the logic simulator; and logic simulation provided in the logic simulator and performed by the logic simulator. A second detecting means for detecting an execution instruction string of the instruction level simulator, and an asynchronous interrupt occurrence timing in the instruction level simulator based on the asynchronous interrupt detected in the instruction level simulator and detected by the first detecting means. Sim A matching means for matching the asynchronous interrupt occurrence timing in the instruction level simulator, and a mismatch between the execution instruction string provided in the instruction level simulator and detected by the second detection means and the execution instruction string in the instruction level simulator. A logic means for ending the instruction level simulation upon detection. 3. An asynchronous interrupt information storage unit for recording occurrence of the asynchronous interrupt detected by the first detection unit, and an execution instruction sequence storage for recording an execution instruction sequence detected by the second detection unit. Means for matching the asynchronous interrupt occurrence timing in the instruction level simulator with the asynchronous interrupt occurrence timing in the logic simulator with reference to the storage contents of the asynchronous interrupt information storage means, and wherein the comparing means The instruction level simulation is terminated when a mismatch between the execution instruction sequence detected by the second detection unit and the execution instruction sequence in the instruction level simulator is detected with reference to the storage contents of the execution instruction sequence storage unit. 3. The logic simulation apparatus according to claim 2, wherein: 4. An input / output device connected to at least an own system.
A logic simulator for performing logic simulation apparatus models continue, the instruction level simulator to create a correct value for the logic simulation, and means for comparing the execution result of the logic simulator execution result and the instruction level simulator Including logic simulation
A logic simulation method for verifying the device model using a device, comprising:
A logic simulation method comprising the step of eliminating a difference between an execution instruction sequence of the logic simulator and an execution instruction sequence of the instruction level simulator, which is caused by a difference in occurrence timing of the indentation . 5. An apparatus wherein at least an input / output device is connected to the own system.
A logic simulator for performing logic simulation apparatus models continue, the instruction level simulator to create a correct value for the logic simulation, and means for comparing the execution result of the logic simulator execution result and the instruction level simulator Including logic simulation
A logic simulation method for verifying the device model using a device, comprising: a first step of detecting occurrence of an asynchronous interrupt from the input / output device during execution of a logic simulation by the logic simulator in the logic simulator; A second step of detecting an execution instruction sequence of a logic simulation by the logic simulator in the logic simulator; and an asynchronous interrupt in the instruction level simulator based on the asynchronous interrupt detected in the first step in the instruction level simulator. A third step of matching an occurrence timing with an asynchronous interrupt occurrence timing in the logic simulator; and executing the instruction sequence detected by the second detection means in the instruction level simulator and executing the instruction sequence in the instruction level simulator. Logic simulation method characterized by a fourth step of terminating the instruction level simulation when detecting a mismatch between the decree column. 6. An asynchronous interrupt information storage unit for recording occurrence of the asynchronous interrupt detected by the first detection unit, and an execution instruction sequence storage for recording an execution instruction sequence detected by the second detection unit. Means for making the asynchronous interrupt occurrence timing in the instruction level simulator coincide with the asynchronous interrupt occurrence timing in the logic simulator by referring to the storage contents of the asynchronous interrupt information storage means in the third step. In a step 4, when the discrepancy between the execution instruction sequence detected by the second detection means and the execution instruction sequence in the instruction level simulator is detected with reference to the storage contents of the execution instruction sequence storage means, 6. The logic simulation method according to claim 5, wherein the simulation is terminated. 7. An input / output device connected to at least an own system.
Logic simulation of the equipment model
Run in Regulator, wherein to create the correct value of the logic simulation, the logic simulation control logic simulation apparatus for verifying the device model by comparing the execution result of the logic simulator and the instruction level simulator at the instruction level simulator A recording medium on which a program is recorded, wherein the logical simulation control program is the logical system.
Causing the simulation device to detect occurrence of an asynchronous interrupt from the input / output device during execution of a logic simulation by the logic simulator, to detect an instruction sequence of the logic simulation by the logic simulator, Based on the asynchronous interrupt detected in the above, the asynchronous interrupt generation timing in the instruction level simulator is matched with the asynchronous interrupt generation timing in the logic simulator, and the execution instruction string detected in the logic simulator and the instruction level simulator A recording medium storing a logic simulation control program, wherein the instruction level simulation is terminated when a mismatch with an execution instruction sequence is detected. 8. A logic simulation comprising: an asynchronous interrupt information storage means for recording occurrence of the asynchronous interrupt detected by the logic simulator; and an execution instruction string storage means for recording an execution instruction string detected by the logic simulator. apparatus wherein the said logic simulation control program the logic sheet
The simulation device refers to the storage contents of the asynchronous interrupt information storage means to match the asynchronous interrupt generation timing in the instruction level simulator with the asynchronous interrupt generation timing in the logic simulator, and stores the execution instruction string storage means 8. The logic according to claim 7, wherein the instruction level simulation is terminated when a mismatch between an execution instruction sequence detected by the logic simulator and an execution instruction sequence by the instruction level simulator is detected with reference to contents. A recording medium on which a simulation control program is recorded.