JP2001051864A - Test conducting system for data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To analyze the cause of an error if the execution of a test instruction sequence is stopped due to a processor logic defect or if an infinite loop is entered and no execution result is obtained. SOLUTION: This test conducting system has a test environment setting process 101, an instruction emulator 102 which generates an expected value, a test instruction sequence execution control process 103, a result comparing result 104, and a fault factor specifying process 105, and an instruction and an object function which cause a fault are found out to investigate the fault factor if the expected value generated by the instruction simulation of the test instruction sequence becomes discrepant with the execution result of the test instruction sequence on a data testing device or, if the execution of the test instruction sequence is stopped due to the fault resulting from a processor logic defect, or if an infinite loop is entered and no execution result is obtained, thereby evading the occurrence of a fault caused by the same defect factor in the subsequent execution of a test program.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a data processing apparatus, and more particularly to a method for continuously executing a large amount of test programs and testing a data processing apparatus under test.

[0002]

2. Description of the Related Art In a method of executing a test program in a data processing device, a combination of pipeline processing of test instruction sequences and complicated instruction operations causes an operation under a condition where a heavy load is applied to the data processing device to cause a failure. If it occurs or operates unexpectedly, the test instruction string being executed will generate an illegal interrupt, an infinite loop or an execution result value of an abnormal value,
If it does not operate normally, the instruction and target function that caused the failure at the test program level are found manually, and the cause of the error is analyzed. Execution was suppressed.

Japanese Patent Application No. 6-282599 discloses that when a test program is executed on a data processing device, an arbitrary section in the test instruction sequence that does not operate normally is not executed on the data processing device under test. Discloses a method of testing only a normally operable instruction sequence using means for setting an initial value and an expected value at an arbitrary point in order to execute the instruction on an instruction interpreter.

[0004]

In the prior art, the test program has a large number of similar test instruction sequences, and there is a possibility that a fault that has occurred in the past may repeatedly occur. Therefore, execution of a similar test instruction sequence results in frequent occurrence of failures of the same factor.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and execute a test instruction sequence which may cause a failure.
In the test instruction sequence, all test instruction sequences including any section that does not operate normally follow the failure avoidance measures to avoid the same defect,
An object of the present invention is to provide a more efficient and accurate test method for a data processing device.

[0006]

In order to achieve the above object,
Run a large amount of test programs on the data processing device,
A method for testing a data processing device includes a test environment setting process, an instruction simulator for generating expected values, a test instruction sequence execution control process, a result comparison process, and a failure factor identification process, and a test instruction sequence is generated by the instruction simulator. If a mismatch is found in the comparison between the expected value obtained and the execution result of the test instruction sequence on the data test apparatus, or the test instruction sequence is executed due to a failure due to a logic failure in the data processing device during the execution of the test instruction sequence. If execution is suppressed or an infinite loop results in no execution result, the cause of the instruction and the target function are found, and the cause of the failure is investigated. It has a function of avoiding occurrence.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention showing a test program execution method in a data processing device. A test environment setting unit (101) for setting a test instruction sequence (106) on an arbitrary memory of the data processing device and an initial execution value (107) in each hardware resource such as a register. Instruction simulation for generating test instruction sequence simulation information (108) in which an expected value (110) and an expected execution sequence for each instruction are tabulated using the test instruction sequence (106) and the execution initial value (107). The unit (102) sets the execution initial value (107) as an initial value and executes the test instruction sequence (106) on the data processing device to be tested to obtain an execution result value (111). The test instruction sequence execution control unit (103) for forcibly terminating due to the occurrence of a timer interrupt when the processing has not been completed due to (1), the expected value (110) and the execution result value (11)
1) is compared, a mismatch is detected, and failure factor information (109) is detected.
And an execution result comparison unit (104) that outputs an error message (112), a test instruction sequence (106), and an expected value (11).
0), the test instruction sequence simulating information (108), and the execution result value (111) are used to analyze the failure factor and to obtain the failure factor information (1).
09), and the failure avoidance method is the failure avoidance method (113).
A failure factor identification unit (105) that further selects and stores failure factor information and an avoidance method.

FIG. 2 is a flowchart showing the processing of the entire test apparatus of FIG. The test program is kept static,
Alternatively, a test instruction sequence and an initial execution value are set from a dynamically generated test instruction sequence data and execution initial value data group (20).
1) Then, each instruction is simulated based on the initial execution value and the test instruction sequence to generate an expected value and simulation information (202). A timer value that depends on the number of instructions executed in the test instruction sequence is added to the initial value, and a timer interrupt that forcibly times out is generated if the test instruction sequence execution is not terminated due to a failure due to timer monitoring ( 2
03). The generated simulation information is compared with the accumulated failure factor information, and if a failure may have occurred before, the initial value is changed or executed in the degra mode according to the avoidance method added to the failure factor information. Then, a test instruction sequence is executed on the test target processing device, and an execution result is obtained (204). If the execution result is not obtained and a timeout occurs due to the occurrence of a timer interrupt (205), hardware resources are collected when the interrupt occurs (206). The expected value and the execution result value are compared (207),
If there is a mismatch, the error resource is referred to from the error message, and the simulated information of the test instruction sequence is compared with the simulated information to search and identify the instruction address and instruction in which the failure has occurred (208). Refer to the simulation information based on the specified instruction address and instruction,
The re-execution range and the initial value / expected value at the time of re-execution of the test instruction sequence in an arbitrary section are regenerated and re-executed (209), and a failure factor analysis (210) is performed. The process is repeated while expanding the re-execution range until a failure factor can be identified (211). If the execution result is not obtained and the time-out (205) occurs, the address at which the timer interrupt has occurred is temporarily set as the instruction address at which the failure has occurred, and a failure cause analysis (210) is similarly performed.
Add the identified failure factor to the failure factor information (21
2). This operation is repeated until the test of the specified test program is completed (213).

FIG. 3 is a flowchart of a process for analyzing a cause of a failure when a mismatch occurs by comparison with an execution result. An error location is searched from the information output by the error message, and the type of the resource in which the error has occurred and the execution result value are collected (301). Referring to the resource to be changed in the simulation information of the test instruction sequence, (30
The type and execution result value of the error resource collected in 1) are compared with each other, and a matching instruction and instruction address are searched (30).
2) Do it. The simulation information includes an execution instruction count, an instruction address, an instruction code, expected operation information of the instruction, and the type and value of a resource changed by execution of the instruction. If the search is successful, the address of the instruction to be executed immediately before the searched instruction address is searched from the simulation information, and is set as the start address at the time of re-execution. Using the address of the instruction that updates the resource following the searched instruction from the simulation information as the end address, the number of execution instructions in the test instruction sequence at the time of re-execution is calculated from the execution instruction count up to the instruction at the end address. After execution of an arbitrary number of instructions, a setting is made to forcibly generate an interrupt (instruction step interrupt), and the re-execution range is limited (3.
03). In the case of a search failure, the start address of the test instruction string in error is used as the start address for re-execution as it is, and the address of the instruction that first updates the resource is used as the end address. Calculate the number of executed instructions in the test instruction sequence at the time of re-execution from the number of executed instructions, and in the case of a successful search, similarly execute the arbitrary number of instructions and make settings to forcibly generate an interrupt (instruction step interrupt). Restrict execution range (30
Do 3). The test instruction sequence in which the error occurred is simulated until immediately before the start address of the re-execution range, an initial value at the time of re-execution is set (304), and the test instruction sequence is executed from the test instruction sequence start address in the re-execution range. Simulates the instruction up to the instruction count, generates an expected value of the re-execution range and simulation information (305), executes the test instruction sequence in the re-execution range on the data processing device under test, With the occurrence of the instruction step interrupt set in 303), an execution result value of the test instruction sequence in the re-execution range is collected (306). The expected value generated in (305) is compared with the execution result value collected in (306) (307),
If the results match, the re-execution range is limited (303) again based on the re-execution range simulation information, and the number of executed instruction steps is increased. The above process is repeated until the result does not match. If the results do not match, it is determined that an error has occurred due to execution of the last instruction of the test instruction sequence in the re-execution range,
With reference to the simulation information of the re-execution range, a search is performed to determine whether or not the content matching the information of the instruction in error (expected operation) exists in the accumulated failure factor information (30).
8) If it exists, the method of avoiding the failure is reset according to the method of avoiding the failure cause information, the initial value is reset at the time of re-execution, and the test instruction sequence in the re-execution range is executed again (30).
9). If it does not exist in the failure factor information, refer to the failure avoidance selection information and follow the similar error type avoidance method.
The initial value at the time of re-execution is reset, and the test instruction sequence in the re-execution range is executed again (309). The expected value of the re-execution range generated in (305) is compared with the execution result value in (309) (310). If the results do not match, the fault is considered to have occurred for the first time, and the fault avoidance selection information indicates Is selected, and the above processing is repeated until the result matches. If the results match, it is assured that the obstacle has been avoided by the selected avoidance method. If the selected avoidance method is not stored in the fault cause information, the avoidance method is stored together with the fault cause information (311). According to the method of avoiding the failure factor information, if the failure avoidance is successful, the information is not accumulated.

FIG. 4 is a flowchart for analyzing a cause of a failure when an error message cannot be obtained by executing a test instruction sequence. During execution of the test instruction sequence, execution of the test instruction sequence is stopped due to a failure due to a logic failure of the data processing device under test, or the execution of the test instruction sequence ends in an infinite loop. An interrupt is generated, and it is regarded as a test instruction sequence execution timeout. When the timer interrupt occurs, hardware resources such as an interrupt address and each register value are collected (401). When timeout is detected, sequential expected value information of all resources is generated for each instruction unit of the simulation information of the test instruction sequence (402), and (40)
The hardware resources collected in 1) are sequentially compared with the sequential expected value information of each instruction unit generated in (402),
The execution instruction count is extracted from the sequential expected value information at the time of the mismatch, the start address of the test instruction string is used as the start address for re-execution, and after executing an arbitrary number of instructions, an interrupt (instruction step) is performed. Interrupt), and the re-execution range is limited (403). As a result, no timeout occurs during re-execution. The initial value at the time of re-execution is set (404),
Instruction simulation is performed from the instruction at the test instruction sequence start address in the re-execution range to the instruction for the execution instruction count, and an expected value of the re-execution range and simulation information are generated (405). Then, the test instruction sequence in the re-execution range is executed, and the execution result value of the test instruction sequence in the re-execution range is collected in accordance with the occurrence of the instruction step interrupt set in (403) (406). (405)
The expected value generated in step (406) and the execution result value collected in step (406) are compared (407). If the results match, the re-execution range is limited again based on the re-execution range simulation information (403).
To increase the number of executed instruction steps. As in the case where the error message shown in FIG. 3 is obtained, the above processing is repeated until the result does not match. If the results do not match, it is specified that an error has occurred due to the execution of the last instruction in the test instruction sequence in the re-execution range, and the simulated information in the re-execution range is referenced to obtain information on the erroneous instruction (expected operation ) Is searched for in the accumulated fault cause information (408), and if there is, the method of avoiding the fault is determined according to the method of avoiding the fault cause information, and the initial value at the time of re-execution is determined. The reset is performed, and the test instruction sequence in the re-execution range is executed again (409). If it does not exist in the failure cause information, the failure avoidance selection information is referred to, the initial value at the time of re-execution is reset according to a similar error type avoidance method, and the test instruction sequence in the re-execution range is executed again (409). ). (405)
The expected value of the re-execution range generated in (4) is compared with the execution result value in (409) (410). If the results do not match, the failure is regarded as having occurred for the first time, and the next avoidance method is determined based on the failure avoidance selection information. And repeat the above process until the result matches. If the results match, it is assured that the obstacle has been avoided by the selected avoidance method. If the selected avoidance method is not stored in the failure cause information, the avoidance method is stored together with the failure cause information (411). According to the method of avoiding the failure factor information, if the failure avoidance is successful, the information is not accumulated. In the example of FIG. 4, the branch instruction at the address 0x3020 is expected to loop 50 times based on the result of the comparison instruction at the address 0x301C. However, in the operation expected by the instruction simulation information, the address: Ox
Data Cache Hit LD at 3010
Instruction execution result and address executed immediately after: Ox30
There is a register dependency relationship in which the execution result of the LD instruction for Data Cache Miss at address 14 is used by the comparison instruction at address: Ox301C. Actually, the execution result of the LD instruction at address: Ox3014 is Dat
a. Since indeterminate data is read out by Cache Miss, the comparison instruction at the address: Ox301C does not set a loop end condition, and an infinite loop occurs and a timeout occurs. In re-execution, the address in the first loop:
An LD instruction for Data Cache Miss at address Ox3014 is executed, and the result is inconsistent. From the failure avoidance selection information, Cac is used as a method for avoiding cache failure.
The case where he Hit was selected and avoided was shown.

[0011]

According to the present invention, it is possible to reduce the number of steps for analyzing the cause of a defect and to improve the verification accuracy by avoiding the occurrence of a defect due to the same factor, thereby enabling a highly accurate logic verification in a short time. Become.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a test process for performing a test of a data processing device by a test method according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating the entire processing of the test processing of FIG. 1;

FIG. 3 is a flowchart when a mismatch occurs in FIG. 1;

FIG. 4 is a flowchart of a process for analyzing a cause of failure occurrence in the case of a timeout in FIG. 1;

[Explanation of symbols]

 101 Test instruction sequence environment setting unit 102 Instruction simulation unit 103 Test instruction sequence execution control unit 104 Execution result comparison / output unit 105 Failure factor identification unit 106 Test instruction sequence 107 Initial execution value 108 Test instruction simulation information 109 Failure factor information 110 Expected value 111 execution result value 112 error message 113 fault avoidance method

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hirokazu Mitama 1 Horiyamashita, Hadano-shi, Kanagawa F-term in Hitachi Information Technology Co., Ltd. 5B048 CC02 CC05 DD01 FF02

Claims (3)

[Claims] A method for testing a data processing device by causing a data processing device to execute a large amount of test programs,
It has a test environment setting process, an instruction simulator that generates expected values, a test instruction sequence execution control process, a result comparison process, and a failure factor identification process. If a mismatch occurs in the comparison of the test instruction sequence with the execution result of the test instruction sequence, or during execution of the test instruction sequence, execution of the test instruction sequence is suppressed due to a failure due to a logic failure in the data processing device, or the test instruction sequence is executed in an infinite loop. When the result cannot be obtained, the function that has the function of avoiding the occurrence of the failure due to the same failure factor in the subsequent execution of the test program by finding out the instruction and the target function that caused the above and investigating the failure factor is characterized. The test execution method of the data processing device. 2. A failure factor specifying process according to claim 1, wherein when a failure occurs due to execution of the test instruction sequence, the re-execution range of the test instruction sequence is limited and partially re-executed.
A test execution method for a data processing apparatus, having a function of searching for an instruction causing a failure and specifying the cause of the failure and a function of storing a method of avoiding the failure in failure cause information. 3. The test instruction sequence execution control process according to claim 1, wherein the failure instruction information is referred to, and if there is a possibility that a failure which may be the same in the test program to be executed may occur, the test instruction sequence is controlled. A test execution method for a data processing device, characterized by having a function of avoiding occurrence of a failure in the execution of the data processing.