JP2022141461A - Information processing device, information processing system, information processing method, and program - Google Patents

Abstract

To provide an information processing device, an information processing system, an information processing method, and a program that can easily identify an instruction that causes a mismatch when the mismatch is detected with another information processing device in execution results of an instruction sequence.SOLUTION: An information processing device includes: a control unit that executes an instruction sequence having a plurality of instructions; a communication unit that receives a designation of an end execution count indicating the total number of executions of instructions that terminates execution of the instruction sequence in the middle thereof; and a test control unit that terminates the execution of the instruction sequence in the middle thereof when the number of times the instructions are executed reaches the end execution count during the execution of the instruction sequence by the control unit.SELECTED DRAWING: Figure 1

Description

The present invention relates to an information processing device, an information processing system, an information processing method, and a program.

2. Description of the Related Art There is a test method for determining the normality of a device under test by executing a test having the same instruction sequence on the device under test and a simulator and confirming the identity of the execution results. In such a test method, for example, when a discrepancy in execution results is detected, a process of identifying the instruction that caused the discrepancy among the instruction strings is executed.

As an example of a method of identifying the instruction that caused the mismatch, there is a method of inserting an end instruction to instruct the end of the test at an arbitrary position in the instruction string. In this case, the instruction string with the end instruction inserted is re-executed by the device under test and the simulator, and the execution results are compared. By comparing the execution results while changing the insertion position of the end instruction, the instruction that caused the mismatch can be identified.

JP 2020-153804 A

However, when the instruction sequence includes a branch instruction, it may be difficult to identify the instruction that caused the mismatch. For example, when an end instruction is inserted immediately after a branch instruction indicating a repeat process, the branch destination instruction group of the branch instruction is re-executed after the branch instruction is executed and before the end instruction is executed. For this reason, when an inconsistency in the execution result is detected, it takes a long time to analyze the instruction to identify the cause from a large number of instructions including branch instructions and branch destination instructions.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an information processing apparatus, an information processing system, an information processing method, and a program that solve the above problems.

The present invention comprises a control unit for executing an instruction string having a plurality of instructions, a communication unit for accepting a designation of the end execution count indicating the total number of executions of the instructions, which terminates the execution of the instruction string in the middle, and the control unit. and a test control unit that terminates the execution of the instruction sequence when the number of executions of the instruction reaches the end execution count during the execution of the instruction sequence by the unit.

Further, the present invention is an information processing system having a first information processing device representing a device under test and a second information processing device having a simulator. The first information processing device includes a control unit that executes an instruction sequence having a plurality of instructions, and a termination execution count indicating a total number of executions of instructions that terminates execution of the instruction sequence in the second information processing. a communication unit receiving from a device, and interrupting the execution of the instruction sequence when the number of times the instruction is executed reaches the end execution count during the execution of the instruction sequence by the control unit and a test control unit that terminates with The test control unit transmits a first execution result obtained by executing the instruction sequence to the second information processing device via the communication unit. The second information processing device includes: a communication unit that transmits the number of execution times to the first information processing device; a simulator that executes the sequence of instructions until the number of executions of the instructions reaches the number of execution times; and a control unit that acquires a second execution result from execution of the instruction sequence by the simulator. The control unit compares the first execution result received from the first information processing device and the second execution result by the simulator, and outputs a comparison result.

Further, the present invention is an information processing method executed by an information processing apparatus, comprising a step of receiving a designation of an end execution count indicating a total number of executions of commands, in which execution of a sequence of commands including a plurality of commands is terminated midway. and terminating the execution of the instruction sequence when the number of times the instruction is executed reaches the end execution count during the execution of the instruction sequence.

Further, the present invention provides a computer with a procedure for receiving a designation of the end execution count indicating the total number of executions of instructions for ending the execution of an instruction sequence including a plurality of instructions, and a procedure for terminating the execution of the instruction sequence when the number of executions reaches the end execution count.

According to the present invention, when a discrepancy is detected in the execution result of an instruction sequence with another information processing apparatus, the instruction causing the discrepancy can be easily identified.

1 is a block diagram showing a configuration example of an information processing apparatus according to a first embodiment; FIG. 4 is a sequence diagram showing an operation example of the information processing apparatus according to the first embodiment; FIG. It is a figure which shows an example of the test instruction sequence in 1st Embodiment. 4 is a flowchart for explaining processing of the test system in the first embodiment; FIG. 11 is a flowchart for explaining processing of the test system in the second embodiment; FIG. 1 is a block diagram showing a minimum configuration example of an information processing apparatus according to each embodiment; FIG. It is a figure which shows the processing flow by the information processing apparatus of a minimum structure.

An information processing apparatus according to an embodiment of the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram showing a configuration example of a test system 300 according to the first embodiment. A test system 300 shown in FIG. 1 is an example of an information processing system according to the first embodiment. A test system 300 includes a test apparatus 1 and a device under test 2 . The device under test 2 is an information processing device. The test apparatus 1 and the device under test 2 are connected by a general-purpose interface.

The test system 300 of this embodiment causes the test device 1 and the device under test 2 to execute tests having the same instruction sequence, and compares the execution results. When the test system 300 determines that the execution results are the same, the test system 300 confirms the normality of the device under test 2 . Further, when a discrepancy in the execution result of the instruction sequence is detected, the instruction causing the discrepancy is specified among the instruction sequences.

The test apparatus 1 includes, for example, a CPU (Central Processing Unit) 11 , a main storage device 10 , a communication section 12 and an auxiliary storage device 13 . In the test apparatus 1, the CPU 11, the main storage device 10, the communication unit 12, and the auxiliary storage device 13 can input/output information via buses. The test apparatus 1 is communicably connected to the device under test 2 via the communication unit 12 . The auxiliary storage device 13 is configured using a storage device such as a magnetic hard disk device or a semiconductor storage device, for example.

The device under test 2 includes, for example, a CPU 21 , a main storage device 20 , a communication section 22 and an auxiliary storage device 23 . In the device under test 2, the CPU 21, the main storage device 20, the communication unit 22, and the auxiliary storage device 23 can input and output information via buses. The device under test 2 is communicably connected to the test device 1 via the communication unit 22 .

The auxiliary storage device 23 is configured using a storage device such as a magnetic hard disk device or a semiconductor storage device, for example. The auxiliary storage device 23 stores a test program 500 for verifying the operation contents of the device under test 2 . Details of the test program 500 will be described later. The test program 500 is read out from the auxiliary storage device 23 by the CPU 21 and developed in the main storage device 20 to be executed.

FIG. 2 is a diagram showing an example of functional blocks of the test system 300 according to the first embodiment. The CPU 11 of the test apparatus 1 reads and executes a program recorded in the main storage device 10 or the auxiliary storage device 13, for example. Thereby, the test apparatus 1 functions as an apparatus having an operating system 100 , test tasks 101 and a simulator 103 on the main storage device 10 . The test task 101 has test program generation means 1010 , test execution means 1011 , execution result comparison means 1012 , retest execution means 1013 and communication means 1014 .

All or part of each function of the test apparatus 1 may be implemented using hardware such as an ASIC (Application Specific Integrated Circuit), a PLD (Programmable Logic Device), or an FPGA (Field Programmable Gate Array). The program may be recorded on a computer-readable recording medium. Computer-readable recording media include portable media such as flexible disks, magneto-optical disks, ROMs and CD-ROMs, and storage devices such as hard disks incorporated in computer systems. The program may be transmitted over telecommunications lines.

The test program generation means 1010 generates the test program 500 and stores it in the main storage device 10 . A test program 500 includes a test (instruction sequence) 501 and test data 502 . The test (instruction string) 501 is hereinafter referred to as a test instruction string 501 .

The test instruction sequence 501 has multiple instructions. The test data is data input by each command of the test command sequence 501 . Test program 500 does not necessarily require input of test data. If test program 500 does not require data input, generation of test data 502 may be omitted. Details of the test instruction sequence 501 will be described later with reference to FIG.

The test execution means 1011 controls execution of the test program 500 by the simulator 103 of the test apparatus 1 and the device under test 2 . The execution result comparison means 1012 compares the execution results of the test program 500 by the simulator 103 and the device under test 2 and outputs the comparison result to the retest execution means 1013 .

The retest execution means 1013 instructs re-execution of the test program 500 when the execution results of the simulator 103 and the device under test 2 do not match. The retest executing means 1013 instructs reexecution in order to identify the instruction that causes the mismatch. The retest executing means 1013 controls reexecution of the test program 500 by the simulator 103 and the device under test 2 .

The communication means 1014 transmits the generated test program 500 to the device under test 2 and receives execution results of the test program 500 by the device under test 2 . The communication means 1014 notifies the device under test 2 of the end execution count, which is referred to when re-executing the test. The end execution count indicates the total number of executions of instructions that terminate the test program 500 halfway.

The simulator 103 is software or hardware that simulates the operation of the device under test 2 . The simulator 103 executes the same test program 500 as the device under test 2 . The simulator 103 executes the test program 500 and outputs execution results to the execution result comparison means 1012 .

The simulator 103 further has an execution instruction number counter 1030 . The executed instruction number counter 1030 counts the number of times an instruction is executed when the test instruction sequence 501 is executed. The simulator 103 ends the execution of the test instruction sequence 501 when the value of the executed instruction number counter 1030 reaches the end execution count.

Next, the device under test 2 will be described. The CPU 21 of the device under test 2 reads and executes a program recorded in the main storage device 20 or the auxiliary storage device 23 . Thus, the device under test 2 has an executed instruction number counter 201 on the main storage device 20 . The executed instruction number counter 201 counts the number of times an instruction is executed when the test instruction sequence 501 is executed. Main storage device 20 further stores test program 500 transmitted from test apparatus 1 .

The device under test 2 shown in FIG. 2 includes test termination means 202 . The test termination means 202 terminates the test instruction sequence 501 being executed based on the number of termination executions notified from the test apparatus 1 . The test termination means 202 terminates the execution of the test instruction sequence 501 when the value of the execution instruction number counter 201 reaches the number of termination executions. For example, the test termination means 202 terminates the execution of the test instruction sequence 501 using an instruction such as a system call or an API (Application Programming Interface).

All or part of each function of the device under test 2 may be implemented using hardware such as ASIC, PLD, FPGA, or the like. The program may be recorded on a computer-readable recording medium. Computer-readable recording media include portable media such as flexible disks, magneto-optical disks, ROMs and CD-ROMs, and storage devices such as hard disks incorporated in computer systems. The program may be transmitted over telecommunications lines.

FIG. 3 is a diagram showing an example of an instruction string included in the test instruction string 501. As shown in FIG. A test instruction string 501 is an instruction string consisting of a plurality of instructions. According to the example of FIG. 3, test instruction sequence 501 has instruction A, instruction B, branch instruction, instruction C, and instruction D. FIG. A branch instruction is, for example, a branch instruction indicating repeat processing. When a branch instruction is executed, for example, a branch is taken to an already executed instruction, and the instruction at the branch destination is re-executed.

Here, an example of the processing order of the test instruction sequence 501 will be described. The test instruction sequence 501 is executed, for example, in the order of instruction A, instruction B, and branch instruction. When a branch instruction is executed, it branches to, for example, instruction A according to the branch condition of the branch instruction. As a result, the instruction A is executed again, and after the instruction A is executed, the instruction B is executed. Note that the branch may be branched to instruction C depending on the branch condition of the branch instruction.

As described above, when the test instruction sequence 501 includes a branch instruction, the order in which the test instruction sequence 501 is written differs from the execution order of the instructions that are actually executed. Also, depending on the branch conditions, the branch destination instruction of the branch instruction may be executed multiple times.

As described above, the test system 300 of this embodiment causes the device under test 2 and the simulator 103 of the test device 1 to execute the same test instruction sequence 501 . The test system 300 determines the normality of the device under test 2 by confirming the identity of the results of execution by the device under test 2 and the simulator 103 . When a mismatch is detected in the execution results of the test instruction sequence 501 between the simulator 103 and the device under test 2, the instruction that causes the mismatch is identified.

As an example of the specific processing, there is a method of inserting an end instruction for instructing the end of the test at an arbitrary position in the instruction string and ending the test immediately after the arbitrary instruction in the instruction string. The instruction sequence with the end instruction inserted is re-executed. Then, the instruction causing the mismatch is identified based on the presence or absence of the mismatch in the execution results. For example, by comparing the execution results while changing the insertion position of the end instruction, the instruction causing the mismatch is identified.

However, according to this method, it may not be possible to terminate the instruction sequence immediately after an arbitrary instruction. As a result, the execution result cannot be acquired when the execution of the instruction string is terminated immediately after an arbitrary instruction, and it takes time to identify the instruction causing the mismatch.

For example, if the instruction string includes a branch instruction, the execution of the instruction string cannot be terminated after execution of the branch destination instruction. A case in which the execution of the instruction sequence cannot be completed after execution of instruction A executed after branching will be illustrated. For example, if a termination instruction is inserted after instruction A, the execution of the instruction sequence will be terminated before execution of the branch instruction. Also, when inserting the end instruction immediately after the branch instruction, the execution of the instruction string is finished after the branch destination instruction group (instruction A, instruction B, . . . ) is re-executed.

Therefore, the device under test 2 according to the present embodiment terminates the test instruction sequence 501 being executed based on the end execution count notified from the test device 1 . That is, the device under test 2 terminates the execution of the test instruction sequence 501 when the value of the executed instruction number counter 201, which counts the number of times the instruction is executed, reaches the end execution count during the execution of the test instruction sequence 501. Let This makes it possible to terminate the execution of the instruction sequence at any timing.

As described above, according to the device under test 2 of the present embodiment, the execution of the instruction string is terminated based on the number of times the instruction is executed, instead of inserting the end instruction into the instruction string. As a result, even if the instruction string includes a branch instruction, execution of the instruction string can be terminated immediately after execution of an arbitrary instruction. As a result, it is possible to acquire the execution result when the execution of the instruction string is terminated at arbitrary timing.

For example, the test system 300 acquires execution results by the device under test 2 and the simulator 103 while changing the end execution count. The test system 300 can acquire, for example, execution results corresponding to a plurality of end execution counts. As a result, the test system 300 can easily identify the instruction causing the mismatch based on the presence or absence of the mismatch in the execution results according to the number of times of execution to end.

FIG. 4 is a flow chart illustrating processing of the test system 300 in the first embodiment. The test program generation means 1010 (FIG. 2) generates the test program 500 (step S301). As described above, the test program 500 includes the test instruction string 501 and the test data 502 to which the test instruction string 501 refers. The test program 500 may be generated in advance.

The test executing means 1011 transfers the test program 500 to the simulator 103 of the device under test 2 and the test device 1 (step S302). Upon receiving the test program 500 , the device under test 2 stores it in the test program storage area of the main storage device 20 .

The test executing means 1011 instructs the device under test 2 and the simulator 103 to execute the test program 500 . The device under test 2 executes the test program 500 stored in the main storage device 20 according to the instruction (step S303). Similarly, the simulator 103 executes the test program 500 transferred from the test executing means 1011 according to the instruction (step S304).

After completing the test program 500 , the device under test 2 acquires the execution result of the test program 500 and transmits it to the test apparatus 1 . After completing the test program 500, the simulator 103 acquires the execution result of the test program 500 and notifies the execution result comparing means 1012 (FIG. 2). The execution result includes, for example, the state of each register after executing the test program 500 . The execution result may further include output data, output status, etc. of the test program 500 .

The execution result comparison means 1012 compares the execution result received from the device under test 2 with the execution result output from the simulator 103 (step S305). Execution result comparison means 1012 determines whether or not both execution results are identical. The execution result comparing means 1012 may, for example, compare only the states of some registers among the execution results.

If it is determined that the execution results match (YES in step S305), the test executing means 1011 outputs log information and ends the test. The log information includes, for example, information related to execution of the test program 500 in the device under test 2 and the simulator 103 respectively. Log information may include, for example, register states, memory dumps, and the like.

On the other hand, if it is determined that the execution results do not match (NO in step S305), the retest executing means 1013 causes the test program 500 to be executed again. The retest executing means 1013 transfers the test program 500 to the simulator 103 and the device under test 2 (step S306). If the simulator 103 and the device under test 2 already hold the test program 500, the test program 500 need not be transferred.

The retest executing means 1013 notifies the test ending means 202 of the device under test 2 and the simulator 103 of the number of times of execution of the test (step S307). The end execution count indicates the total number of executions of instructions that terminate the test instruction sequence 501 in the middle of execution. In other words, the end execution count indicates the accumulated number of command executions from the start of execution of the test instruction sequence 501 to the end of execution.

An arbitrary value is set as the end execution count, for example, based on the execution record of the test program 500 . The end execution count may be set to an arbitrary small value as an initial value and incremented by one instruction each time the execution is re-executed. Alternatively, the end execution count may be set so as to decrease the value of the executed instruction number counter 201 by one instruction when the test instruction sequence 501 is executed to the end.

The retest executing means 1013 instructs the device under test 2 and the simulator 103 to execute the test program 500 . The device under test 2 executes one command from the test command sequence 501 stored in the main storage device 20 according to the instruction (step S308). As one instruction is executed, the test termination means 202 increments the value of the executed instruction number counter 201 (step S309).

Similarly, the simulator 103 executes one instruction of the test instruction sequence 501 according to the instruction (step S310). As one instruction is executed, the retest executing means 1013 increments the value of the executed instruction number counter 1030 (step S311).

The test terminating means 202 compares the value of the executed instruction number counter 201 with the number of termination executions notified in step S307 (step S312). If they match (YES in S312), the test termination means 202 terminates the test program 500 in the middle of execution. That is, the device under test 2 terminates the test program 500 halfway after executing the command the number of times indicated by the end execution count from the start of the test program 500 .

In this manner, the test termination means 202 can terminate the execution of the test instruction sequence 501 at an arbitrary timing based on the executed instruction number counter 201 and the number of termination executions. Also, the test termination means 202 can terminate execution of the test instruction sequence 501 immediately after execution of the same instruction with the simulator 103 . After the test program 500 ends, the device under test 2 acquires the execution result of the test program 500 and transmits it to the test device 1 .

Similarly, the simulator 103 of the test apparatus 1 compares the value of the executed instruction number counter 1030 with the number of times of end execution notified in step S307 (step S312). If they match (YES in step S312), execution of the test program 500 on the simulator 103 ends halfway. That is, the simulator 103 terminates the test program 500 after executing the instruction the number of times indicated by the end execution count from the start of the test program 500 .

The simulator 103 can also terminate the execution of the test instruction sequence 501 at an arbitrary timing based on the executed instruction number counter 1030 and the number of termination executions. After completing the test instruction sequence 501 , the simulator 103 acquires the execution result of the test program 500 and transmits it to the execution result comparison means 1012 .

On the other hand, if the count values do not match in step S312 (NO in step S312), the device under test 2 continues execution of the test program 500 (S308, S309). Similarly, the simulator 103 continues execution of the test program 500 (S310, S311).

The execution result comparing means 1012 compares the execution result related to re-execution transmitted from the device under test 2 with the execution result related to re-execution output from the simulator 103 (step S313). If it is determined that both execution results match (YES in S313), the retest execution means 1013 outputs log information and terminates the series of test steps.

On the other hand, if it is determined that the execution results do not match (NO in S313), the retest execution means 1013 identifies the instruction that causes the mismatch (step S314). For example, the retest execution unit 1013 refers to whether or not there is a mismatch in the execution results when another end execution count is set. For example, if no discrepancy is detected in the execution result when the end execution count that is one larger value is specified, the instruction corresponding to the specified end execution count is specified as the instruction causing the discrepancy.

The retest execution unit 1013 acquires the log information and ends the series of test steps (step S315). At this time, log information may also be acquired for the simulator 103 .

As described above, the device under test 2 of the first embodiment includes the control unit (CPU) 21 that executes an instruction sequence (test instruction sequence 501) having a plurality of instructions, the communication unit 22, and the test control unit 202. Prepare. The communication unit 22 accepts designation of the end execution count, which indicates the total number of executions of the commands, for ending the execution of the command sequence in the middle. The test control unit 202 terminates the execution of the instruction sequence in the middle when the number of times the instruction is executed reaches the end execution count during the execution of the instruction sequence by the control unit 21 .

In this way, the device under test 2 terminates the execution of the instruction string in the middle of the instruction string when the cumulative number of executions of the instruction reaches the predetermined number of executions after the start of execution of the instruction string. The device under test 2 suspends the execution of the instruction sequence based on the total number of instruction executions rather than adding an end instruction to the instruction sequence. As a result, even if the instruction string includes a branch instruction, the device under test 2 can terminate the execution of the instruction string at an arbitrary timing and acquire the execution result.

Also, the test system 300 can acquire execution results by the device under test 2 and the simulator 103 according to each end execution count while changing the value of the end execution count. The test system 300 can obtain execution results immediately after execution of different instructions by the device under test 2 and the simulator 103, respectively. This makes it possible to easily identify the instruction that causes the mismatch.

Further, the instruction string in this embodiment includes a branch instruction that branches to an already executed instruction in the instruction string. By executing the branch instruction, the control unit re-executes the already executed instruction at the branch destination of the branch instruction. The device under test 2 in the present embodiment terminates the instruction sequence based on the total number of instruction executions, so that even if the instruction sequence includes a branch instruction, the instruction sequence is Execution can be terminated. This makes it possible to easily identify the instruction causing the mismatch even when the instruction string includes a branch instruction.

Further, the test control unit 2 in the present embodiment counts up the number of times the instruction is executed each time the instruction in the instruction sequence is executed after starting the execution of the instruction sequence, and compares it with the end execution count. Further, the test control unit terminates the execution of the instruction sequence in the middle when the number of times the instruction is executed matches the end execution number. As a result, the device under test 2 according to the present embodiment can complete the execution of the instruction sequence at the timing when the instruction sequence has been executed a predetermined number of times after starting the execution of the instruction sequence.

Further, the test control unit 2 according to the present embodiment transmits the first execution result obtained by executing the instruction sequence to another information processing device via the communication unit. The first execution result is the execution result when the sequence of instructions is executed by the other information processing apparatus until the number of times the instructions have been executed reaches the number of times the instruction is executed, and the second execution result by the other information processing apparatus. compared with the results. As a result, execution results can be compared between the device under test 2 and the simulator 103 when execution of the same instruction string is completed at the same timing. Therefore, the instruction causing the mismatch can be efficiently and easily identified.

Further, the test control unit 2 in the present embodiment provides a first execution result when the control unit executes the instruction string to the end, and a second execution result when the instruction string is executed to the end by another information processing device. When the execution results do not match, the same instruction sequence is re-executed based on the number of times of execution to end. In this manner, when a mismatch in the execution result of the instruction string is detected between the device under test 2 and the simulator 103, re-execution processing is performed to terminate the execution of the instruction string halfway according to the number of times of termination execution.

(Second embodiment)
The second embodiment is different from the first embodiment in that log information is acquired when the number of command executions specified in advance is reached during execution of the test program 500 . The description will focus on differences from the first embodiment. The configurations and functional block diagrams of the test apparatus 1 and the device under test 2 are as described in the first embodiment.

FIG. 5 is a flow chart illustrating processing of the test system 300 in the second embodiment. Processing other than step S307 in steps S301 to S315 in the flowchart is the same as in the first embodiment.

In step S307 in the second embodiment, the retest execution unit 1013 notifies the test termination unit 202 and the simulator 103 of the log output execution count in addition to the end execution count. The number of log output executions is the total number of executions of instructions indicating the timing of outputting a log related to the execution of the test instruction sequence 501 . In other words, log information is output when the cumulative number of instruction executions after the start of execution of the test instruction sequence 501 reaches the log output execution number.

The log output execution count may be set to a number smaller than the end execution count by one or a predetermined number. Alternatively, the log output execution count may be set to the execution count corresponding to an arbitrary command. Two or more different values may be specified for the log output execution count.

In the flowchart of FIG. 5, after step S309, the test termination means 202 compares the value of the executed instruction number counter 201 with the log output execution count notified in step S307 (step S320). If they match (YES in step S320), the test termination means 202 outputs log information related to the execution of the test program 500 (step S321). For example, the test termination means 202 acquires log information using commands such as system calls or APIs.

Similarly, after step S311, the simulator 103 compares the value of the executed instruction number counter 1030 with the log output execution count notified in step S307 (step S322). If they match (YES in step S322), the simulator 103 outputs log information related to the execution of the test program 500 (step S323).

The log information includes, for example, information of a type specified in advance. The log information may be the same as or different from the log information in step S315. Note that the simulator 103 does not necessarily have to output log information.

As described above, the communication unit of the device under test 2 in the second embodiment further accepts the designation of the log output execution count indicating the total number of command executions for outputting the log information related to the execution of the command sequence. The test control unit acquires log information when the number of command executions reaches the log output execution count during execution of the command sequence by the control unit.

As a result, it is possible to output log information at the time when an arbitrary number of instruction executions is reached. That is, when the execution of the test instruction sequence 501 ends in the middle, the log information after execution of the instruction immediately before the last instruction can be acquired. In other words, it is possible to acquire not only the log information after the test instruction sequence 501 is terminated due to the interruption, but also the log information after the execution of any instruction executed before the termination.

As a result, for example, log information after the execution of the instruction immediately before the instruction that causes the mismatch and log information after the execution of the instruction that causes the mismatch can be acquired, and both log information can be compared. As a result, the execution state of the device under test 2 can be analyzed more efficiently when a discrepancy in execution results is detected.

(Minimum configuration example)
The information processing device (device under test) 2 according to the minimum configuration example will be described below.
FIG. 6 is a block diagram showing a minimum configuration example of the information processing device 2 according to each embodiment. FIG. 7 is a diagram showing a processing flow by the information processing device 2 with the minimum configuration. It has a control unit (CPU) 21 that executes an instruction string including a plurality of instructions, a communication unit 22 and a test control unit (test termination means) 202 . The communication unit 22 receives designation of the end execution count indicating the total execution count of the command (step S701). The test termination means 202 terminates the execution of the instruction sequence in the middle when the number of times the instruction is executed reaches the end execution count during the execution of the instruction sequence by the control unit 21 (step S702).

(computer configuration)
The information processing apparatus described above has a computer system inside. The process of operation of the information processing apparatus described above is stored in a computer-readable recording medium in the form of a program, and the above processing is performed by reading and executing this program by a computer. Here, the computer-readable recording medium refers to a magnetic disk, a magneto-optical disk, a CD-ROM (Read Only Memory), a DVD-ROM, a semiconductor memory, and the like. Alternatively, the computer program may be distributed to a computer via a communication line, and the computer receiving the distribution may execute the program.

The program in the present embodiment may be for realizing part of the functions to be exhibited by the computer. For example, the program may function in combination with another program already stored in the storage or in combination with another program installed in another device.

In other embodiments, the computer may include a custom LSI (Large Scale Integrated Circuit) such as a PLD (Programmable Logic Device) in addition to or instead of the above configuration. Examples of PLD include PAL (Programmable Array Logic), GAL (Generic Array Logic), CPLD (Complex Programmable Logic Device), and FPGA (Field Programmable Gate Array). In this case, part or all of the functions implemented by the processor may be implemented by the integrated circuit.

Examples of storage include magnetic disks, magneto-optical disks, semiconductor memories, and the like. The storage may be internal media directly connected to the bus of the computer, or external media connected to the computer via an interface or communication line. Further, when this program is delivered to a computer via a communication line, the computer receiving the delivery may load the program into its main memory and execute the above process. In at least one embodiment, the storage is a non-transitory recording medium.

Also, the program may be for realizing part of the functions described above.
Furthermore, the program may be a so-called difference file (difference program) that implements the functions described above in combination with another program already stored in the storage.

Some or all of the above embodiments can also be described as follows, but are not limited to the following.

300 ... test system,
1 ... test equipment,
2 ... device under test,
10... Main storage device,
11... control section,
12... communication section,
13... Auxiliary storage device,
20 ... main storage device,
21 ... control unit,
22... communication section,
23 ... Auxiliary storage device,
100 operating system,
101 test task,
103... simulator,
1010 ... Test program generation means,
1011 ... test execution means,
1012 Execution result comparison means,
1013 ... retest execution means,
1014 ... communication means,
1030 ... Execution instruction number counter,
201 ... Execution instruction number counter,
202 ... Test termination means

Claims (10)

a control unit that executes an instruction sequence having a plurality of instructions;
a communication unit that accepts a designation of the end execution count indicating the total number of executions of the instructions for ending the execution of the instruction sequence in the middle;
a test control unit that terminates the execution of the instruction sequence when the number of times the instruction is executed reaches the end execution count during the execution of the instruction sequence by the control unit;
Information processing device. the sequence of instructions includes a branch instruction that branches to an already executed instruction in the sequence of instructions;
By executing the branch instruction, the control unit re-executes the executed instruction at the branch destination of the branch instruction.
The information processing device according to claim 1 . The test control unit counts up the number of times the instruction is executed each time the instruction in the instruction sequence is executed after starting execution of the instruction sequence, compares it with the end execution count, and is executed matches the end execution count, the execution of the instruction sequence is terminated halfway.
The information processing apparatus according to claim 1 or 2. The test control unit transmits a first execution result obtained by executing the instruction sequence to another information processing device via the communication unit,
The first execution result is an execution result when the sequence of instructions is executed in the other information processing apparatus until the number of times the instructions are executed reaches the number of times the instructions are executed, and the other information processing apparatus ends. compared with a second run result by the device;
The information processing apparatus according to any one of claims 1 to 3. The test control unit provides a first execution result when the control unit executes the instruction string to the end and a second execution result when the instruction string is executed to the end by another information processing device. if they do not match, re-execute the same instruction sequence based on the end execution count;
The information processing apparatus according to any one of claims 1 to 3. The communication unit receives designation of a plurality of different end execution counts,
The test control unit acquires a plurality of the first execution results by executing the instruction sequence, corresponding to each of the plurality of end execution counts.
The information processing apparatus according to claim 4 or 5. The communication unit further receives a specification of a log output execution count indicating the total number of executions of the command for outputting log information related to the execution of the command sequence,
The test control unit acquires the log information when the number of times the command is executed reaches the log output execution count during execution of the command sequence by the control unit.
The information processing apparatus according to any one of claims 1 to 6. Having a first information processing device indicating a device under test and a second information processing device having a simulator,
The first information processing device is
a control unit that executes an instruction sequence having a plurality of instructions;
a communication unit that receives, from the second information processing device, an end execution count that indicates the total number of executions of the commands that end the execution of the command sequence in the middle;
a test control unit that terminates execution of the instruction sequence when the number of times the instruction is executed reaches the end execution count during the execution of the instruction sequence by the control unit; with
The test control unit transmits a first execution result obtained by executing the instruction sequence to the second information processing device via the communication unit,
The second information processing device is
a communication unit that transmits the end execution count to the first information processing device;
a simulator that executes the sequence of instructions until the number of times the instructions have been executed reaches the number of times of termination execution;
a control unit that acquires a second execution result by executing the instruction sequence of the simulator,
The control unit compares the first execution result received from the first information processing device and the second execution result by the simulator, and outputs the comparison result.
Information processing system. a step of receiving a designation of the end execution count indicating the total number of executions of instructions for ending the execution of an instruction sequence having a plurality of instructions in the middle;
a step of terminating the execution of the instruction sequence when the number of times the instruction is executed reaches the end execution count during the execution of the instruction sequence;
An information processing method comprising: to the computer,
a procedure for receiving a designation of the end execution count indicating the total number of executions of instructions for ending the execution of an instruction string including a plurality of instructions;
a procedure of terminating the execution of the instruction sequence when the number of times the instruction is executed reaches the end execution count during the execution of the instruction sequence;
program to run.

Images