JPH04241640A - Testing method for information processor - Google Patents

Abstract

PURPOSE:To effectively utilize a generated instruction string at the time of performing tests by analyzing a test instruction and detecting an error factor instruction. CONSTITUTION:A means which restarts an error instruction detecting means 4 from the instruction immediately after an error factor instruction in a test instruction string by resetting a device to be tested, fetching the simulated result of a simulator 21 obtained until an error factor instruction is detected, and setting the simulated result to the device to be tested as data for execution when an error instruction detecting means 3 detects the error factor instruction, is provided.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing an information processing apparatus by executing a test instruction sequence generated by randomly combining a plurality of instructions.

0002

[Background Art] Conventionally, in a method for testing an information processing device by executing a test instruction sequence generated by randomly combining a plurality of instructions, the execution result of the test instruction sequence on a device under test and the simulation using a simulator are used. If an error is detected by comparison with the result, the error instruction detection means detects the error instruction as shown in FIG.
As shown in , the error-causing instruction is detected by comparing the results of individually executing the instructions in the test instruction sequence on the device under test and the simulator, and the detection of the error-causing instruction enables the detection of subsequent error-causing instructions. It had ended.

0003

[Problem to be Solved by the Invention] In a method for testing an information processing device by executing a test instruction sequence generated by randomly combining a plurality of instructions, the execution result of the test instruction sequence on the device under test and the simulator are compared. If an error is detected by comparison with the simulation results, conventional error instruction detection means will not detect the error-causing instructions after one error-causing instruction is detected. Even if an error-causing instruction is included, the second and subsequent error-causing instructions are not detected, resulting in a problem that the test instruction sequence is not effectively tested.

0004

[Means for Solving the Problems] The present invention provides a test instruction sequence generation means, a simulator that simulates instruction operation using software, and an execution result of a test instruction sequence generated by the test instruction sequence generation means on a device under test. and an error detection means that detects an error by comparing it with the simulation result by the simulator, and when the error detection means detects an error, the execution result of each individual instruction in the test instruction sequence on the device under test and the simulation result by the simulator. In the method for testing an information processing device, the device under test is reset when the error instruction detection means detects the instruction causing the error, and the error instruction detection means detects the instruction causing the error. The present invention is characterized by having means for extracting the simulation results by the simulator up to the present time, setting them in the device under test as execution data, and restarting the error instruction detection means from the instruction immediately after the error-causing instruction in the test instruction sequence. be.

[0005]

Embodiment Next, a method for testing an information processing apparatus, which is an embodiment of the present invention, will be described in detail with reference to the drawings.

FIG. 1 is a flowchart showing the processing of this test method, FIG. 2 is a block diagram showing the processing within the test instruction string generation means, FIG. 3 is a block diagram showing the processing within the test instruction string execution means, and FIG. 4 is a block diagram showing the processing within the test instruction string execution means. FIG. 5 is a flowchart showing the processing within the error instruction detection means, FIG. 5 is a diagram showing a generated test instruction string, and FIG. 6 is a diagram showing data for executing the test instruction string.

Referring to FIG. 1, in this test method, test instruction string generation means 1, test instruction string execution means 2, error detection means 3, and error instruction detection means 4 are sequentially and repeatedly executed.

Looking at FIG. 2, the test instruction sequence generation means 1
It has a test instruction sequence generation process 11, a test instruction sequence execution data generation process 12, and a test instruction sequence execution data setting process 13.

Looking at FIG. 3, the test instruction sequence execution means 2
It has a simulator 21, an execution process 22 that executes a test instruction sequence on the device under test, and an execution process 23 that executes the test instruction sequence on the simulator 21.

Looking at FIG. 4, the error instruction detection means 4
Test instruction sequence execution data setting process 41, test instruction analysis completion determination process 42, analysis target instruction extraction process 43 from the test instruction sequence, and test instruction sequence execution means 2 calling process 4
4, a call process 45 for the error detection means 3, an error information editing and output process 46, a reset process 47 for the device under test, and a test command on the simulator for the data for executing the test command sequence on the device under test. The data setting process 48 also includes a data setting process 48 for copying column execution data.

Now, it is assumed that the test instruction string generation means 1 generates a test instruction string 51 shown in FIG. 5 that includes instructions causing an error in two places.

First, a test instruction string 51 is generated by a test instruction string generation process 11 in the test instruction string generation means 1 . Next, the execution data 52 of this test instruction sequence 51 is generated by the test instruction sequence execution data generation process 12, and the test instruction sequence execution data on the device under test is generated by the test instruction sequence execution data setting process 13. These are set in a space 53 and a data space 54 for executing a test instruction sequence on the simulator 21, respectively. Note that the test instruction string generated by the test instruction string generation process 11 is always limited to the data in the test instruction string execution data space 53 on the device under test and the test instruction string execution data space 54 on the simulator 21. generated to be used as runtime data. Thereafter, by the test instruction string execution process 22 on the device under test in the test instruction string execution means 2 and the test instruction string execution process 23 on the simulator 21, the test instruction string 51 is stored in the execution data spaces 53 and 54. Executed using data.

Test instruction string 5 by test instruction string execution means 2
1, the error detection means 3 compares the data in the test instruction sequence execution data spaces 53 and 54 as a result of executing the test instruction sequence 51 on the device under test and on the simulator 21. It is executed to determine whether there are any errors. The data in the test instruction sequence execution data spaces 53 and 54 are the data generated in the test instruction sequence execution data generation process 12 and set by the test instruction sequence execution data setting process 13, and the initial values are as follows. Since they have the same value, if the test instruction sequence 51 is executed correctly, the data in the test instruction sequence execution data spaces 53 and 54 after the test instruction sequence 51 is executed will also have the same value. However, in the case of the test instruction sequence 51, since two error-causing instructions are included, the data in the test instruction sequence execution data spaces 53 and 54 after the test instruction sequence 51 is executed will have different values, and the error will be detected. The execution result of the test instruction sequence 51 by means 3 is determined to be an error. If the judgment result of the error detection means 3 is that no error has occurred, the test instruction sequence generation means 1 generates an instruction sequence different from the test instruction sequence 51 again, and continues the test using the different test instruction sequence. However, in the case of execution of the test instruction sequence 51, since the determination result by the error detection means 3 is an error, the error instruction detection means 4 subsequently performs processing.

In the error instruction detection means 4, first, a data space 53 for executing a test instruction sequence on the device under test and a data space 53 for executing a test instruction sequence on the device under test are set by a data setting process 41 for executing a test instruction sequence.
The data space 54 for executing the test instruction sequence on 1 is reset. After setting the data, the test instruction analysis completion determination process 42 determines whether the analysis of all test instructions included in the test instruction string 51 has been completed, and continues until the end of analysis of all test instructions is detected. 51 test instructions are extracted individually and executed in sequence while making error judgments on the execution results of the test instructions.

In the case of the test instruction sequence 51, the test instruction 1 is first extracted by the analysis target instruction extraction process 43, and then the test instruction sequence execution means 2 called by the test instruction sequence execution means 2 called by the test instruction sequence execution means 2 calls the device under test. and on the simulator 21. After the test instruction 1 is executed, the error detection means 3 is called by the error detection means 3 calling process 45, and it is determined whether an error has occurred or not after the test instruction 1 has been executed. Since test instruction 1 is executed correctly, the data in the test instruction string execution data spaces 53 and 54 have the same value, so the error detection means 3 does not detect an error in the device under test with test instruction 1, and the test continues as is. The instruction analysis completion determination process 42 determines whether or not the test instruction analysis has been completed, and then error analysis of the test instruction 2 is performed. In the manner described above, the presence or absence of error detection in the device under test for each test command in the test command sequence 51 is analyzed.

Assume that test commands are sequentially extracted from the test command sequence 51, error analysis is performed, and test command i is executed to detect an error in the device under test. Unlike the test instructions extracted so far, when test instruction i is executed, test instruction i will malfunction on the device under test.
The data in 4 do not match, and the determination of error occurrence/non-occurrence by the error detection means 3 is an error, and the error information collection and output processing 46 edits and outputs the error occurrence command and error data.

Note that the test instruction sequence 51 also appears after the test instruction i.
There are still instructions to be analyzed, and it is necessary to analyze the instructions after test instruction (i+1), but before the execution of test instruction (i+1), there is It is necessary to match the data in the test instruction sequence execution data spaces 53 and 54 on the device and on the simulator 21. Therefore, the reset process 47 of the device under test
After first resetting the device under test, the data in the data space 54 for executing the test instruction string on the simulator 21 is retrieved by the simulator execution data setting process 48 to the execution data on the device under test, and It is set in the data space 53 for executing the test instruction sequence on the test device. By the simulator execution data setting process 48 to the execution data on the device under test, the data space 53 for executing the test instruction string on the device under test and the data space 54 for executing the test instruction string on the simulator 21 are set. After matching the data, error analysis of the test commands starting from the test command (i+1) continues. When the test instruction j that detects an error in the device under test becomes an instruction to be analyzed, the same process as in the case of the test instruction i is performed, and the analysis of all test instructions in the test instruction sequence 51 is thereafter completed. up to error instruction detection means 4
Error analysis is performed by After the error analysis is completed, as in the case where no error is detected, control is returned to the test instruction string generation means 1 again, a test instruction string different from the test instruction string 51 is generated, and the test is subsequently performed. As described above, this test method performs error analysis when an error is detected, and is continuously executed until the operator issues an instruction to end the test execution.

[0018]

Effects of the Invention The method of testing an information processing device according to the present invention by executing a test instruction sequence generated by randomly combining a plurality of instructions is such that a plurality of instructions to be tested are randomly selected and a test instruction sequence is executed. This is a test to confirm the normal operation of the hardware and firmware of the device under test by generating and executing a sequence. Therefore, generation, execution, and evaluation of the test instruction sequence are performed repeatedly, and the generation of the test instruction sequence also differs each time the test instruction sequence is executed. Therefore, it is impossible to predict whether a combination of instructions in a test instruction string once generated will appear in the test instruction string again, and the test instruction string needs to be tested effectively.

In the present invention, the device under test is reset when the error instruction detection means detects the instruction causing the error,
By having a means for extracting the simulation results by the simulator up to the detection of the error-causing instruction, setting it in the device under test as execution data, and restarting the error-instruction detection means from the instruction immediately after the error-causing instruction in the test instruction sequence, Even if there are multiple error-causing instructions in a test instruction sequence, all test instructions can be analyzed and the error-causing instruction can be detected, so the instruction sequence generated during the test can be effectively used. It has the effect of being

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing the operation of a test method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing processing within a test instruction sequence generation means in FIG. 1;

FIG. 3 is a block diagram showing processing within a test instruction sequence execution means in FIG. 1;

FIG. 4 is a flowchart showing processing within the error instruction detection means in FIG. 1;

FIG. 5 is a diagram showing a test instruction string generated by the test instruction string generation process in FIG. 2;

6 is a diagram showing test instruction string execution data generated by the test instruction string execution data generation process in FIG. 2; FIG.

FIG. 7 is a flowchart showing processing within a conventional error instruction detection means until the present invention is applied.

[Explanation of symbols]

1 Test instruction sequence generation means 2 Test instruction sequence execution means 3 Error detection means 4 Error instruction detection means 11 Test instruction sequence generation processing 12 Test instruction sequence execution data generation processing 13
Data setting process for test instruction sequence execution 21 Simulator 22 Test instruction sequence execution process on the device under test 23
Test instruction sequence execution process on simulator 41
Test instruction sequence execution data setting process 42 Test instruction analysis completion determination process 43 Analysis target instruction extraction process 44 Test instruction sequence execution means 2 calling process 45
Calling process 46 of error detection means 3
Error information editing and output processing 47 Device under test reset processing 48 Simulator execution data setting processing 51 Test instruction string 52 Test instruction string execution data 53 Data space for test instruction string execution on the device under test 54 Data space for test instruction sequence execution

Claims (2)

[Claims] 1. A test instruction sequence generation means, a simulator for simulating instruction operations using software, an execution result of the test instruction sequence generated by the test instruction sequence generation means on a device under test, and a simulation performed by the simulator. an error detection means for detecting an error by comparison with the result; and a comparison of the execution result of each individual instruction in the test instruction sequence in the device under test and the simulation result by the simulator when the error detection means detects the error. and error instruction detection means for detecting an error-causing instruction, the device under test is reset when the error-causing instruction is detected by the error-causing instruction, until the error-causing instruction is detected. The method further comprises means for extracting simulation results by the simulator, setting them in the device under test as execution data, and restarting the error instruction detection means from the instruction immediately after the error-causing instruction in the test instruction sequence. Test method for information processing equipment. 2. The error instruction detection means resets a data space for executing a test instruction sequence on the device under test and a data space for executing a test instruction sequence on the simulator, and after setting the data, While determining whether the analysis of all test instructions included in the instruction string has been completed, the test instructions of the test instruction string are individually extracted until the analysis of all test instructions is detected, and the execution results of the test instructions are sequentially extracted. 2. The method for testing an information processing device according to claim 1, wherein the test method is executed while making an error determination.