JPH10283388A - Logic verifying device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a logic verifying device by which it is not necessary to hold a huge simulation pattern, it is possible to largely reduce the preparing time of a test pattern, and it is possible to improve the efficiency of simulation. SOLUTION: A pattern automatic generator 2 automatically generates a simulation pattern such as an address, data and control signal from an operation parameter 3, and outputs it to an LSI 1 being the object of logic verification. Automatic judging devices 4 and 14 automatically judge the validity of the operation of the LSI 1 being the object of logic verification during the execution of simulation. An inside state reproducing device 10 reports the inside state of the LSI 1 being the object of logic verification.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification device for performing logic verification on a logic circuit by logic simulation.

[0002]

2. Description of the Related Art In recent years, due to the large scale and complexity of logic accompanying the high functionality and high integration of LSI, the design period of a logic circuit has become longer. Occupy. An enormous test pattern is required for the logic verification of such a large-scale LSI, and the time required for the test pattern, the expected value generation and the expected value comparison greatly affects the design period as the logic verification period is extended. In order to solve such a problem, automatic generation of test patterns and automation of expected value comparison have been considered.

FIG. 9 is a block diagram showing a configuration of a conventional logic verification device disclosed in, for example, Japanese Patent Laid-Open No. 5-128197. This conventional logic verification device automatically generates a time-series simulation pattern that covers all operations from the operation description in the design verification of the logic design, and automatically compares the simulation result of the operation description with the simulation result of the function description. By doing so, the design turnaround time can be significantly reduced.
In FIG. 9, the logic verification device includes an operation input unit 101,
It comprises a function description input unit 102, a pattern generation unit 103, and a comparison simulation unit 104. In FIG. 9, a is an operation description, b is a function description, c is a simulation pattern output from the pattern generation unit 103, d is a simulation model output from the operation description input unit 101, and e is a function description input unit 10
2 indicates a simulation model output, and f indicates a verification result.

Next, the operation will be described. The operation input unit 101 inputs an operation description a in which a logic circuit to be tested is expressed in an operation level hardware description language, and creates a simulation model d in a format that can be input by the comparison simulation unit 104. Further, the function description input means 102 inputs a function description b representing the logic circuit to be tested in a hardware description language at a function level, and creates a simulation model e in a format that can be input by the comparison simulation means 104. Further, the pattern generation unit 103 inputs an operation description a in which a logic circuit to be tested is expressed in a hardware description language of an operation level, and generates a time-series simulation pattern c covering all operations. And the comparison simulation means 1
04 performs a simulation of the operation level using the simulation pattern c and the simulation model d created by the operation description input unit 101, and further performs a function level simulation using the simulation pattern c and the simulation model e created by the function description input unit 102. The simulation is performed, the respective simulation results are compared, and a verification result f, which is information indicating whether the comparison results match or mismatch, is output.

FIG. 10 is a block diagram showing the configuration of a conventional logic simulation system disclosed in, for example, Japanese Patent Application Laid-Open No. 7-271834. This conventional logic simulation method enables a logic verification to be performed efficiently by automatically generating a request generation test program effective for request control logic verification of a logic circuit under test from a test program and operation parameters. It was done. In FIG. 10, the conventional logic simulation method is issued from a test program 201, a function specification defining an address and a data format of a machine language instruction, a memory configuration specification such as a cache built in the processor, and a certain processor. An operation parameter 202 for storing an operation specification in the request control and a machine language instruction group that analyzes whether or not a request is generated in the read machine language instruction and recognizes the occurrence of the request and request information accompanying the instruction are input value parameter 231. A test program generation device 203 for editing as a request generation test program 232, a logic simulator 204 for creating an expected value and verifying the logic of a logic circuit under test, , Expected value parameter Data 251 and the result value 25
2 comprises a comparison / determination device 205 provided with a comparison / determination unit 253 for determining the location where the cause of the failure has occurred. The logic simulator 204 can be referred to and written from the logic circuit device 241 whose normality has been confirmed in advance, the logic circuit device 232 to be tested for logic simulation, and any of the logic circuit device 241 and the logic circuit device 232 to be tested. Memory register unit 243.

Next, the operation will be described. First, generation of the request generation test program 232 will be described. The test program generation device 203 executes the test program 2
01, and reads the machine language instructions constituting the test program stored in the operation parameters 202, and specifies the address and data format of the machine language instructions, the function specifications, the memory specifications such as the cache memory built in the processor, Based on the operation specifications in request control, such as the type of request issued from a certain processor and its conditions, it analyzes the presence or absence of the memory of the address and data of the read machine language instruction, and analyzes the read machine language instruction. Recognize whether a request has occurred. If no request occurs, read the next machine instruction,
When a request is generated, a recognized machine language instruction group is extracted from the test program 201, and information such as the type of the request, the request address, and data accompanying the extracted instruction is stored in the input value parameter 231. It is determined whether all the constituent machine language instructions have been analyzed. If all the machine language instructions have not been analyzed, the next machine language instruction is read. If all the machine language instructions have been analyzed, the test program 20 is read from the input value parameter 231.
A request generation test program 232 that is equivalent to a program obtained by dividing 1 is generated.

Next, generation of the expected value parameter 251 will be described. The logic simulator 204 reads information such as a machine language instruction group and a request processing condition necessary for generating an expected value from the generated request generation test program 232, sets conditions, and confirms normality in advance. A machine language instruction is input to the logic circuit device 241 that is operating. As a result, the machine language instruction is processed, the resulting value of the memory register unit 243 is stored in the expected value parameter 251 as an expected value, and all the machine language instructions constituting the request generation test program 232 are processed. It is determined whether or not it has been performed. If all the machine language instructions have not been processed, the next machine language instruction and the request information accompanying the machine language instruction are read. If all the machine language instructions have been processed, the generation of the expected value parameter 251 ends. When any abnormality occurs in the logic simulation, the processing request is confirmed from the machine language instruction executed by the logic circuit device under test 242, the expected value for the request is extracted from the expected value parameter 251 and the logic simulation is performed. The result value of the memory register unit 243 is stored in the result value 252. The expected value parameter 251 and the result value 252 are compared by the comparison / determination unit 253, and the location of the memory and the register where the comparison result does not match is determined, and the process is terminated.

[0008]

Next, the problems of the prior art described above will be described. In the prior art shown in FIG. 9, it is necessary to generate an expected value in advance, and when the logic of a logic circuit to be tested is large-scale and complicated, an enormous test pattern is required to verify these. ,
At the same time, an enormous expected value is required, and an enormous storage device for storing data is required. In addition, in a method of creating a time-series simulation pattern that covers all operations from an operation description in which a logic circuit to be tested is expressed in an operation-level hardware description language, the logic circuit to be tested has a logical change. In such a case, it may be necessary to create a simulation pattern again.

In the prior art shown in FIG. 10, it is necessary to previously generate a request generation test program valid for a logic circuit under test from a machine language instruction. It may be necessary to re-create a valid request generation test program. In addition, by inputting a machine language instruction to a logic circuit device whose normality has been confirmed in advance,
It is necessary to accumulate the obtained values as expected values, and when an enormous expected value is generated, an enormous storage device is required.

As the prior art, in addition to the above two prior arts, Japanese Patent Application Laid-Open Nos. 7-49902 and 7-2
There are conventional techniques such as 96033, JP-A-5-250434 and JP-A-4-310172. The circuit diagram input device for an integrated circuit disclosed in Japanese Patent Application Laid-Open No. 7-49902 is configured to automatically generate an input pattern from a local circuit and an input terminal. There is. The logic model verification device disclosed in Japanese Patent Application Laid-Open No. 7-296033 is configured to generate a test pattern from pin information of a netlist including a test logic model generated from a library under test for logic synthesis. It is necessary to hold a huge simulation pattern. The method of generating a test pattern for a synchronous sequential circuit disclosed in Japanese Patent Application Laid-Open No. 5-250434 is configured to automatically generate a test pattern from synchronous sequential circuit data, a state transition description, and a library. It is necessary to hold simulation patterns. Further, the present invention automatically generates a test pattern for detecting a fault in a logic circuit, and has a different purpose from the present invention. The logic circuit verification device and the automatic test pattern generation device disclosed in Japanese Patent Application Laid-Open No. 4-212172 are configured to automatically generate a test pattern from a circuit change data file and schematic data. It is necessary to keep.
Further, the present invention automatically generates a test pattern for detecting a fault in a logic circuit, and has a different purpose from the present invention.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and does not need to hold an enormous number of simulation patterns. It is an object of the present invention to obtain a logic verification device capable of improving efficiency.

[0012]

According to a first aspect of the present invention, there is provided an operation parameter 3 including an address, data, write / read, data transfer number, data transfer interval, and the like. Automatically generates simulation patterns such as signals and performs logic verification L
An automatic pattern generator (simulation pattern generating means) 2 for outputting to the SI 1 and a simulation execution using a simulation pattern to verify the validity of the operation of the LSI 1 to be verified without requiring an expected value that must be created before the simulation is executed. Automatic judgment devices (validity judging means) 4 and 14 for automatically judging the internal state, and an internal state reporting device (internal state reporting means) 10 for reporting the internal state of the LSI 1 to be verified. Is what you do.

In the second invention, the automatic pattern generator 2
Is characterized by inputting an operation parameter 3 that is randomly changed within a specified range.

In the third invention, the automatic judgment devices 4, 14
Is a signal monitoring device (signal monitoring means) 6 for monitoring whether the output signal of the LSI 1 to be verified is normal or not, and simulation patterns such as addresses, data, and control signals output from the automatic pattern generator 2. Data comparison devices (data comparison means) 5 and 15 for comparing write data and read data at the same address based on the data.

In the fourth invention, the internal state reporting device 10
Is characterized in that the same operation as the internal control logic circuit of the logic verification target LSI 1 is performed to report the internal state of the logic verification target LSI 1 at the time of inputting the simulation pattern.

The fifth invention is characterized in that, when there are a plurality of LSIs 1 to be verified, an automatic determination device 14 also determines access between the plurality of LSIs 1 to be verified.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of the logic verification device according to the first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an LSI to be verified as a logic circuit under test having a function of performing write / read access to an internal register or a connected memory 11 in response to an external request, and 2 denotes an address from an operation parameter 3 , Data, read / write, data transfer number, data transfer interval, etc.
An automatic pattern generator as a simulation pattern generating means for outputting a simulation pattern to 1;
Are the above-mentioned operation parameters composed of address, data, write / read, data transfer number, data transfer interval and the like. Reference numeral 4 denotes a signal monitoring device 6 as a signal monitoring device for monitoring whether an output signal of the LSI 1 to be verified is normal, and a data comparing device as a data comparing device for comparing write data and read data at the same address. 5 is an automatic judging device as a judging means for judging the validity of the operation of the LSI 1 for logic verification automatically during the execution of the simulation. 7 is an address signal line between the automatic pattern generator 2 and the LSI 1 to be verified, and 8 is an address signal line between the automatic pattern generator 2 and the LSI 1 to be verified.
A data signal line 9 is a control signal line between the automatic pattern generator 2 and the LSI 1 to be verified. 10 performs the same operation as the internal control logic circuit of the LSI 1 to be verified,
LSI for logic verification when inputting simulation patterns
1 is an internal status reporting device as internal status reporting means for reporting the internal status of the internal reporting system. 11 is an LSI to be verified.
The memory 14 accessed from 1 is composed of a signal monitoring device 16 for monitoring whether the output signal of the LSI 1 for logic verification to the memory 11 is normal, and a write data and read data comparison device 15 of the same address. This is an automatic determination device as validity determination means for automatically determining the validity of the operation of the logic verification target LSI 1 with respect to the memory 11 during the execution of the simulation. Reference numeral 17 denotes an address signal line between the logic verification target LSI 1 and the memory 11, reference numeral 18 denotes a data signal line between the logic verification target LSI 1 and the memory 11,
Reference numeral 19 denotes a control signal line between the logic verification target LSI 1 and the memory 11.

Next, the operation will be described. First, generation of the operation parameter 3 will be described. As shown in FIG. 2, the operation parameter table 21 stores operation parameters such as an address, data, a transfer length, a transfer interval, and writing / reading in a predetermined range. Then, the value of the operation parameter corresponding to the generated random number is output to the automatic pattern generator 2. By repeating the process of generating random numbers in this manner, it becomes possible to continuously output the operation parameter 3 to the automatic pattern generator 2. That is, the automatic generator 2 is provided with the operation parameters 3 that have been randomly changed within the specified range.

Next, generation of a simulation pattern will be described. The automatic pattern generator 2 has an address,
Given operation parameters 3 such as data, write / read, data transfer number, data transfer interval, etc., a simulation pattern is generated and output at a specified timing. FIG. 3 shows an automatic pattern generator 2 and a logic verification target L.
5 is a timing chart at the time of writing signals flowing through the address signal line 7, the data signal line 8, and the control signal line 9 between SI1. On the control signal line 9, an address valid signal 33 indicating that the address output from the automatic pattern generator 2 is valid, a data valid signal 35 indicating that the data is valid, and a logic verification target LSI 1 are automatically generated. A data reception signal 36 indicating that the data output from the device 2 has been received, and a write signal 37 indicating a write access to the logic verification target LSI 1 or the memory 11 flow. In the case of FIG. 3, the address signal 32,
The data signal 34, the address valid signal 33, the data valid signal 35 and the write signal 37
And the data reception signal 36 is the logic verification target LS
Output from I1. The clock signal 31 is the logic verification target L
The signals are input to the SI 1 and the automatic pattern generator 2, and both operations are performed based on the clock signal 31.

Upon receiving a write or read request from the automatic pattern generator 2, the logic verification target LSI 1 accesses the internal register of the logic verification target LSI 1 or the memory 11 connected to the logic verification target LSI 1. At this time, a simulation pattern is also output to the automatic determination device 4.

Next, the operation of the data comparison device 5 and the signal monitoring device 6 in the automatic judgment device 4 will be described. The data comparison device 5 includes an internal register of the LSI 1 for logic verification,
And a data holding area for all addresses of the memory 11 and can hold data for each address. The automatic pattern generator 2 operates such that an access to a certain address is always a write at first. FIG. 4 is a flowchart showing the operation of the data comparison device 5. First, the data comparison device 5 recognizes that the access has started (step 41) because the address valid signal has become significant (= 0), and confirms the write signal at this time. If the write signal is significant (= 0), write is determined, otherwise read is determined (step 42). At the same time, it holds an address signal. If it is a write, the data signal when the data valid signal becomes significant (= 0) is held together with the address signal (step 4).
3) When the data reception signal becomes significant (= 0), the process ends (step 44). If it is read, the data at the previously written address held and the currently read data are compared (step 45). If they match, the process ends normally (step 46). If they do not match, the process ends with an error (step 47). ).

FIG. 5 is a flowchart showing the operation of the signal monitoring device 6. The signal monitoring device 6 operates to monitor the operation order of each of the control signal lines 9. When the address valid signal becomes significant (= 0) (step 52), it is recognized that the access has been started (step 51). Next, it is determined whether or not the address valid signal is invalid (= 1) (step 53). If the address valid signal remains significant (= 0) for a prescribed time or more, a timeout is detected and an access error is detected (step 59). Thereafter, similarly (steps 54 to 57), it is monitored whether or not the data valid signal and the data reception signal operate in the order of the timing chart shown in FIG. Then, when each signal is accessed in the order of the timing chart shown in FIG. 2, the process ends normally (step 58).

The LSI 1 to be verified and the memory 11
The automatic determination device 14 connected to the address signal line 17, the data signal line 18, and the control signal line 19 between the
Then, the validity of the operation of the LSI 1 to be verified is determined.

Next, the operation of the internal state reporting device 10 will be described. FIG. 6 is a state transition diagram showing logic for controlling the operation of the LSI 1 to be verified.
Works the same as. When a request is received and the processing of the previous request is being executed, the logic verification target LSI 1
The received request is made to wait, or the pattern automatic generator 2 is requested to re-execute the request. The internal state reporting device 10 defines the internal state of the LSI 1 to be verified at the time of receiving the simulation pattern (at the time of receiving the request) by, for example, A_ST0 to A_ST5 shown in the state transition diagram of FIG.
A combination of ST0 to A_ST5 is defined in advance, and the list shown in FIG. 7 is output when the simulation is executed. FIG. 7 shows a combination list defined in advance or a combination of combinations output from the internal state reporting device 10 when a simulation pattern is received. The comprehensiveness of the logic verification is measured by using the output list and a predetermined combination.
That is, in the internal state reporting device 10, based on the simulation pattern output from the pattern automatic generator 2,
A combination of an access destination such as a memory or a register, an access type including a write / read, and a data transfer length, and an internal state A_ST0 to A_ST5 is defined in advance as a parameter for measuring the coverage of logic verification. Then, at the time of executing the simulation, the internal state reporting device 10 receives the simulation pattern output from the automatic pattern generator 2 and receives the access type including the access destination, the write / read, and the data transfer length, and A_ST0 to A_ST0 at that time. An internal state represented by any one of A_ST5 is output.

As described above, according to the first embodiment, since a simulation pattern is generated from operation parameters including addresses, data, writing / reading, the number of data transfers, data transfer intervals, etc., a large number of simulation patterns can be held. The test pattern creation time can be greatly reduced, and the logic verification target LSI
By judging the validity of the operation during the simulation and reporting the internal state, the efficiency of the simulation can be improved and the cost of logic verification can be reduced. Further, by randomly changing the operation parameters within a specified range, more simulation patterns can be automatically generated, so that the coverage of logic verification can be improved. In addition, expected value data is created in advance by monitoring the output signal of the LSI to be verified and comparing write data and read data of the same address with the address, data, and control signal output from the automatic pattern generator. Therefore, the validity of the operation of the logic verification target LSI can be determined during the execution of the simulation. Further, by outputting the internal state at the time of inputting the simulation pattern, it is possible to measure the completeness of the logic verification.

Embodiment 2 FIG. FIG. 8 is a block diagram showing a configuration of the logic verification device according to the second embodiment of the present invention.
In this logic verification system, the LSI 1 to be verified is n
When there are a plurality of LSIs 1 to be verified, the number of LSIs 1 to be verified is connected to the address signal line 17, the data signal line 18, and the control signal line 19 so that each of the LSIs 1 can be accessed. ing. However, unlike the first embodiment, it is accessible from the address signal line 17, the data signal line 18, and the control signal line 19 side. The number of internal states in FIGS. 6 and 7 described in the first embodiment is different from other logic verification target LSs in the second embodiment.
Since it is accessible from I1, the address signal line 17
And the internal state of the control logic on the data signal line 18 and control signal line 19 sides. In FIG. 8, the logic verification target LS
I1, pattern automatic generator 2, operation parameter 3, automatic determination device 4, data comparison device 5, signal monitoring device 6, internal status reporting device 10, address signal line 7, data signal line 8, control signal line 9, memory 11 , The automatic determination device 14, the data comparison device 15, the signal monitoring device 16, the address signal line 17, the data signal line 18, and the control signal line 19 are shown in FIG.
This is the same as that described above. Also, in FIG.
Reference numerals -1 to 60-n denote simulation models each including the LSI 1 for logic verification, the automatic pattern generator 2, the operation parameters 3, the automatic determination device 4, and the internal state reporting device 10. The automatic determination device 4 includes a data comparison device 5 and a signal monitoring device 6. The automatic determination device 14 includes a data comparison device 15 and a signal monitoring device 16, and determines access between the LSI 1 to be verified and the memory 11 and between the LSIs 1 to be verified. Other operations are the same as those in the first embodiment, and a description thereof will not be repeated.

As described above, according to the second embodiment, when there are a plurality of LSIs to be verified, each of the plurality of LSIs to be verified is accessed. , More test patterns can be given in a fixed time, so that the logic verification time can be shortened and the cost of logic verification can be reduced.

[0028]

As described above, according to the first aspect, a test pattern is created by automatically generating a simulation pattern from operation parameters including addresses, data, write / read, the number of data transfers, data transfer intervals, and the like. The time can be significantly reduced, and the validity of the operation of the logic circuit under test can be determined during the execution of the simulation, and the internal state can be reported to improve the efficiency of the simulation. The effect of reducing the cost of verification can be obtained.

According to the second aspect of the invention, more simulation patterns can be automatically generated by randomly changing operation parameters within a specified range, thereby improving the coverage of logic verification. Is obtained.

According to the third aspect of the present invention, whether or not the output signal of the logic circuit under test is normal is monitored, and the same address is determined by the address, data, and control signal output from the simulation pattern generating means. By comparing the write data and the read data, it is not necessary to create expected value data in advance, and an effect is obtained that the validity of the operation of the logic circuit under test can be determined during the execution of the simulation.

According to the fourth aspect, by outputting the internal state at the time of inputting the simulation pattern, an effect is obtained that the coverage of the logic verification can be measured.

According to the fifth aspect, by accessing different logic circuits under test, more test patterns can be given to a plurality of logic circuits under test in a given time. Therefore, the effect of shortening the logic verification time and reducing the cost of logic verification can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a logic verification system according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating generation of an operation parameter according to the first embodiment.

FIG. 3 is a timing chart of signals between the automatic pattern generator and the LSI to be verified in the first embodiment;

FIG. 4 is a flowchart showing an operation of the data comparison device according to the first embodiment.

FIG. 5 is a flowchart showing an operation of the signal monitoring device according to the first embodiment.

FIG. 6 is a state transition diagram illustrating operations of an internal control circuit and an internal state reporting device of the LSI to be verified according to the first embodiment;

FIG. 7 is a diagram showing a list of the number of internal states output by the internal state reporting device in the first embodiment.

FIG. 8 is a block diagram showing a configuration of a logic verification system according to a second embodiment of the present invention.

FIG. 9 is a block diagram illustrating a configuration of a conventional logic verification device.

FIG. 10 is a block diagram showing a configuration of a conventional logic simulation method.

[Explanation of symbols]

1 LSI for logic verification (logic circuit under test), 2 pattern automatic generator (simulation pattern generation means), 3,202 operation parameters, 4,14 automatic judgment device (validity judgment device), 5,15 data comparison device ( 6, 16 signal monitoring device (signal monitoring device), 7, 17 address signal line, 8, 18 data signal line, 9, 19 control signal line, 10 internal status reporting device (internal status reporting device), 11 memory, 21 operation parameter table, 31 clock signal, 32 address signal, 33 address valid signal, 34 data signal, 35 data valid signal, 36 data receive signal, 3
7 Write signals, 60-1, 60-2, 60-n,
c, d, e simulation model, 101 operation description input means, 102 function description input means, 103 pattern generation means, 104 comparison simulation means, a
Operation description, b function description, f verification result, 201 test program, 203 test program generation device, 20
4 Logic simulator, 205 Comparison device, 231
Input value parameters, 232 Request generation test program, 241 Logic circuit device, 242 Logic device under test, 243 Memory register section, 251 Expected value parameter, 252 Result value, 253 Comparison judgment section.

Claims (5)

[Claims] In a logic verification apparatus for performing logic verification of a logic circuit under test by logic simulation, an operation parameter including an address, data, writing / reading, the number of data transfer, a data transfer interval, and the like, and based on the operation parameter. Simulation pattern generating means for generating a simulation pattern such as an address, data, and a control signal and outputting the simulation pattern to the logic circuit under test; A logic verification device comprising: a determination unit; and an internal state reporting unit that reports an internal state of the logic circuit under test. 2. The logic verification apparatus according to claim 1, wherein said simulation pattern generation means inputs an operation parameter that has been randomly changed within a specified range. 3. The validity judging means is the same as a signal monitoring means for monitoring whether an output signal of a logic circuit under test is normal or not, based on a simulation pattern output from the simulation pattern generating means. 2. The logic verification device according to claim 1, further comprising a data comparison unit that compares write data and read data of an address. 4. The internal state reporting means performs the same operation as the internal control logic circuit of the logic circuit under test,
2. The logic verification device according to claim 1, wherein an internal state of the logic circuit under test at the time of inputting a simulation pattern is reported. 5. The logic verification according to claim 1, wherein when there are a plurality of logic circuits under test, access determination between the plurality of logic circuits under test is also performed by the validity determination means. apparatus.