JP2002163322A - Method and device for verifying logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To exactly detect a spot, where a through current is generated by an HiZ entry, in a logic simulation. SOLUTION: This device is provided with a floating deciding part 3 for detecting a spot, where the through current is generated by gate floating of an MOS transistor caused by an HiZ value entry making the output of a verification target cell into unfixed value, on the basis of a decision function F34 prepared from the circuit chart of a real device, which does not depend on the description of a library F3 for logic simulation in a verification target circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a device for verifying a logic circuit, and more particularly to a logic circuit comprising a CMOS logic circuit.
The present invention relates to a method and apparatus for verifying a logic circuit in an SI.

[0002]

2. Description of the Related Art In recent years, the circuit scale of semiconductor integrated circuits (LSIs), especially logic LSIs composed of CMOS logic circuits, has increased dramatically, and these developments have been carried out using CAD (computer-aided design) devices. It has become mainstream. Furthermore, it is very difficult to manually check these connection rules (rules). Therefore, a method using a CAD device that verifies the connection rules by automatically performing logic verification is widely used. .

In this type of logic verification, a net value of the logic circuit data of the circuit to be verified is observed based on the logic circuit data and test data of the circuit to be verified, thereby simulating the operation state and performing the logic verification. Logic verification using static logic verification, a netlist indicating connection information of a circuit to be verified, and a library indicating circuit information of the logic circuit to determine whether the connection state of the logic circuit is correct based on a verification rule There is.

[0004] As the process becomes finer, power consumption in a standby state (standby mode) has become more problematic than ever before in consumer devices and mobile applications. The discovery of a problem with high power consumption during evaluation on an actual device causes a significant regression and delays the time to market for a product. As a design cause of this problem, there is a through current caused by floating the gate of the MOS transistor due to a high impedance (hereinafter, HiZ) input. That is, the gate potential becomes unstable due to the HiZ input, and when the potential is at the intermediate potential, a through current is generated due to the simultaneous turning on of the P-channel transistor and the N-channel transistor. This cause is a factor that can be found by logic simulation at the gate level. However, in the conventional logic circuit verification method and apparatus, even if gate floating due to HiZ input can be detected,
At the detection location, X caused by an additional description element that does not exist in the actual device added for logic simulation.
There is a problem that a pseudo error, which is a detection location of a value occurrence location, is included.

[0005] This is an example of a conventional dynamic logic verification system.
Referring to FIG. 17 which shows a block diagram of a conventional first logic verification device described in Japanese Patent Application Laid-Open No. 06-016646, the first logic circuit verification device according to the prior art includes test data F10.
1 and logic circuit data F1 to be simulated
Simulator 1 for inputting 02 and performing simulation
01, an output detection unit 102 for detecting the net values “0”, “1”, and “undefined value (X)” output from the simulator 101, and processing a detection result of the output detection unit 102 to output a simulation result F103. Output processing unit 103
And

[0006] The output detector 102 includes a "0" detector 1021 for detecting "0", a "1" detector 1022 for detecting "1", and an "X" detector 1023 for detecting "X".
And

Next, the operation of the first conventional logic circuit verification device will be described with reference to FIG. 17. Test data F101 and logic circuit data F102 describing the circuit structure are described.
Is input to the simulator 101. Simulator 101
Outputs the value of the logic element output of the logic circuit to be verified, that is, the net value. The output detection unit 102 outputs “0”, “1”,
Only “X” is detected and output to the output processing unit 103. The output processing unit 103 sets the input net value and its change to “0”
From "1" and from "1" to "0",
The ones that do not become “1”, the ones that do not become “0”, and the ones that remain at “X” are totaled, and analysis is performed as to which net has performed which operation.
Output as 103.

However, in the above-mentioned first conventional logic verification device, a place where an indefinite (X) value occurs in a net value is detected in a logic simulation.
In some cases, the location where the value is generated is not the same as the location where a through current is generated by gate floating due to the input of the HiZ value (hereinafter, a true error) in an actual device.

The reason is that the logic simulation library has an additional description to which a delay value depending on the logic simulator is pasted and a buffer or the like which does not actually exist for obtaining logical consistency is added. When the occurrence of X due to HiZ input is detected by logic simulation of a simulation library, the X value occurrence location is a buffer or the like described as an additional description (hereinafter, an additional description element)
But it is possible. Therefore, the X-value generation location depends on the description of the simulation library, and the X-value generation location also detects the additional description element that does not occur in the actual device (hereinafter, the X-value generation location by the detected additional description element). Is called a pseudo error).

Referring to FIG. 19A, which schematically shows a logic description of a tristate buffer in a circuit diagram as an example of a library for logic simulation, a data signal D
B1 that outputs data signal D0 in response to the input of
1, a buffer B12 that outputs a control signal EN0 in response to the input of the control signal EN, and a tristate buffer B1 that outputs an output signal Q in response to the input of the data signal D0 when the value of the control signal EN0 is 1.
And 3. Here, the buffer B11 is an additional description element for delay value matching, and does not exist in an actual device. In the logic simulation, the data signal D is set to H
When iZ is input (set), the control signal E
The data signal D output from the buffer B11 regardless of the value of N
0 becomes X. That is, the location where the X value occurs is the buffer B11 that does not exist in the actual device, and causes a pseudo error.

When the control signal EN is 0 even when HiZ is input to the data signal D, a through current does not occur due to the floating gate at the output of the logic element constituting the tristate buffer B13, so that a true error occurs. Output an unrelated pseudo error.

That is, in the first conventional logic verification device, since the detected X value occurrence location includes a pseudo error, the output X value occurrence location detection result is analyzed for true error detection. Time was needed. In addition, there were cases where true errors were missed due to the large number of spurious errors.

[0013] This is an example of a conventional static logic verification system.
Referring to FIG. 18 which shows a block diagram of a conventional second logic verification device described in Japanese Patent Application Laid-Open No. Hei 10-334124, this second logic circuit verification device according to the related art generates a logic circuit diagram for creating a logic circuit diagram. Device 201 and a netlist input unit 202 for inputting a netlist indicating connection information between logic circuits of a circuit diagram created by the logic circuit diagram creation device 201
A library input unit 203 for inputting a library indicating circuit information of a logic circuit, a verification unit 204 for performing verification,
An error / warning output unit 205 that outputs a verification result
And a verification rule storage area 206 storing the verification rules of the logic circuit.

Next, the operation of the second conventional logic circuit verification device will be described with reference to FIG. 18. Focusing on the tri-state buffer of the input netlist, the connection state of the control terminal of this tri-state buffer is described. It is determined whether or not the floating of the gate in the HiZ state occurs (floating error) according to the verification rule from the information of the library. The information of the library in this example describes the relationship between the level state of the control terminal of the tri-state buffer and the output value as the circuit information of the logic circuit. Further, according to the verification rule, when it is determined that the tri-state buffer is in the HiZ state, a floating error occurs when the output pin of the tri-state buffer is connected to one input of the next logic circuit.

In the second conventional logic verification device, the possibility of outputting a HiZ value is determined from the connection state of the control terminal of the tristate buffer, and the next stage logic circuit is determined based on the number of tristate buffer output signals shared. It is determined whether or not a floating occurs in the gate of the device. If the control terminal is not directly connected to the power supply VDD and the ground GND, the signal value input to the control terminal cannot be determined unless simulation is performed. Gate floating due to HiZ input cannot be detected.

FIG. 19 is a schematic circuit diagram showing a logical description of a library at a verification point of the second conventional logic circuit verification device.
Referring to (B), a tri-state buffer B21 that turns on and off the output according to the value of the control signal EN1 and controls the output of the data signal Q1 having an output corresponding to the input data signal D, and supplies the data signal Q1. A logic circuit (buffer) B22 for outputting the received data signal Q2,
A tri-state buffer B23 for turning on and off the output according to the value of the control signal EN2 and controlling the output of the output signal Q3 according to the input data signal Q2.

The verification unit 204 includes a library input unit 203
, The possibility of outputting HiZ as the data signal Q1 output from the tristate buffer B21 depending on the value of the control signal EN1 of the tristate buffer B21 is determined based on the value of the control signal EN1 of the tristate buffer B21.
Is output, and the data signal Q1 is independently output to the next-stage buffer B2.
It is determined that a floating error (the occurrence of gate floating due to HiZ input) occurs when the connection is made to (input to) 2.

However, the buffer B22 at the next stage is a pseudo buffer added to the logic verification library, and the value of the control signal EN1 of the buffer B21 is such that the control terminal to which the control signal EN1 is input is directly connected to the power supply VDD or the ground. If it is not connected to GND, it will not be known unless simulation is performed,
When the next-stage tristate buffer B23 to which the output data signal Q2 of the V.22 is connected (input) is controlled by the control signal EN2, the control signal EN2
Is turned off, no through current is generated in the tri-state buffer B23.

However, in the second conventional logic circuit verification device, as described above, since the floating error is always detected by the tristate buffer B21, a pseudo error may occur.

[0020]

In the above-described first conventional logic circuit verification method and its apparatus, a place where an indefinite (X) value occurs in a net value in a logic simulation is detected. Since the library contains a pseudo error, which is a place where an X value is generated due to an additional description element such as a buffer that does not actually exist for pasting a delay value dependent on a logic simulator or for achieving logical consistency in the library, the detected X value The place of occurrence is not the same as a true error where a through current occurs due to gate floating due to a high impedance (HiZ) value input in an actual device, that is, a pseudo error is included in a detected X value occurrence place. So, for true error detection,
There is a disadvantage that it takes time to analyze the output X-value occurrence detection result.

There is also a disadvantage that a true error may be missed due to the number of pseudo errors.

Further, the second conventional logic circuit verification method and its device determine the possibility of output of the HiZ value from the connection state of the control terminal of the tri-state buffer, and determine the next based on the number of shared tri-state buffer output signals. Since it is determined whether or not floating occurs in the gate of the logic circuit in the stage, if the control terminal is not directly connected to the power supply VDD and the ground GND, the input signal value to the control terminal must be determined by simulation. Since the gate floating due to the HiZ input cannot be detected accurately due to the unknown, there is a disadvantage that a pseudo error may occur.

An object of the present invention is to provide a logic capable of accurately detecting a point where a through-current occurs due to simultaneous turning on of a P-channel transistor and an N-channel transistor when a gate potential becomes unstable due to a HiZ input and an intermediate potential during a logic simulation. It is an object of the present invention to provide a circuit verification method and a device thereof.

[0024]

According to a first aspect of the present invention, there is provided a logic circuit verifying method according to the first aspect of the present invention, which outputs an output of a function cell which is a logic element of a logic circuit to be verified based on the logic circuit data of the circuit to be verified and test data. In a logic circuit verification method for performing a logic verification by simulating an operation state by observing a net value as a value, a logic circuit is created from a circuit diagram of an actual device independent of a description of a logic simulation library of the circuit to be verified. Based on the judgment function, the location of the through current generation caused by the gate floating of the MOS transistor caused by the input of the high impedance (hereinafter, HiZ) value at which the output of the cell to be verified, which is the function cell to be subjected to logic verification, becomes an indefinite value Is detected.

According to a second aspect of the present invention, there is provided a logic circuit verifying method comprising the steps of, based on logic circuit data of a circuit to be verified and test data, a net value which is an output value of a function cell which is a logic element of the logic circuit to be verified. In the logic circuit verification method of performing a logic verification by simulating an operation state by observing, after starting a simulation, an input value detection unit calling step for calling an input value detection unit when a verification time set by a user is reached, A cell name obtaining step of obtaining a cell name of a verification target cell which is a function cell of a logic verification library used in the verification target circuit, and an input value obtaining obtaining a data input value input to the verification target cell A step for calling a corresponding floating determination function from the cell name of the cell to be verified. A function calling step, a floating determination step of determining whether or not the determination condition matches the determination condition in the determination function, an error or warning determination step of determining an error or a warning when the floating determination step matches, and all of the verification targets A function cell end confirmation step of repeating the process from the input value detection unit calling step to the error or warning determination step for the function cell of the above, and the input value detection unit calling step each time the simulation time reaches the verification time. And a simulation end judging step of repeating the processing up to the repetition processing step.

According to a third aspect of the present invention, in the logic circuit verification method according to the second aspect, the floating determination step determines whether the first input signal has a high impedance (hereinafter, HiZ) value. A first input signal determination step to be performed, a first output signal for outputting a through current generation due to an error or gate floating in the case of a HiZ value in the first input signal determination step, A second input signal determining step of determining whether the second input signal has a HiZ value after the first output step if the second input signal is not a HiZ value in the determining step, and determining the second input signal. In the case of a HiZ value in the step, a second output step of outputting a through current due to an error or gate floating, and a step of determining the first input signal, When the Z value is not the Z value and after the second output step, a third input signal determination step of determining whether the third input signal is a HiZ value, and a HiZ determination step of the third input signal. If the value is 3rd, the through current is generated by error or gate floating.
And an output step.

According to a fourth aspect of the present invention, in the logic circuit verification method according to the second aspect, after the calling of the decision function, a decision function presence / absence decision step of determining the presence / absence of a corresponding decision function is provided. And a non-verification target warning step for warning that the target is not a verification target when there is no verification target.

According to a fifth aspect of the present invention, there is provided a logic circuit verifying method according to the present invention, comprising the steps of: In the logic circuit verification method of performing a logic verification by simulating an operation state by observing, after starting a simulation, an input value detection unit calling step for calling an input value detection unit when a verification time set by a user is reached, A cell name obtaining step of obtaining a cell name of a verification target cell which is a function cell of a logic verification library used in the verification target circuit, and an input value obtaining obtaining a data input value input to the verification target cell A step for calling a corresponding floating determination function from the cell name of the cell to be verified. A function call step, receiving a designated signal name which is the name of the designated signal from a designated signal list storing a designated signal designated by a user, wherein an input signal name of the cell to be detected matches the designated signal name and an input signal value Is HiZ
HiZ determination step of a designation signal for determining whether
The designation signal is HiZ in the HiZ determination step of the designation signal.
In the case of, an error determination step of determining all errors regardless of the configuration of the circuit to which the input signal is directly connected,
The designation signal is HiZ in the HiZ determination step of the designation signal.
If not, a floating judgment step for judging whether or not the judgment condition in the judgment function matches, an error or warning judgment step for judging an error or a warning if the judgment is made in the floating judgment step, and for all the function cells to be verified. A function cell end confirming step of repeating a process from the input value detecting unit calling step to the error or warning judging step; and the iterative process from the input value detecting unit calling step every time a verification time is reached until a simulation end time. It is characterized by having a simulation end determination step for repeating the processing up to the step.

According to a sixth aspect of the present invention, there is provided a logic circuit verifying method, comprising the steps of: In a logic circuit verification method for performing a logic verification by simulating an operation state by observing, an input value detection unit calling step for calling an input value detection unit when a set verification time is reached after starting a simulation; A designation signal cell name acquisition step for acquiring a cell name of a cell to be verified, which is a function cell to which a designation signal designated by a user is input from a library; and an input for acquiring a data input value input to the cell to be verified. A value acquisition step, and a determination function of a floating determination corresponding to the cell name of the verification target cell. And the judgment function call step issuing beauty,
A floating determination step of determining whether a specified signal name in a specified signal list created by the user matches a detected signal name and determining whether the specified function matches a determination condition in the determination function; When performing an error or a warning determination step to determine an error or a warning, a function cell end confirmation step of repeating the processing from the input value detection unit calling step to the error or a warning determination step for all the specified signals to be verified, A simulation end determining step of repeating a process from the input value detecting unit calling step to the iterative processing step each time the verification time is reached until the simulation end time.

According to a seventh aspect of the present invention, there is provided a logic circuit verifying apparatus for converting a net value which is an output value of a function cell which is a logic element of a logic circuit to be verified, based on the logic circuit data of the circuit to be verified and test data. In the logic circuit verification device that performs the logic verification by simulating the operation state by observing, the logic verification is performed based on the judgment function created from the circuit diagram of the actual device that does not depend on the description of the logic simulation library of the circuit to be verified. High impedance (hereinafter referred to as Hi) in which the output of the cell to be verified, which is the function cell targeted for
Z) A floating determination unit is provided for detecting a location where a through current occurs at the gate floating of the MOS transistor due to the value input.

According to an eighth aspect of the present invention, there is provided a logic circuit verifying apparatus which converts a net value which is an output value of a function cell which is a logic element of a logic circuit to be verified, based on the logic circuit data and test data of the circuit to be verified. In a logic circuit verification apparatus that performs logic verification by performing a logic simulation of an operation state by observing the logic data, the logic data is a collection of function cells described below that receives the test data and the logic circuit data and refers to the logic circuit data. A simulator for performing the logic simulation with reference to a verification library; an input value detection unit that extracts and outputs a cell name and an input value of a verification target cell that is the function cell to be verified from the simulator; The cell name of the target cell, the input value, and the actual device circuit of the detection target cell A floating determination unit that determines whether a through current is generated in the detection target circuit due to gate floating due to a high impedance input based on a determination function created from and outputs a message of a determination result; and a simulation result of the simulator and the floating determination unit. An output processing unit configured to output a simulation result and a determination result based on the message of the determination unit.

According to a ninth aspect of the present invention, in the logic circuit verification device according to the eighth aspect, the floating determination unit determines correspondence between the cell name extracted by the input value detection unit, the determination function, and the cell name. A judgment function selection unit for selecting a judgment function of the cell to be verified from a judgment function file storing the judgment function with reference to a list; and a gate floating through the judgment function and the input value of the cell having the cell name. A determination unit configured to determine whether or not a current is generated and to output a determination result as a message.

According to a tenth aspect of the present invention, there is provided a logic circuit verifying apparatus for converting a net value which is an output value of a function cell which is a logic element of a logic circuit to be verified, based on logic circuit data and test data of a circuit to be verified. In a logic circuit verification apparatus that performs logic verification by performing a logic simulation of an operation state by observing the logic data, the logic data is a collection of function cells described below that receives the test data and the logic circuit data and refers to the logic circuit data. A simulator for performing the logic simulation with reference to a verification library; an input value detection unit that extracts and outputs a cell name and an input value of a verification target cell that is the function cell to be verified from the simulator; The cell name of the target cell, the input value, and the actual device time of the detection target cell. Based on the determination function created from the diagram, the type of the input signal, and the type of the circuit to which the input signal is connected, the detection target circuit determines whether or not a through current is generated by gate floating due to the high impedance input, and determines the determination result. A floating determination unit that outputs a message, and a type of the input signal required for the floating determination unit and a type of a circuit to which the input signal is connected are extracted from a SPICE netlist having the same hierarchical structure as a logic verification library. And an output processing unit that outputs a simulation result and a determination result based on the simulation result of the simulator and the message of the floating determination unit.

The logic circuit verifying device according to the present invention, based on the logic circuit data of the circuit to be verified and the test data, converts a net value which is an output value of a function cell which is a logic element of the logic circuit to be verified. In a logic circuit verification apparatus that performs logic verification by performing a logic simulation of an operation state by observing the logic data, the logic data is a collection of function cells described below that receives the test data and the logic circuit data and refers to the logic circuit data. A simulator for performing the logic simulation with reference to a verification library; an input value detection unit that extracts and outputs a cell name and an input value of a verification target cell that is the function cell to be verified from the simulator; The cell name of the target cell, the input value, and the actual device time of the detection target cell. A circuit in which the detection target circuit determines whether or not a through current occurs due to gate floating due to a high impedance input based on a determination function created from the drawing, and a specified signal specified by a user is directly connected to an input signal. Irrespective of the configuration, if the data input value is a high impedance value, a floating judgment unit that judges all errors and outputs a message of the judgment result; and a simulation based on the simulation result of the simulator and the message of the floating judgment unit. An output processing unit that outputs the result and the determination result.

[0035]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

In the logic circuit verification method according to the embodiment of the present invention, a net value which is an output value of a function cell which is a logic element of a logic circuit to be verified is determined based on logic circuit data of the circuit to be verified and test data. In a logic circuit verification method for performing a logic verification by simulating an operation state by observing, a logic verification based on a judgment function created from a circuit diagram of an actual device which does not depend on a description of a logic simulation library of the circuit to be verified. The high impedance (hereinafter referred to as Hi) in which the output of the cell to be verified, which is the above-mentioned function cell, becomes an indefinite value
Z) A feature is to accurately detect a through current generation point caused by a gate floating of a MOS transistor due to a value input.

Further, the logic circuit verification device that performs the logic circuit verification method of the present embodiment is configured to output the output of a function cell that is a logic element of the logic circuit to be verified based on the logic circuit data of the circuit to be verified and the test data. In a logic circuit verification device that performs a logic verification by simulating an operation state by observing a net value that is a value, the logic circuit verification device is created from a circuit diagram of an actual device that does not depend on a description of a logic simulation library of the circuit to be verified. A floating determination unit is provided for detecting a location of a through current that occurs in the gate floating of the MOS transistor due to a HiZ value input in which the output of the cell to be verified, which is the function cell to be subjected to logic verification, is an indefinite value based on a determination function. It is characterized by the following.

Next, referring to FIG. 1 which shows a block diagram of the first embodiment of the present invention, a logic circuit verification apparatus for executing the logic circuit verification method of this embodiment shown in FIG. A simulator 1 which receives test data F1 to be supplied and logic circuit data F2 as data to be verified, and performs a logic simulation by referring to a logic verification library F3 which is a group of function cells described later referred to by the logic circuit data F2; An input value detector 2 for extracting and outputting a cell name F31 and an input value F32 of a function cell FS to be verified (hereinafter, a cell to be verified) FS from the simulator 1, and a cell of a cell to be verified extracted by the input value detector 2 Name F31, input value F32, and determination function F described later created from the circuit diagram of the actual device of the detection target cell
34, a floating determination unit 3 that determines whether a through-current occurs in the detection target circuit due to the gate floating due to the HiZ input and outputs a message F35 of the determination result, a simulation result of the simulator 1, and a message of the floating determination unit 3. An output processing unit 4 that outputs a simulation result F4 and a determination result F5 based on F35.

FIG. 2 is a block diagram showing the detailed configuration of the floating judgment unit 3. Referring to FIG. 2, the floating judgment unit 3 which characterizes the present embodiment shown in FIG. A judgment function selection unit 31 for selecting a judgment function F34 of a function cell to be verified from a judgment function file F34 with reference to a correspondence list F33 of functions and cell names, a judgment function F34 and a cell name F
A determination unit 32 that determines whether or not a through current has occurred due to gate floating from the input value F32 of the cell 31 and outputs a determination result as a message F35.

Next, the operation of this embodiment will be described with reference to FIG. 1. The test data F1 is an input signal for simulation supplied to the simulator 1, and the logic circuit data F2 is to be verified. This is the data of the logic circuit. The logic verification library F3 includes buffers, inverters, ANDs, ORs, which are the minimum logic (logic elements) of the logic circuit described for the simulation.
This is a group of function cells, which are modules defining flip-flops and the like, and are referred to by the logic circuit data F2 during simulation.

First, the simulator 1 generates test data F
1 and the logic circuit data F2 are input, and a logic simulation is performed with reference to a logic verification library F3. When the input value detection unit 2 reaches the verification time set by the user,
At this verification time, the logic circuit data F2 is used from the logic verification library F3, that is, the cell name F31 of the function cell under verification (hereinafter referred to as a verification target cell) is extracted and input to the verification target cell. The input value F32 is extracted from the simulator 1. The floating determination unit 3 receives the cell name F31 of the cell to be verified extracted by the input value detection unit 2 and the input value F32 as inputs, and directly connects an input signal corresponding to the test data F1 (hereinafter, a direct input circuit). ), A determination is made as to whether or not a through current occurs due to gate floating due to the HiZ input, and a message F35 of the determination result is output. The output processing unit 4 outputs the simulation result 4 of the simulator 1 and the message F of the determination result of the floating determination unit 3.
In response to 35, the judgment result F5 is output.

Next, the operation of the floating judging unit 3 will be described in detail with reference to FIG. 2. The floating judging unit 3 checks the cell to be verified among the function cells stored in the logic verification library F3. Of the cell name, the input signal value, and the direct input circuit to determine whether or not a through current has occurred due to gate floating by HiZ input.

The floating judgment unit 3 firstly inputs the cell name F31 extracted by the input value detection unit 2 and the cell input value F32
Is received, the judgment function selection unit 31 calls the judgment function F34 from the correspondence list F33 between the judgment function and the cell name, and inputs the same to the judgment unit 32. Next, the determination unit 32 determines the determination function F3
When the input value F32 of 4 causes a through current due to gate floating, an error is determined. If the input signal is a set / reset signal, a warning is determined. Such information of the set / reset signal is set in the determination function in advance. Finally, the determination unit 32 outputs the determination result as an output message F35.

The judgment function F34 is manually created from a circuit diagram of an actual device.

The decision function F34 of the floating decision unit 3
Referring to Table 1 which shows an example of the determination method, first, when the input signals are a data signal and a control signal, if the direct input circuit is a buffer or an inverter, it is determined that an error occurs when the data input value is HiZ. And the data input value is Hi
If it is not Z, it is determined to be normal. If the direct input circuit is a tri-state buffer or a clocked inverter, an error is determined when the data input value is HiZ and the control signal is on, and otherwise, it is determined to be normal. Furthermore, if the direct input circuit is a combinational circuit other than the above, an error is determined if the data input value is HiZ and another signal does not turn off the gate, and otherwise, it is determined to be normal.

Next, when the input signal is a set / reset signal, if the data input value is HiZ, all are judged to be warnings, otherwise, it is judged to be normal.

[0047]

[Table 1]

Although the configuration of the embodiment has been described in detail, the simulator 1 is a logic simulator (for example, Veril) capable of extracting an arbitrary net value of a circuit to be verified at an arbitrary time.
og simulator), and this kind of logic simulator is well known to those skilled in the art and has no direct relation to the present invention, so that its detailed configuration is omitted.

Next, the logic circuit verification method according to the present embodiment will be described with reference to FIG. 3 which is a flowchart showing the processing flow of the logic circuit verification method according to the present embodiment. When the verification time, which is the time at which verification is desired, has been reached (step S1), the input value detection unit 2 is called.

Next, the cell name of the function cell (cell to be verified) of the logic verification library F3 used in the circuit to be verified is obtained (step S).
2) Next, a data input value to be input to the cell to be verified in the logic simulation is obtained (step S3).

Next, a corresponding floating determination function is called from the cell name of the cell to be verified (step S).
4). A floating judgment is made as to whether or not the judgment condition matches with the judgment function (step S5). If the judgment is affirmative, an error or a warning is judged (step S6).

The determination processing of steps S2 to S6 is performed for all the function cells to be verified (step S7), and the processing of steps S1 to S7 is repeated every time the verification time is reached until the simulation end time (step S8).

A diagram schematically illustrating an example of a circuit description structure of the logic verification library F3 (hereinafter, library circuit description) and a circuit diagram of an example of a corresponding actual device circuit structure (hereinafter, actual circuit), respectively. 4 (A) and FIG. 4 (B)
The operation of the present embodiment will be specifically described with reference to FIG. 4. First, the library circuit description shown in FIG. 4A is a buffer circuit that outputs a data signal D1 in response to an input of an input data signal D. B1 and a buffer B2 that outputs the clock signal CLK1 in response to the input of the clock signal CLK
And a cell name FF1_ to which a data signal D1, a clock signal CLK, and a reset signal RES are input and an output signal Q is output
1 with a reset flip-flop FF1.

The corresponding real circuit of FIG. 4B has the cell name FF
Flip-flop FF1 with reset represented by 1_1
This flip-flop FF1A includes a clocked inverter G1 controlled by clocks CK1 and CKB to output a data signal D1 in response to an input of an input data signal D, and a clock signal CKB in response to an input of a clock signal CLK. An inverter G2 for outputting, an inverter G3 for outputting a clock signal CK1 in response to the input of the clock signal CKB, a data signal D1 and a clock signal CK.
B, CK1 and a logic circuit G4 which receives the reset signal RES and outputs an output signal Q.

Next, a correspondence list F3 between the decision function and the cell name
FIG. 5, which shows an example of Table 3 in the form of a table, shows an example of an inverter determination function check_in
v, and the determination function check_nan of the NAND gate
d and the flip-flop determination function check_ff, for example, the flip-flop determination function ch
eck_ff is the number of input signals 3, cell names FF1_1, F
Information such as F1_2, FF1_3, and FF1_4 is shown.

For convenience of explanation, the cell name of the flip-flop with reset FF1 is FF1_1 and the input data signal D is H
iZ, clock signal CLK is “1”, reset signal RE
It is assumed that S is "0".

In this case, in the first conventional logic verification method described above, a pseudo error is reported because an indefinite value X is detected in the output data signal D1 of the buffer B1 to which the data signal D in the library circuit description is input. .

In this embodiment, first, the input value detector 2
Is the detected cell name FF1_1 and the data input value, that is, the input data signal D = HiZ and the clock signal CLK =
“1” and a reset signal RES = “0” are supplied to the floating determination unit 3.

In the floating judgment unit 3, the judgment function selection unit 31 selects, from the correspondence list F33, a judgment function check_ff including the cell name FF1_1 that matches the cell name FF1_1 as the cell to be verified.

Next, the judgment section 32 selects the judgment function c
Using the check_ff, the determination is performed on the detection target cell FF1_1 according to the determination conditions in Table 1.

In the decision step S5 by the decision function, the decision function check of the flip-flop with reset is performed.
Referring to FIG. 6 which shows a determination method based on _ff in a flowchart, a step S51 of determining whether the input signal A has the HiZ value, and a step S52 of outputting an error or generation of a through current due to gate floating in the case of Yes in step S51. If No in step S51 and after step S52, it is determined in step S53 whether the input signal B is a HiZ value, and in step S53, Yes.
In step S54, an error or through current generation due to gate floating is output, and N
In the case of o and after step S54, step S55 for determining whether the input signal C is the HiZ value, and step S5
5. In the case of Yes in step S5, there is provided a step S56 of outputting a through current due to an error or gate floating.

The input signal A shown in FIG.
, The input signal B represents the data signal D, and the input signal C represents the reset signal RES. Based on the above assumption, the input signal A is "1", the input signal B is HiZ, and the input signal C is "0".
1. In the determination step S53 of the input signal B and the determination step S55 of the input signal C, "No" is selected, and the determination result is neither an error nor a warning.

Table 2 shows the combination of the input signals of the flip-flop with reset and the error and warning of the floating judgment by the detection method of the present embodiment.
The comparison with the error due to the detection of the occurrence of X by the logic verification method of FIG.

[0064]

[Table 2]

In Table 2, the detection content indicates the type of the error message F35 output by the detection method of the floating determination unit 3 of the present embodiment. Input data signal D is H
iZ, clock signal CLK is “1”, reset signal RE
When S is "0" or "1", in the second conventional logic circuit verification method, the output data signal D1 of the buffer B1 to which the data signal D is input in the library circuit description of this example is an indefinite value X. Is detected, but is not detected by the result of the determination by the detection method of the floating determination unit 3 of the present embodiment. In a real circuit, since no through current is generated, the determination of the second conventional logic circuit verification method is a pseudo error.

As described above, the present embodiment eliminates a pseudo error, and is caused by the fact that the gate potential becomes unstable due to the gate floating due to the HiZ input and the P-channel transistor and the N-channel transistor are simultaneously turned on at the intermediate potential. It is possible to accurately detect the location of the through current.

Next, referring to Table 3 showing the determination method of the floating determination unit 3A characterizing the second embodiment of the present invention, in the first embodiment, the input signal is set / reset by the determination function F34. In the case of the signal, if the data input value is HiZ, all the warnings are determined. On the other hand, in the present embodiment, as in the case of the data signal and the control signal, an error and a normal are determined from the type of the direct input circuit and the determination condition. It is to be classified into.

Thus, in the present embodiment, it is possible to obtain the same detection result as that of the actual circuit for all signals.

[0069]

[Table 3]

Next, a third embodiment of the present invention will be described with reference to FIG. 7 in which constituent elements common to those in FIG. The difference between the present embodiment and the above-described first embodiment is that the type of input signal and the input signal are connected in addition to the judgment condition of the first embodiment instead of the floating judgment unit 3. A floating determination unit 3B that performs floating detection using the type of circuit, and the types of input signals necessary for the floating determination unit 3B and the types of circuits to which the input signals are connected are set in the same hierarchy as the logic verification library F3. The circuit configuration extraction unit 5 for extracting from the SPICE netlist F6 having a structure is provided.

Next, the operation of the present embodiment will be described focusing on the differences from the first embodiment with reference to FIG. 7. The circuit configuration extraction unit 5 is the same as the logic verification library F3 in the same hierarchy. From the SPICE netlist F6 having the structure, the circuit type and the determination condition required for the determination function F34 of the floating determination unit 3B are determined from the cell name of the function cell, the input signal name, and the connection relationship with the element to which the input signal is directly connected. create.

The operation of the circuit configuration extracting unit 5 will be described with reference to FIG. 8 which shows the processing of the circuit configuration extracting unit 5 in the form of a flowchart. First, from the SPICE netlist F6, the logic in which the input terminal of the cell is connected to the gate is described. If it is an element (step S61), the information of the child type, the gate name, the source name, and the drain name of this logical element is stored in the element list F5.
1 (step S62). Element list F5
1 stores the number of elements sharing the source or drain and a pointer to an element list that stores information on the elements (step S63). The element list F51 is added until the source or the drain of the connected element becomes the power supply VDD or the ground GND (step S64). When the file is checked to the end (step S65), the connection relationship between the P-channel element and the N-channel element is extracted from the element list F51 (step S66). A determination formula that matches the circuit structure from the connection relationship is selected from the circuit configuration list F51 in which the logical configuration is defined (step S67), and the signal name of the gate is set in the determination formula of the selected circuit configuration (step S68). . The determination formula of the circuit configuration whose signal name is set by the circuit configuration extraction unit 5 is used in the determination function of the floating determination unit 3B. Step S66 until the end of the element list F51
To S69 are repeated.

Referring to FIG. 9 which shows an example of the structure of the element list F51 in a table format,
From the model name, gate node name, source node name, source node number, pointer to the element list connected to the source node, drain node name, drain node number, pointer to the element list connected to the drain node It is configured.

Referring to FIG. 10 showing a method of creating the element list F51 of the present embodiment, IN1 defined as an input terminal from the SPICE netlist F6.
Extracts the element whose gate is input and creates an initial element list F511. The information of the element connected to the source node of the element is created in the element list F512, and the pointer of the element list F512 is stored in the element list F512.

Since the drain node of the element to which IN1 is connected to the gate is connected to VDD, the number of the next element list is "0", and the pointer to the next element list is "null".
l ″ is stored. The source node and the drain node are VDD.
Alternatively, when connected to GND, similarly, the number of the next element list is “0” and the pointer to the next element list is “n”.
In addition to the connection of the nodes to VDD and GND, a connection destination element list is created and the pointer is stored in the connection source element list. The pointer to the connection destination element list depends on the number of nodes. Hereafter, the remaining element list F5 constituting the element list F51 in the above procedure will be described.
13 to F518 are created.

The connection relation of the elements is extracted from the generated element list, and a judgment formula that matches the circuit configuration defined in the circuit configuration list F52 is selected. A gate signal name is given to the selected determination equation to create a determination equation. As described above, in the present embodiment, since the circuit configuration is extracted from the SPICE netlist, it is possible to quickly respond to a change in the library, and to obtain an effect that the application target can be expanded and the quality can be guaranteed early.

FIG. 11 shows an example of the circuit configuration list F52.
, P is a P-channel transistor, N is an N-channel transistor, “*” is a parallel connection,
“|” Represents a series connection.

The element list according to the embodiment shown in FIG.
−P−N−N ”, the judgment formula is“ IN1 = H
iZ & P1 = 0 & P2 = 1 ".

Next, a fourth embodiment of the present invention will be described with reference to FIG. 12, which is similarly shown in a flowchart with common reference characters / numerals added to constituent elements common to FIG. The difference of the present embodiment from the above-described first embodiment is that a judgment function presence / absence judgment step S9 for judging the presence / absence of a judgment function corresponding to between the judgment function calling step S4 for floating judgment and the floating judgment step S5. When,
A non-verification target warning step S11 that warns that the cell is not a verification target when there is no judgment function, and when a cell that does not match the corresponding list of the judgment function of the floating judgment unit and the cell name is used, Announcing the cell name.

Next, the operation of this embodiment will be described mainly with reference to FIG. 12, focusing on the differences from the first embodiment. After the start of the simulation, the same steps as in the first embodiment will be described. The processing of S1 to S4 is performed. That is, when the verification time has been reached (step S1), the input value detection unit 2
To obtain the cell name of the cell to be verified (step S2), and then obtain the data input value of the cell to be verified (step S3). The corresponding floating determination function is called from the cell name (step S4).

Next, in step S9, it is determined whether or not there is a determination function to be called in determination function calling step S4. If there is no corresponding determination function, a notification object indicating that the cell to be verified is out of the determination target is set. (Step S10).

Next, in step S9, if there is a judgment function to be called in the judgment function calling step S4, the process proceeds to step S5, and the same steps S5 to S8 as those in the first embodiment are performed. That is, if the judgment condition of the judgment function is matched (step S5), it is judged as an error or a warning (step S6). Steps S2 to S6 for all function cells to be verified
(Step S7), and every time the verification time is reached until the simulation end time, Steps S1 to S1 are performed.
The process of S7 is repeated (Step S8).

As described above, it is possible to prevent the verification from being missed by detecting the function cell which is not to be verified.

Next, the determination method of the floating determination unit 3C characterizing the fifth embodiment of the present invention will be described with reference to Table 3 used in the second embodiment. As in the case of the second embodiment, even if the input signal is a set / reset signal, the mode is classified into an error and a normal based on the type of the input circuit and the determination condition as in the case of the data signal and the control signal. Further, as in the fourth embodiment, notification of the function cell which has become out of the verification target is performed.

Next, a sixth embodiment of the present invention will be described with reference to FIG. 13 in which constituent elements common to those in FIG. The present embodiment is different from the above-described first embodiment in that the data input value is HiZ regardless of the configuration of the direct input circuit for the designated signal designated by the user instead of the floating determination unit 3 Means that a floating determination unit 3D that determines all errors and a designation signal list F7 that is a list of the designation signals are provided.

Referring to FIG. 14, which is a flowchart showing the processing of the present embodiment and the same components as those in FIG. 3 are denoted by the same reference characters / numerals as in FIG. The difference from the first embodiment is that, after the judgment function calling step S4 for floating judgment, a step S11 of judging a match with the signal name of the designated signal list and a HiZ condition of the input signal, and a step S11 Step S12 of outputting an error if the determination result is Yes
In the case of the judgment result No in step S11, there is a step S13 for judging a match with the judgment condition, and in the case of the judgment result Yes in step S13, a step S14 for outputting an error or a warning.

Next, the operation of the present embodiment will be described with reference to FIGS. 13 and 14 with emphasis on the differences from the first embodiment. The cell name F31 of the cell to be verified and the input value F32 thereof are supplied (steps S1 to S1).
3) Call a corresponding floating determination function from the cell name (step S4). Designated signal list F
7, a designation signal name which is the name of the designation signal designated by the user is received, and it is determined whether the input signal name F31 of the detection target cell matches the designation signal name and the input signal value is HiZ (step S11). . If Yes in step S11,
All errors are determined irrespective of the circuit configuration of the direct input circuit (step S12), and if No, it is determined whether or not they match the determination conditions of the determination function (step S13). If the result of the determination in step S13 is Yes, an error or a warning is determined.

Next, the determination processing of steps S2 to S4 and S11 to S14 is performed for all the function cells to be verified (step S7), and every time the verification time is reached until the simulation end time, steps S2 to S4 are performed.
The processes of S11 to S14 and S7 are repeated (Step S
8).

The error determination (step S12) may be replaced with a warning determination.

Next, a seventh embodiment of the present invention will be described with reference to FIG. 15, which is a flowchart similar to that of FIG. This embodiment is different from the above-described first embodiment in that, instead of step S2, a cell name of a function cell to which a designation signal is input as a cell name to be verified is obtained, and step S5 is obtained. When the specified signal name and the detected signal name match instead of the step S7, the matching determination step S16 and the step S7 are performed.
And a confirmation step S17 of confirming whether all the designated signals have been verified, and detecting only the designated signal designated by the user in the same manner as in the first embodiment.

Next, with reference to FIG. 15, the operation of the present embodiment will be described focusing on the differences from the first embodiment. First, when the verification time is reached (step S1)
The input value detection unit 2 is called to obtain the cell name of the cell to be verified, which is the function cell to which the designated signal has been input, from the logic verification library (step S15). Next, the data input value of the cell to be verified is obtained. Acquire (step S3). The corresponding floating determination function is called from the cell name (step S4).

Next, if the specified signal name in the specified signal list created by the user matches the detected signal name, if the determination condition in the above determination function matches (step S1).
6), an error or a warning is determined (step S)
6).

The determination processing of steps S15, S3, S4, S16, S6, and S17 is performed for all the designated signals to be verified (step S17), and every time the simulation time reaches the simulation end time, steps S1S15 and S1S15 are performed.
The processing of S3, S4, S16, S6, S17, S8 is repeated (step S8).

As a result, verification targets can be narrowed down, and the verification time can be reduced.

Next, referring to FIG. 16, which shows the eighth embodiment of the present invention in which components common to those of FIG. 7 are denoted by common reference characters / numerals and are similarly indicated by blocks. This embodiment differs from the third embodiment only in the type of input signal, the type of circuit to which the input signal is connected, and the designated signal specified by the user instead of the floating determination unit 3B. A floating determination unit 3E that determines whether a through-current occurs due to gate floating due to HiZ input based on the detection target and outputs a message F35 of the determination result, and a designation signal list F7.

Next, the operation of the present embodiment will be described with reference to FIG.
When this input signal is a set / reset signal and the data input value is HiZ, all are determined to be "warnings", and the data signal and the control signal are determined to have an error as shown in Table 1 based on the type of the input circuit and the determination conditions. Classify as normal.

As described above, the logic circuit verification method and device of the present invention have the following effects.

The first effect is that it is possible to detect a through-current generation location due to gate floating at HiZ input at the same location as the actual device, and it is easy to specify a through-current generation location since no pseudo error occurs. That is, the analysis time can be reduced. Further, since no pseudo error is detected, the true error is not overlooked. The reason is,
This is because a floating determination unit based on an actual device that does not depend on the description of the logic simulation library is provided.

The second effect is that since a place where a through current is generated can be found at the design stage, there is little reversal of the design process and the developed product can be put on the market early. The reason for this is that a part that has been conventionally found in actual device evaluation can be detected by logic simulation.

A third effect is that a syntax checker at the register transfer level is used to detect and correct a location where a through current may occur due to gate floating at the HiZ input, and a manual correction at the gate level. May be defective. By performing the verification method of the present invention after the manual correction, the creation of defects is prevented and the design quality is maintained.

[0101]

As described above, the logic circuit verification method and apparatus according to the present invention provide a HiZ based on a judgment function created from a circuit diagram of an actual device which does not depend on the description of a logic simulation library of a circuit to be verified. By providing a floating determination unit that accurately detects the location of a through current that occurs when the gate of a MOS transistor is floating due to a value input, the location of a through current that occurs due to gate floating at the HiZ input is detected at the same location as the actual device Since a pseudo error does not occur, it is easy to identify a place where a through current occurs, and the analysis time can be shortened.

Further, there is an effect that a true error is not overlooked because no pseudo error is detected. Conventionally,
Since the location of the through current that was found in the actual device evaluation can be found in the logic simulation at the design stage,
There is an effect that development products can be put into the market early with little reversion of the design process.

Further, when a location where a through current is likely to occur due to gate floating at the HiZ input is detected and corrected by using a syntax checker at the register transfer level, a malfunction occurs when the correction is manually performed at the gate level. However, by performing the verification of the present invention after manual correction, there is an effect that defects can be prevented from being created and design quality can be maintained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a logic circuit verification device that executes a logic circuit verification method according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a detailed configuration of a floating determination unit in FIG. 1;

FIG. 3 is a flowchart illustrating an example of a logic circuit verification method according to the present embodiment.

FIG. 4 is a circuit diagram showing an example of a circuit description structure of a logic verification library and an example of a corresponding actual device circuit structure, respectively.

FIG. 5 is an explanatory diagram illustrating an example of a correspondence list of a determination function and a cell name in a table format.

FIG. 6 is a flowchart illustrating a determination method of a flip-flop with reset using a determination function.

FIG. 7 is a block diagram illustrating a logic circuit verification device that performs a logic circuit verification method according to a third embodiment of the present invention.

FIG. 8 is a flowchart illustrating a process of a circuit configuration extraction unit in FIG. 7;

FIG. 9 is a diagram illustrating an example of a configuration of an element list in a table format.

FIG. 10 is an explanatory diagram illustrating a method of creating an element list according to the present embodiment.

FIG. 11 is an explanatory diagram illustrating an example of a circuit configuration list.

FIG. 12 is a flowchart illustrating a logic circuit verification method according to a fourth embodiment of the present invention.

FIG. 13 is a block diagram illustrating a logic circuit verification device that performs a logic circuit verification method according to a sixth embodiment of the present invention.

FIG. 14 is a flowchart illustrating a logic circuit verification method according to the present embodiment.

FIG. 15 is a flowchart illustrating a logic circuit verification method according to a seventh embodiment of the present invention.

FIG. 16 is a block diagram illustrating a logic circuit verification device that performs a logic circuit verification method according to an eighth embodiment of the present invention.

FIG. 17 is a block diagram illustrating an example of a first conventional logic circuit verification device.

FIG. 18 is a block diagram showing an example of a second conventional logic circuit verification device.

FIG. 19 is a circuit diagram schematically showing a logical description of a tristate buffer as a first and a second example of a logic simulation library.

[Explanation of symbols]

Reference Signs List 1,101 Simulator 2 Input value detection unit 3, 3A, 3B, 3C, 3D, 3E Floating determination unit 4 Output processing unit 5 Circuit configuration extraction unit 31 Decision function selection unit 32 Determination unit 102 Output detection unit 103 Output processing unit 201 Logic Circuit diagram creation device 202 Netlist input unit 203 Library input unit 204 Verification unit 205 Error / warning output unit 206 Verification rule storage area B1, B2 Buffer F1, F101 Test data F2, F102 Logic circuit data F5 Judgment result F6 SPICE netlist F7 Designation signal list F51 Element list F4, F103 Simulation result F31 Cell name F32 Input value F33 Correspondence list F34 Judgment function F35 Message FF1 Flip-flop G1-G3 Inverter G4 Logic circuit

Claims (11)

[Claims] An operation state is simulated by observing a net value which is an output value of a function cell which is a logic element of a logic circuit to be verified based on logic circuit data and test data of the circuit to be verified. In the logic circuit verification method for performing logic verification, the verification target being the function cell to be subjected to logic verification based on a determination function created from a circuit diagram of an actual device that does not depend on a description of a logic simulation library of the circuit to be verified MO caused by input of a high impedance (hereinafter, HiZ) value at which the output of the cell becomes an indefinite value
A method of verifying a logic circuit, comprising: accurately detecting a through-current generation position caused by floating of a gate of an S transistor. 2. An operation state is simulated by observing a net value which is an output value of a function cell which is a logic element of a logic circuit to be verified based on logic circuit data and test data of the circuit to be verified. In a logic circuit verification method for performing logic verification, an input value detection unit calling step for calling an input value detection unit when a verification time set by a user is reached after starting a simulation, and a logic verification used in the circuit to be verified. Obtaining a cell name of a cell to be verified, which is a function cell of a library for use, obtaining an input value to obtain a data input value input to the cell to be verified, and obtaining the cell name of the cell to be verified A judgment function calling step of calling a corresponding judgment function of the floating judgment from A floating judgment step for judging whether or not the judgment condition matches; an error or warning judgment step for judging an error or a warning when the judgment is affirmative in the floating judgment step; calling the input value detection unit for all function cells to be verified A function cell end confirmation step of repeating a process from a step to the error or warning determination step; and a process from the input value detection unit calling step to the repetition process step is repeated every time a verification time is reached until a simulation end time. A simulation end determination step. 3. The first input signal determining step of determining whether the first input signal has a high impedance (hereinafter, HiZ) value, and the first input signal determining step. A first output step of outputting a through current due to an error or gate floating in the case of a HiZ value in the step; a second output step of determining whether the first input signal is not a HiZ value and a second output step after the first output step. Input signal is H
a second input signal determining step of determining whether the value is an iZ value; and a second output step of outputting an error or generation of a through current due to gate floating in the case of the HiZ value in the second input signal determining step. When the first input signal is not HiZ in the first input signal determination step and after the second output step, the third input signal becomes H level.
a third input signal determination step of determining whether the value is an iZ value; and a third output step of outputting an error or generation of a through current due to gate floating in the case of the HiZ value in the third input signal determination step. The logic circuit verification method according to claim 2, further comprising: 4. A judgment function presence / absence judgment step for judging the presence / absence of a corresponding judgment function after the judgment function calling step, and a non-verification target warning step for warning that the judgment function is not a target when there is no judgment function. The logic circuit verification method according to claim 2, further comprising: 5. An operation state is simulated by observing a net value which is an output value of a function cell which is a logic element of the logic circuit to be verified based on the logic circuit data and test data of the circuit to be verified. In a logic circuit verification method for performing logic verification, an input value detection unit calling step for calling an input value detection unit when a verification time set by a user is reached after starting a simulation, and a logic verification used in the circuit to be verified. Obtaining a cell name of a cell to be verified, which is a function cell of a library for use, obtaining an input value to obtain a data input value input to the cell to be verified, and obtaining the cell name of the cell to be verified A judgment function calling step for calling the corresponding judgment function of the floating judgment from A designation signal that receives a designation signal name that is the name of the designation signal from a designation signal list storing the designation signal, and determines whether the input signal name of the detection target cell matches the designation signal name and the input signal value is HiZ. In the HiZ determining step of the above, and in the HiZ determining step of the specifying signal, the designated signal is HiZ.
In the case of (1), an error determination step of determining all errors regardless of the configuration of a circuit to which the input signal is directly connected;
If not, a floating judgment step for judging whether or not the judgment condition in the judgment function is matched, an error or warning judgment step for judging an error or a warning if the judgment is made in the floating judgment step, for all the function cells to be verified A function cell end confirming step of repeating a process from the input value detecting unit calling step to the error or warning determining step; and the iterative process from the input value detecting unit calling step every time a verification time is reached until a simulation end time. A method for verifying a logic circuit, comprising a simulation end determination step for repeating processing up to the step. 6. An operation state is simulated by observing a net value which is an output value of a function cell which is a logic element of a logic circuit to be verified based on logic circuit data and test data of the circuit to be verified. In the logic circuit verification method that performs logic verification, an input value detection unit call step that calls the input value detection unit when the set verification time is reached after the simulation starts, and a specified signal specified by the user from the logic verification library is input A designation signal cell name acquiring step of acquiring a cell name of a cell to be verified, which is a function cell being performed; an input value acquiring step of acquiring a data input value inputted to the cell to be verified; A decision function calling step of calling a corresponding floating decision function from a cell name; A floating determination step of determining whether a specified signal name in a specified signal list created by a user matches a determination condition in the determination function when the detected signal name matches the detected signal name; An error or warning determining step for determining an error or a warning; a function cell end confirming step of repeating a process from the input value detecting unit calling step to the error or warning determining step for all designated signals to be verified; and a simulation. A logic circuit verification method, comprising: a simulation end determination step of repeating a process from the input value detection unit calling step to the repetition processing step each time a verification time is reached until an end time. 7. An operation state is simulated by observing a net value which is an output value of a function cell which is a logic element of the logic circuit to be verified based on the logic circuit data and test data of the circuit to be verified. In a logic circuit verification apparatus for performing logic verification, the verification target being the function cell to be subjected to logic verification based on a determination function created from a circuit diagram of an actual device that does not depend on a description of a logic simulation library of the circuit to be verified MO caused by input of a high impedance (hereinafter, HiZ) value at which the output of the cell becomes an indefinite value
A logic circuit verification device, comprising: a floating determination unit that detects a through-current generation location caused by gate floating of an S transistor. 8. A logic simulation of an operation state is performed by observing a net value which is an output value of a function cell which is a logic element of the logic circuit to be verified based on the logic circuit data and test data of the circuit to be verified. A logic circuit verification device that performs logic verification by inputting the test data and the logic circuit data, and performing the logic simulation with reference to a logic verification library, which is a collection of function cells to be described later referred to by the logic circuit data. A simulator to perform, an input value detection unit that extracts and outputs a cell name and an input value of a verification target cell that is the function cell to be verified from the simulator, and an extracted cell name and the input value of the extracted verification target cell. The detection is performed based on a judgment function created from a circuit diagram of an actual device of the cell to be detected. A floating determination unit that determines whether a through-current is generated in the output target circuit due to gate floating due to the high impedance input and outputs a message of the determination result; a simulation result based on the simulation result of the simulator and the message of the floating determination unit And an output processing unit for outputting a determination result. 9. The verification target cell from a judgment function file in which the floating judgment unit stores the judgment function with reference to the correspondence list of the cell name, the judgment function, and the cell name extracted by the input value detection unit. A determination function selection unit that selects a determination function of, a determination unit that determines whether or not a through current has occurred due to gate floating from the determination function and the input value of the cell having the cell name, and outputs a determination result as a message. The logic circuit verification device according to claim 8, further comprising: 10. A logic simulation of an operation state by observing a net value which is a value of an output of a function cell which is a logic element of a logic circuit to be verified based on logic circuit data and test data of the circuit to be verified. A logic circuit verification device that performs logic verification by inputting the test data and the logic circuit data, and performing the logic simulation with reference to a logic verification library, which is a collection of function cells to be described later referred to by the logic circuit data. A simulator to perform, an input value detection unit that extracts and outputs a cell name and an input value of a verification target cell that is the function cell to be verified from the simulator, and an extracted cell name and the input value of the extracted verification target cell. Judgment function and input signal type created from the circuit diagram of the actual device of the cell to be detected A floating determination unit that determines whether a through current is generated in the detection target circuit due to gate floating due to high impedance input based on the type and the type of circuit to which the input signal is connected, and outputs a determination result message; A circuit configuration extraction unit for extracting a type of the input signal required for the floating determination unit and a type of a circuit to which the input signal is connected from a SPICE netlist having the same hierarchical structure as a logic verification library; A logic circuit verification device comprising: an output processing unit that outputs a simulation result and a determination result based on the simulation result and the message of the floating determination unit. 11. A logic simulation of an operation state by observing a net value which is an output value of a function cell which is a logic element of a logic circuit to be verified based on logic circuit data and test data of the circuit to be verified. A logic circuit verification device that performs logic verification by inputting the test data and the logic circuit data, and performing the logic simulation with reference to a logic verification library, which is a collection of function cells to be described later referred to by the logic circuit data. A simulator to perform, an input value detection unit that extracts and outputs a cell name and an input value of a verification target cell that is the function cell to be verified from the simulator, and an extracted cell name and the input value of the extracted verification target cell. Based on the judgment function created from the circuit diagram of the actual device of the detection target cell, It determines whether the detection target circuit generates a through current due to gate floating due to the high impedance input, and for the specified signal specified by the user, the data input value is high regardless of the configuration of the circuit to which the input signal is directly connected. A floating determination unit that outputs a determination result message by determining all errors when the impedance value is an impedance value; and an output processing unit that outputs a simulation result and a determination result based on the simulation result of the simulator and the message of the floating determination unit. A logic circuit verification device comprising: