CN114785715A - Link delay detection system and method - Google Patents
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Abstract
The application relates to a link delay detection system and a link delay detection method. The system comprises: the device comprises a vector generation device, a link detection device and a link detection device, wherein the vector generation device is connected with an input end of a link to be detected and is used for inputting a test vector to the link to be detected, the test vector comprises a plurality of data which are sequentially arranged, and values of two adjacent data are different; the measuring equipment is connected with the output end of the link to be tested and used for acquiring test data obtained by the test vector through the link to be tested; respectively delaying the test data for different durations to obtain a plurality of delay vectors; and determining whether the time delay of the link to be detected reaches the standard or not according to the mutual relation of the data of the plurality of delay vectors in the preset time range. The method can judge whether the time delay of the link to be detected reaches the standard or not only according to the test data output by the link to be detected, and does not need to compare with other standard data, so that resources are saved, the method can simply and reliably judge whether the time delay of the link to be detected reaches the standard or not, and the detection time is saved.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a link delay detection system and method.
Background
With the development of Field Programmable Gate Array (FPGA) (field Programmable Gate array) technology, the FPGA chip made in China is more and more complex, and the FPGA chip mainly includes the following three parts: configurable logic block CLB (configurable logic block), input/output block IOB (input/output block) and programmable interconnect (programmable interconnect). The FPGA is designed in a hardware description language, and then generates a bit stream file containing configuration information of all programmable logic modules through EDA (Electronic design automation) software. Each programmable logic module in the FPGA, such as a CLB, an IOB, a programmable interconnection line, and the like, has a signal transmission delay, and the delay of the modules changes with the manufacturing process of the FPGA chip, the working voltage, the temperature, and the like, which causes difficulty in accurately calculating the signal transmission delay in the FPGA chip. The FPGA is a modular IP core (intelligent performance core), which can greatly reduce the cost of hardware development and is configured more flexibly, so the FPGA is widely applied in the fields of industry, aerospace, aviation, artificial intelligence and the like, and it is important to influence whether the timing in the FPGA is accurate, whether the delay is appropriate, whether the delay can normally operate, and therefore how to detect whether the delay of the link in the FPGA reaches the standard is a problem to be solved at present.
Disclosure of Invention
Therefore, it is necessary to provide a link delay detection system and method capable of simply and conveniently detecting whether the delay of a link reaches the standard only by the output delay of the link.
A link latency detection system, the system comprising: the device comprises a vector generation device and a test device, wherein the vector generation device is connected with an input end of a link to be tested and is used for inputting a test vector to the link to be tested, the test vector comprises a plurality of data which are sequentially arranged, and values of two adjacent data are different; the measuring equipment is connected with the output end of the link to be tested and used for acquiring test data obtained by the test vector through the link to be tested; delaying the test data for different durations respectively to obtain a plurality of delay vectors; and determining whether the time delay of the link to be detected reaches the standard or not according to the relationship among the data of the plurality of delay vectors in the preset time range.
In one embodiment, the measuring apparatus comprises: the first delay sampling module is connected with the output end of the link to be tested and used for delaying the test data for a first preset time length to obtain a first delay vector; the second delay sampling module is connected with the first delay sampling module and is used for delaying the first delay vector for a second preset time length to obtain a second delay vector; the third delay sampling module is connected with the second delay sampling module and is used for delaying the second delay vector for a third preset time length to obtain a third delay vector; the processing module is respectively connected with the first delay sampling module, the second delay sampling module and the third delay sampling module, and is used for judging that the delay of the link to be tested reaches the standard when the value of the data in the first delay vector is the same as the value of the data in the second delay vector at least one moment in the preset time range and the value of the data in the second delay vector is different from the value of the data in the third delay vector; and when the value of the data in the first delay vector and the value of the data in the second delay vector at any time within the preset time range are different, and/or the value of the data in the second delay vector is the same as the value of the data in the third delay vector, judging that the delay of the link to be tested does not reach the standard.
In one embodiment, the first delayed sampling module comprises: the input end of the first buffer is connected with the output end of the link to be tested; the input end of the first register is connected with the output end of the first buffer; the second delayed sampling module comprises: the input end of the second buffer is connected with the output end of the first buffer; the input end of the second register is connected with the output end of the second buffer; the third delayed sampling module comprises: the input end of the third buffer is connected with the output end of the second buffer; the input end of the third register is connected with the output end of the third buffer; the processing module is respectively connected with the output ends of the first register, the second register and the third register.
In one embodiment, the third preset duration is equal to the duration of the preset time range.
In one embodiment, after determining that the delay of the link under test does not meet the standard, the processing module is further configured to: if the value of the data in the first delay vector and the value of the data in the second delay vector at any time within the preset time range are different, judging that the time delay of the link to be detected is greater than the standard maximum time delay; and if the value of the data in the second delay vector at any moment in the preset time range is the same as the value of the data in the third delay vector, judging that the time delay of the link to be tested is smaller than the standard minimum time delay.
In one embodiment, the processing module comprises: the first input end of the exclusive-nor gate is connected with the output end of the first delay sampling module, and the second input end of the exclusive-nor gate is connected with the output end of the second delay sampling module; the first input end of the exclusive-or gate is connected with the output end of the second delay sampling module, and the second input end of the exclusive-or gate is connected with the output end of the third delay sampling module; the judging unit is respectively connected with the output end of the exclusive-OR gate and is used for judging that the time delay of the link to be tested reaches the standard when the output of the exclusive-OR gate at least one moment in the preset time range is a high level signal and the output of the exclusive-OR gate is a high level signal; and when the output of the exclusive-OR gate at any time within the preset time range is a low level signal and/or the output of the exclusive-OR gate is a low level signal, judging that the time delay of the link to be tested does not reach the standard.
In one embodiment, the value of the first data of the test vector is random, and the bit width is the maximum input bit width of the link to be tested.
A method for link latency detection, the method comprising: inputting a test vector to a link to be tested, and acquiring test data obtained after the test vector passes through the link to be tested, wherein the test vector comprises a plurality of data which are sequentially arranged, and the values of two adjacent data are different; delaying the test data for different durations respectively to obtain a plurality of delay vectors; and determining whether the time delay of the link to be detected reaches the standard or not according to the relationship among the data of the plurality of delay vectors in the preset time range.
In one embodiment, the method further comprises: acquiring a preset circuit, wherein the preset circuit comprises a plurality of links; determining the theoretical time delay of each link; and taking the link with the theoretical time delay larger than a preset value as the link to be tested.
In one embodiment, the method further comprises: and applying environmental stress to the link to be tested while inputting the test vector to the link to be tested, wherein the environmental stress comprises at least one of a high-temperature environment, a low-temperature environment, a high-voltage environment, a low-voltage environment, a power supply interference environment and an electromagnetic interference environment.
According to the link delay detection system and method, the test vector is input to the link to be detected through the vector generation equipment connected with the input end of the link to be detected, the test vector is a group of data which are sequentially arranged, and values of two adjacent data are different. That is, the logic levels of adjacent clock cycles of the test vector are different, so that the logic levels of every two clock cycles can be changed, and the time delay of the link to be tested can be conveniently detected. Then, through the measuring equipment connected with the output end of the link to be tested, test data of the test vector passing through the link to be tested can be obtained, the test data are respectively delayed for different durations, a plurality of delay vectors can be obtained, and then whether the delay of the link to be tested reaches the standard or not is determined according to the relationship among the data of the plurality of delay vectors in a preset time range. Namely, when the data of the delay vectors in the preset time range meet the preset relation, the time delay of the link to be tested can be judged to reach the standard, otherwise, the time delay of the link to be tested is judged not to reach the standard. Through the measuring equipment, whether the time delay of the link to be detected reaches the standard can be judged only according to the test data output by the link to be detected, comparison with other standard data is not needed, resources are saved, whether the time delay of the link to be detected reaches the standard can be simply and reliably judged, and detection time is saved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the description of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the description below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a link delay detection system in an embodiment;
FIG. 2 is a schematic diagram of the structure of a measuring apparatus in one embodiment;
FIG. 3 is a timing diagram illustrating a case where the delay of the link under test is completely correct according to an embodiment;
fig. 4 is a schematic structural diagram of a link delay detection system in another embodiment;
FIG. 5 is a schematic view of the structure of a measuring apparatus in another embodiment;
FIG. 6 is a flow diagram of a method for link delay detection in one embodiment;
FIG. 7 is a flowchart of a method for screening links under test in one embodiment.
Description of the reference numerals: 10-vector generating equipment, 20-link to be tested, 30-measuring equipment, 31-first delay sampling module, 32-second delay sampling module, 33-third delay sampling module, 34-processing module, 100-starting time of a preset time range, 200-duration of the preset time range, 300-second preset duration, 310-first buffer, 320-second buffer, 330-third buffer, 311-first register, 321-second register, 331-third register, 341-exclusive or gate, 342-exclusive or gate and 343-judging unit.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments is understood to mean "electrical connection", "communication connection", or the like, if there is a transfer of electrical signals or data between the connected objects.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, as used in this specification, the term "and/or" includes any and all combinations of the associated listed items.
As described in the background art, in the method for detecting the delay of the link in the prior art, the actual delay of the link needs to be obtained through a simulation test, and the actual delay is compared with the preset delay, so as to determine whether the test of the link reaches the standard. The actual time delay obtained by simulation needs to be compared with the preset time delay to judge whether the time delay of the link reaches the standard, but the time delay of the link cannot be judged to reach the standard only according to the actual time delay obtained by simulation, so that the judgment needs to be carried out by means of the preset time delay information, the occupied resources are large, and the judgment is inconvenient.
Based on the reasons, the invention provides a link delay detection system and a link delay detection method, which can simply and conveniently detect whether the delay of a link reaches the standard.
In one embodiment, as shown in fig. 1, a link delay detection system is provided, the system comprising:
and the vector generation device 10 is connected with the input end of the link to be tested 20 and is used for inputting the test vector to the link to be tested 20.
Specifically, the test vector includes a plurality of data arranged in sequence, and values of two adjacent data are different. The test vectors are logic 1 and logic 0 data applied to the device pins for testing or operation each clock cycle. The data of the test vector is 0 or 1, and the 0 and 1 are arranged alternately, so that the output result of each clock period of the input link to be tested is ensured to jump, and the time delay information of the link to be tested is convenient to identify.
Specifically, the value of the first data of the test vector is random, and the bit width is the maximum input bit width of the link to be tested. The value of the first data of the test vector does not affect the detection result, and therefore, the first data can be a random value of 0 or 1, as long as the data of the test vector is ensured to be alternately arranged by 0 and 1. The bit width of the test vector is determined by the input bit width which can be received by the link to be tested, so that the detection result is more complete.
The measuring equipment 30 is connected with the output end of the link to be tested 20 and used for acquiring test data obtained by the test vector through the link to be tested 20; respectively delaying the test data for different durations to obtain a plurality of delay vectors; and determining whether the time delay of the link 20 to be detected reaches the standard or not according to the relationship among the data of the plurality of delay vectors in the preset time range.
Specifically, the same test data is delayed for different durations respectively to obtain a plurality of delay vectors, each delay vector corresponds to the corresponding test data delayed for a certain duration, and each delay vector is different.
Specifically, when the data of the plurality of delay vectors in the preset time range meet the preset relationship, the time delay of the link to be tested can be judged to reach the standard, otherwise, the time delay of the link to be tested can not reach the standard, and whether the time delay of the link to be tested reaches the standard can be judged only according to the test data output by the link to be tested without comparing with other standard data, so that resources are saved.
In this embodiment, a test vector is input to the link to be tested through a vector generation device connected to an input end of the link to be tested, the test vector is a group of data arranged in sequence, and values of two adjacent data are different. That is, the logic levels of adjacent clock cycles of the test vector are different, so that the logic levels of every two clock cycles can be changed, and the time delay of the link to be tested can be conveniently detected. Then, through the measuring equipment connected with the output end of the link to be tested, test data of the test vector passing through the link to be tested can be obtained, the test data are respectively delayed for different durations, a plurality of delay vectors can be obtained, and then whether the delay of the link to be tested reaches the standard or not is determined according to the relationship among the data of the plurality of delay vectors in a preset time range. That is, when the data of the plurality of delay vectors in the preset time range satisfy the preset relationship, the delay of the link to be measured can be judged to reach the standard, otherwise, the delay of the link to be measured is judged not to reach the standard. Through the measuring equipment, whether the time delay of the link to be detected reaches the standard can be judged only according to the test data output by the link to be detected, and comparison with other standard data is not needed, so that resources are saved, whether the time delay of the link to be detected reaches the standard can be simply and reliably judged, and the detection time is saved.
In one embodiment, as shown in FIG. 2, the measurement device 30 includes:
the first delay sampling module 31 is connected to the output end of the link to be tested, and is configured to delay the test data by a first preset duration to obtain a first delay vector.
And the second delay sampling module 32 is connected to the first delay sampling module 31, and is configured to delay the first delay vector by a second preset time length to obtain a second delay vector.
And a third delay sampling module 33, connected to the second delay sampling module 32, for delaying the second delay vector by a third preset time length to obtain a third delay vector.
And the processing module 34 is connected to the first delay sampling module 31, the second delay sampling module 32, and the third delay sampling module 33, respectively, and is configured to determine that the delay of the link to be detected reaches the standard when the value of the data in the first delay vector is the same as the value of the data in the second delay vector at least one time within the preset time range, and the value of the data in the second delay vector is different from the value of the data in the third delay vector. And when the value of the data in the first delay vector at any time within the preset time range is different from the value of the data in the second delay vector, and/or the value of the data in the second delay vector is the same as the value of the data in the third delay vector, judging that the delay of the link to be measured does not reach the standard.
Specifically, the duration of the preset time range is equal to a third preset duration. The starting time of the preset time range is the time when the value of the data in the second delay vector of the link to be detected is the standard delay jumps, that is, assuming that the delay of the link to be detected is completely correct, the link delay detection system in the application is adopted to obtain the standard second delay vector, and the time when the value of the data in the standard second delay vector jumps is used as the starting time of the preset time range.
For example, as shown in fig. 3, fig. 3 is a timing diagram when the time delay of the link to be measured is completely correct, and in the timing diagram of fig. 3, a timing diagram of a clock time, a timing diagram of a first delay vector, a timing diagram of a second delay vector, and a timing diagram of a third delay vector are sequentially provided from top to bottom, where a start time 100 of the preset time range is a time when a data value of the standard second delay vector changes, and a duration 200 of the preset time range is a third preset duration.
The duration of the preset time range is fixed, and the starting time is also fixed, so that when the time delay of the link to be tested changes, the jump time of 0/1 in the three delay vectors changes, and the data values of the three delay vectors in the preset time range change, and therefore, whether the time delay of the link to be tested reaches the standard can be judged.
For example, the table for determining whether the link to be tested meets the standard is shown in the following table.
Table one, link to be tested standard judgment table.
In this embodiment, values of the first delay vector, the second delay vector, and the third delay vector in a preset time range are compared, and if a value of data in the first delay vector is the same as a value of data in the second delay vector at least one time in the preset time range, and a value of data in the second delay vector is different from a value of data in the third delay vector, it is determined that the delay of the link to be measured reaches the standard. And if the value of the data in the first delay vector and the value of the data in the second delay vector at any time within the preset time range are different, and/or the value of the data in the second delay vector and the value of the data in the third delay vector are the same, judging that the delay of the link to be measured does not reach the standard. Therefore, three different delay vectors are obtained by delaying the test data for three different durations, and whether the delay of the link to be tested reaches the standard can be judged according to the three different delay vectors, so that the method is convenient and simple.
In one embodiment, as shown in fig. 4, the first delay sampling module 31 includes:
the input of the first buffer 310 is connected to the output of the link under test 20.
The input terminal of the first register 311 is connected to the output terminal of the first buffer 310.
The second delayed sampling module 32 includes:
and an input terminal of the second buffer 320 is connected to an output terminal of the first buffer 310.
And an input terminal of the second register 321 is connected to an output terminal of the second buffer 320.
The third delayed sampling module 33 includes:
and an input terminal of the third buffer 330 is connected to an output terminal of the second buffer 320.
And an input terminal of the third register 331 is connected to an output terminal of the third buffer 330.
The processing module 34 is connected to the output terminals of the first register 311, the second register 321, and the third register 331, respectively.
The buffer is a memory capable of performing high-speed data exchange, and is used as a delayer in this application, so that the time of the data delay arrival can be designed and adjusted according to actual needs. The register is a D flip-flop or other flip-flops with a storage function.
In this embodiment, three buffers are provided to delay the test data for three different durations to obtain three delay vectors, and the corresponding three registers are provided to acquire and temporarily store the three delay vectors. And receiving the three delay vectors through the processing module, and judging whether the delay of the link to be detected reaches the standard according to the three delay vectors.
In one embodiment, after determining that the delay of the link 20 to be tested does not meet the standard, the processing module 34 is further configured to perform the following steps:
and S100, if the value of the data in the first delay vector and the value of the data in the second delay vector at any moment in a preset time range are different, judging that the time delay of the link to be measured is greater than the standard maximum time delay.
Specifically, the second preset time length is greater than or equal to the theoretical maximum value which may occur when the standard maximum time delay time length is subtracted from the time delay of the link to be measured. That is, when the time delay of the link to be measured is larger, the maximum value which is probably generated in theory for the larger part of the time length is smaller than or equal to the second preset time length. Therefore, as long as the value of the data in the first delay vector and the value of the data in the second delay vector at any time within the preset time range are different, it can be determined that the delay is large.
And S120, if the value of the data in the second delay vector at any moment in the preset time range is the same as the value of the data in the third delay vector, judging that the time delay of the link to be tested is smaller than the standard minimum time delay.
Specifically, the standard minimum delay is a delay corresponding to a time when a value of data in a second delay vector of the standard delay jumps, and the standard maximum delay is a delay corresponding to a time when a value of data in a third delay vector of the standard delay jumps.
For example, as shown in fig. 3, fig. 3 is a timing chart when the time delay of the link to be tested is completely correct, wherein the starting time 100 and the preset time range 200 of the preset time range are fixed.
Therefore, when the value of the data in the first delay vector is different from the value of the data in the second delay vector at any time within the preset time range, the timing diagram representing the three delay vectors moves rightward by a certain distance, and the moving range is after the preset time range 200 until the time when the data value of the second delay vector jumps, which means that the delay of the link to be measured is greater than the preset time range 200, and the time delay range corresponding to the preset time range 200 is the standard time delay range. The time delay of the link to be tested is judged to be large. Moreover, the second preset time duration 300 is longer than the time duration of the link to be measured, which is longer than the time duration of the partial time duration of the standard time delay range, so that the situation that the whole timing diagram moves to the right until the values of the three time delay vectors are the same does not occur.
If the value of the data in the second delay vector at any time within the preset time range is the same as the value of the data in the third delay vector, the timing diagram of the three delay vectors moves leftwards for a certain distance, and the moving range is before the preset time range 200 until the time when the data value of the third delay vector jumps, which means that the delay of the link to be tested is smaller than the preset time range 200, the delay of the link to be tested is determined to be smaller.
In this embodiment, the value of the first delay vector, the second delay vector, and the third delay vector can be used to determine whether the delay of the link to be measured does not reach the time standard, and whether the delay of the link to be measured is large or small, so as to accurately determine the state of the link to be measured when the delay of the link to be measured does not reach the time standard.
In one embodiment, as shown in FIG. 5, the processing module 34 includes:
an exclusive-nor gate 341 having a first input connected to the output of the first delay sampling module 31 and a second input connected to the output of the second delay sampling module 32。
Specifically, the exclusive nor gate outputs a high level signal when the inputs are the same, and outputs a low level signal when the inputs are different.
And an exclusive or gate 342, a first input end of which is connected to the output end of the second delay sampling module 32, and a second input end of which is connected to the output end of the third delay sampling module 33.
Specifically, the exclusive or gate outputs a low level signal when the inputs are the same, and outputs a high level signal when the inputs are different.
The determining unit 343, which is connected to the output of the exclusive or gate 341 and the output of the exclusive or gate 342 respectively, is configured to determine that the time delay of the link 20 to be tested reaches the standard when the output of the exclusive or gate 341 is a high level signal and the output of the exclusive or gate 342 is a high level signal at least one time within a preset time range; when the output of the exclusive or gate 341 is a low level signal at any time within the preset time range, and/or the output of the exclusive or gate 342 is a low level signal, it is determined that the time delay of the link to be measured does not reach the standard.
In this embodiment, the values of the data of the first delay vector, the second delay vector, and the third delay vector are converted into logic levels by the exclusive or gate of the same or gate, so that whether the delay of the link to be detected reaches the standard can be simply and conveniently determined.
In one embodiment, as shown in fig. 6, a method for detecting a link delay is provided, where the method includes:
step S600, inputting a test vector to the link to be tested, and acquiring test data obtained after the test vector passes through the link to be tested.
Specifically, the test vector includes a plurality of data arranged in sequence, and values of two adjacent data are different.
Specifically, while inputting a test vector to a link to be tested, an environmental stress is applied to the link to be tested, wherein the environmental stress includes at least one of a high-temperature environment, a low-temperature environment, a high-voltage environment, a low-voltage environment, a power supply interference environment and an electromagnetic interference environment. Therefore, the work of the link to be tested in the environments can be simulated, and the reliability of the time delay of the link to be tested in actual operation can be evaluated.
Step S620, respectively delaying the test data for different durations to obtain a plurality of delay vectors.
And step S640, determining whether the time delay of the link to be detected reaches the standard according to the relationship between the data of the plurality of time delay vectors in the preset time range.
In this embodiment, a test vector is input to the link to be tested, the test vector is a group of data arranged in sequence, and values of two adjacent data are different. That is, the logic levels of adjacent clock cycles of the test vector are different, so that the logic levels of every two clock cycles can be changed, and the time delay of the link to be tested can be conveniently detected. And then obtaining test data of the test vector after passing through the link to be tested, delaying the test data by different durations respectively to obtain a plurality of delay vectors, and determining whether the delay of the link to be tested reaches the standard or not according to the relationship between the data of the plurality of delay vectors in a preset time range. That is, when the data of the plurality of delay vectors in the preset time range satisfy the preset relationship, the delay of the link to be measured can be judged to reach the standard, otherwise, the delay of the link to be measured is judged not to reach the standard. Whether the time delay of the link to be detected reaches the standard can be judged only according to the test data output by the link to be detected, and comparison with other standard data is not needed, so that resources are saved, whether the time delay of the link to be detected reaches the standard can be simply and reliably judged, and the detection time is saved.
In one embodiment, as shown in fig. 7, the link latency detection method further includes:
step S700, a preset circuit is obtained, where the preset circuit includes a plurality of links.
Specifically, after the circuit is designed, the design file in the form of verilog hdl (hardware description language) or VHDL (hardware description language) of the circuit is converted into a gate-level netlist, and then laid out on the FPGA, so that the circuit can be run on the FPGA. The circuit is designed to include a plurality of links.
And step S720, determining the theoretical time delay of each link.
Specifically, when a circuit is designed, theoretical time delay information of each link in the designed circuit, that is, estimated time delay information of each link, can be obtained through a design tool.
And step S740, taking the link with the theoretical time delay larger than the preset value as the link to be measured.
Specifically, after theoretical time delay information of each link is obtained, the links are sorted, and the link larger than a preset value is selected as the link to be tested. This is chosen because the link with the larger time delay has the largest influence on the operation timing of the whole circuit.
Specifically, before measuring the link to be measured, the layout of the link to be measured needs to be fixed, and the layout position of the link to be measured can be constrained and fixed by a UCF (user constraint file) in the FPGA.
In this embodiment, the preset circuit is screened to select the link to be tested that meets the requirement. Therefore, computing resources can be saved as much as possible, and links which have large influence on the working time sequence of the circuit are preferentially detected.
It should be understood that although the steps in the flowcharts of fig. 6 and 7 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 6 and 7 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternatively with other steps or at least some of the other steps or stages.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above may be implemented by hardware instructions of a computer program, which may be stored in a non-volatile computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), for example.
In the description herein, references to "some embodiments," "other embodiments," "desired embodiments," or the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A link delay detection system, the system comprising:
the device comprises a vector generation device and a test device, wherein the vector generation device is connected with an input end of a link to be tested and is used for inputting a test vector to the link to be tested, the test vector comprises a plurality of data which are sequentially arranged, and values of two adjacent data are different;
the measuring equipment is connected with the output end of the link to be tested and used for acquiring test data obtained by the test vector through the link to be tested; delaying the test data for different durations respectively to obtain a plurality of delay vectors; and determining whether the time delay of the link to be detected reaches the standard or not according to the relationship among the data of the plurality of delay vectors in the preset time range.
2. The system of claim 1, wherein the measurement device comprises:
the first delay sampling module is connected with the output end of the link to be tested and used for delaying the test data by a first preset time length to obtain a first delay vector;
the second delay sampling module is connected with the first delay sampling module and is used for delaying the first delay vector for a second preset time length to obtain a second delay vector;
the third delay sampling module is connected with the second delay sampling module and is used for delaying the second delay vector by a third preset time length to obtain a third delay vector;
a processing module, connected to the first delay sampling module, the second delay sampling module, and the third delay sampling module, respectively, and configured to determine that the delay of the link to be tested reaches the standard when a value of data in the first delay vector is the same as a value of data in the second delay vector and a value of data in the second delay vector is different from a value of data in the third delay vector at least one time within the preset time range; and when the value of the data in the first delay vector at any time within the preset time range is different from the value of the data in the second delay vector, and/or the value of the data in the second delay vector is the same as the value of the data in the third delay vector, judging that the delay of the link to be tested does not reach the standard.
3. The system of claim 2, wherein the first delayed sampling module comprises:
the input end of the first buffer is connected with the output end of the link to be tested;
the input end of the first register is connected with the output end of the first buffer;
the second delayed sampling module comprises:
the input end of the second buffer is connected with the output end of the first buffer;
the input end of the second register is connected with the output end of the second buffer;
the third delayed sampling module comprises:
the input end of the third buffer is connected with the output end of the second buffer;
the input end of the third register is connected with the output end of the third buffer;
the processing module is respectively connected with the output ends of the first register, the second register and the third register.
4. The system of claim 3, wherein the third predetermined duration is equal to the duration of the predetermined time range.
5. The system according to any of claims 2-4, wherein after determining that the latency of the link under test does not meet the standard, the processing module is further configured to:
if the value of the data in the first delay vector and the value of the data in the second delay vector at any time within the preset time range are different, judging that the time delay of the link to be tested is greater than the standard maximum time delay;
and if the value of the data in the second delay vector at any moment in the preset time range is the same as the value of the data in the third delay vector, judging that the time delay of the link to be tested is smaller than the standard minimum time delay.
6. The system according to any one of claims 2-4, wherein the processing module comprises:
the first input end of the exclusive-nor gate is connected with the output end of the first delay sampling module, and the second input end of the exclusive-nor gate is connected with the output end of the second delay sampling module;
the first input end of the exclusive-or gate is connected with the output end of the second delay sampling module, and the second input end of the exclusive-or gate is connected with the output end of the third delay sampling module;
the judging unit is respectively connected with the output end of the exclusive-OR gate and is used for judging that the time delay of the link to be tested reaches the standard when the output of the exclusive-OR gate at least one moment in the preset time range is a high level signal and the output of the exclusive-OR gate is a high level signal; and when the output of the exclusive-OR gate at any time within the preset time range is a low level signal and/or the output of the exclusive-OR gate is a low level signal, judging that the time delay of the link to be tested does not reach the standard.
7. The system according to any one of claims 1 to 4, wherein the first data of the test vector has a random value, and the bit width is the maximum input bit width of the link under test.
8. A method for detecting link delay, the method comprising:
inputting a test vector to a link to be tested, and acquiring test data obtained after the test vector passes through the link to be tested, wherein the test vector comprises a plurality of data which are sequentially arranged, and the values of two adjacent data are different;
delaying the test data for different durations respectively to obtain a plurality of delay vectors;
and determining whether the time delay of the link to be detected reaches the standard or not according to the relationship among the data of the plurality of delay vectors in the preset time range.
9. The method of claim 8, further comprising:
acquiring a preset circuit, wherein the preset circuit comprises a plurality of links;
determining the theoretical time delay of each link;
and taking the link with the theoretical time delay larger than a preset value as the link to be tested.
10. The method of claim 8, further comprising:
when the test vector is input into the link to be tested, environmental stress is applied to the link to be tested, wherein the environmental stress comprises at least one of a high-temperature environment, a low-temperature environment, a high-voltage environment, a low-voltage environment, a power supply interference environment and an electromagnetic interference environment.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016000423A1 (en) * | 2014-06-30 | 2016-01-07 | 中兴通讯股份有限公司 | Delay compensation method and device |
| CN112260890A (en) * | 2020-09-28 | 2021-01-22 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Digital array time delay measuring method |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016000423A1 (en) * | 2014-06-30 | 2016-01-07 | 中兴通讯股份有限公司 | Delay compensation method and device |
| CN112260890A (en) * | 2020-09-28 | 2021-01-22 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Digital array time delay measuring method |
Non-Patent Citations (1)
| Title |
|---|
| 逄锦昊 等: "基于FPGA的多路高速数据传输同步时延测量系统", 电子器件, no. 02 * |
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