CN114785715B - Link delay detection system and method - Google Patents
Link delay detection system and method Download PDFInfo
- Publication number
- CN114785715B CN114785715B CN202210253517.6A CN202210253517A CN114785715B CN 114785715 B CN114785715 B CN 114785715B CN 202210253517 A CN202210253517 A CN 202210253517A CN 114785715 B CN114785715 B CN 114785715B
- Authority
- CN
- China
- Prior art keywords
- delay
- link
- data
- vector
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000013598 vector Substances 0.000 claims abstract description 191
- 238000012360 testing method Methods 0.000 claims abstract description 88
- 238000005070 sampling Methods 0.000 claims description 48
- 239000000872 buffer Substances 0.000 claims description 20
- 238000012545 processing Methods 0.000 claims description 15
- 230000003111 delayed effect Effects 0.000 claims description 6
- 230000006353 environmental stress Effects 0.000 claims description 6
- 238000005259 measurement Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 7
- 238000013461 design Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0852—Delays
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
Abstract
The application relates to a link delay detection system and a link delay detection method. The system comprises: the vector generation device is connected with the input end of the link to be tested and is used for inputting a test vector to the link to be tested, wherein the test vector comprises a plurality of data which are sequentially arranged, and the values of two adjacent data are different; the measuring equipment is connected with the output end of the link to be measured and is used for acquiring test data obtained by the test vector passing through the link to be measured; respectively delaying the test data for different time lengths to obtain a plurality of delay vectors; and determining whether the time delay of the link to be tested reaches the standard according to the relation between the data of the delay vectors in the preset time range. The method can judge whether the time delay of the link to be detected meets the standard according to the test data output by the link to be detected, does not need to be compared with other standard data, saves resources, can simply and reliably judge whether the time delay of the link to be detected meets the standard, and saves detection time.
Description
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a system and a method for detecting link delay.
Background
With the development of field programmable gate array FPGA (Field Programmable Gate Array) technology, domestic FPGA chips are more and more complex, and the FPGA chips mainly comprise the following three parts: a configurable logic block CLB (configurable logic block), an input/output block (IOB) and programmable interconnect lines (programmable interconnect). The FPGA is designed with a hardware description language and then generates a bit stream file containing configuration information of all programmable logic modules through EDA (electronic design automation ) software. Each programmable logic module in the FPGA, such as CLB, IOB, and programmable interconnect, etc., has a signal transmission delay, and the delay of these modules varies with the manufacturing process of the FPGA chip, the working voltage, the temperature, etc., which makes it difficult to accurately calculate the signal transmission delay in the FPGA chip. The FPGA is a modularized IP core (Intellectual Property core), so that the cost of hardware development can be greatly reduced, the configuration is more flexible, the FPGA is widely applied to the fields of industry, aerospace, aviation, artificial intelligence and the like, whether the time sequence in the FPGA is accurate, the time delay is proper, whether the FPGA can normally operate or not is greatly influenced, and therefore, how to detect whether the time delay of a link in the FPGA reaches the standard is a problem to be solved at present.
Disclosure of Invention
Based on the above, it is necessary to provide a link delay detection system and method capable of simply and conveniently detecting whether the delay of the link reaches the standard only through the output delay of the link.
A link delay detection system, the system comprising: the vector generation device is connected with the input end of the link to be tested and is used for inputting a test vector to the link to be tested, wherein the test vector comprises a plurality of data which are sequentially arranged, and the values of two adjacent data are different; the measuring equipment is connected with the output end of the link to be tested and is used for acquiring test data obtained by the test vector passing through the link to be tested; respectively delaying the test data for different time lengths to obtain a plurality of delay vectors; and determining whether the time delay of the link to be tested reaches the standard according to the relation between the data of the delay vectors in the preset time range.
In one embodiment, the measuring device comprises: the first delay sampling module is connected with the output end of the link to be tested and is used for delaying the test data for a first preset duration to obtain a first delay vector; the second delay sampling module is connected with the first delay sampling module and is used for delaying the first delay vector for a second preset duration to obtain a second delay vector; the third delay sampling module is connected with the second delay sampling module and is used for delaying the second delay vector for a third preset duration to obtain a third delay vector; the processing module is respectively connected with the first delay sampling module, the second delay sampling module and the third delay sampling module and is used for judging that the time delay of the link to be tested reaches the standard when the value of the data in the first delay vector is the same as the value of the data in the second delay vector at least at one moment in the preset time range and the value of the data in the second delay vector is different from the value of the data in the third delay vector; and when the value of the data in the first delay vector is different from the value of the data in the second delay vector at any time within the preset time range, and/or the value of the data in the second delay vector is the same as the value of the data in the third delay vector, judging that the time delay of the link to be tested does not reach the standard.
In one embodiment, the first delay sampling module includes: the input end of the first buffer is connected with the output end of the link to be tested; the input end of the first register is connected with the output end of the first register; the second delay sampling module comprises: the input end of the second buffer is connected with the output end of the first buffer; the input end of the second register is connected with the output end of the second register; the third delay sampling module includes: the input end of the third buffer is connected with the output end of the second buffer; the input end of the third register is connected with the output end of the third register; the processing module is respectively connected with the output ends of the first register, the second register and the third register.
In one embodiment, the third preset duration is equal to a duration of the preset time range.
In one embodiment, after determining that the delay of the link under test does not reach the standard, the processing module is further configured to: if the value of the data in the first delay vector is different from the value of the data in the second delay vector at any time in the preset time range, judging that the delay of the link to be tested is larger than the standard maximum delay; if the value of the data in the second delay vector is the same as the value of the data in the third delay vector at any time in the preset time range, judging that the time delay of the link to be tested is smaller than the standard minimum time delay.
In one embodiment, the processing module includes: an exclusive-OR gate, wherein a first input end is connected with the output end of the first delay sampling module, and a second input end is connected with the output end of the second delay sampling module; the first input end of the exclusive-OR gate is connected with the output end of the second delay sampling module, and the second input end of the exclusive-OR gate is connected with the output end of the third delay sampling module; the judging unit is respectively connected with the output end of the exclusive-or gate and is used for judging that the time delay of the link to be tested reaches the standard when the output of the exclusive-or gate at least one moment in the preset time range is a high-level signal and the output of the exclusive-or gate is a high-level signal; and when the output of the exclusive-or gate at any time in the preset time range is a low-level signal and/or the output of the exclusive-or gate is a low-level signal, judging that the time delay of the link to be tested does not reach the standard.
In one embodiment, the first data of the test vector has a random value, and the bit width is the maximum input bit width of the link to be tested.
A method of link delay detection, the method comprising: inputting a test vector to a link to be tested, and obtaining test data obtained after the test vector passes through the link to be tested, wherein the test vector comprises a plurality of data which are sequentially arranged, and values of two adjacent data are different; respectively delaying the test data for different time lengths to obtain a plurality of delay vectors; and determining whether the time delay of the link to be tested reaches the standard according to the relation between the data of the delay vectors in the preset time range.
In one embodiment, the method further comprises: acquiring a preset circuit, wherein the preset circuit comprises a plurality of links; determining the theoretical time delay of each link; and taking the link with the theoretical time delay larger than a preset value as the link to be tested.
In one embodiment, the method further comprises: and simultaneously inputting the test vector to the link to be tested, and applying environmental stress to the link to be tested, wherein the environmental stress comprises at least one of a high-temperature environment, a low-temperature environment, a high-voltage environment, a low-voltage environment, a power supply interference environment and an electromagnetic interference environment.
According to the system and the method for detecting the link delay, the test vector is input to the link to be detected through the vector generating device connected with the input end of the link to be detected, the test vector is a group of data which are sequentially arranged, and the values of two adjacent data are different. The logic levels of adjacent clock cycles of the test vector are different, so that the logic levels of every two clock cycles can be changed, and the time delay of the link to be tested can be conveniently detected. Then through the measuring equipment connected with the output end of the link to be measured, the test data of the test vector after passing through the link to be measured can be obtained, the test data are respectively delayed for different time lengths, a plurality of delay vectors can be obtained, and then whether the delay of the link to be measured reaches the standard is determined according to the relation of the data of the delay vectors in a preset time range. When the data of the delay vectors in the preset time range meet the preset relation, the delay of the link to be tested can be judged to reach the standard, otherwise, the delay of the link to be tested is judged to not reach the standard. Through measuring equipment, can only according to the test data of the link output that awaits measuring, can judge whether the time delay of the link that awaits measuring is up to standard, need not to contrast with other standard data, saved the resource to can be simple reliable judge whether the time delay of the link that awaits measuring is up to standard, save the time of detection.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a link delay detection system in one embodiment;
FIG. 2 is a schematic diagram of a measuring device in one embodiment;
FIG. 3 is a timing diagram of one embodiment when the latency of the link under test is completely correct;
FIG. 4 is a schematic diagram of a link delay detection system according to another embodiment;
FIG. 5 is a schematic view of a measuring apparatus according to another embodiment;
FIG. 6 is a flow chart of a method of link delay detection in one embodiment;
fig. 7 is a flow chart of a method of screening links under test in one embodiment.
Reference numerals illustrate: 10-vector generating equipment, 20-links to be tested, 30-measuring equipment, 31-first delay sampling module, 32-second delay sampling module, 33-third delay sampling module, 34-processing module, 100-starting time of a preset time range, 200-duration of the preset time range, 300-second preset duration, 310-first buffer, 320-second buffer, 330-third buffer, 311-first register, 321-second register, 331-third register, 341-exclusive-or gate, 342-exclusive-or gate and 343-judging unit.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that the terms "first," "second," and the like, as used herein, may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments should be understood as "electrical connection", "communication connection", and the like if there is transmission of electrical signals or data between objects to be connected.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
As described in the background art, in the method for detecting the time delay of the link in the prior art, the actual time delay of the link needs to be obtained through a simulation test, and the actual time delay is compared with the preset time delay to determine whether the test of the link meets the standard. The actual time delay obtained through simulation is compared with the preset time delay to judge whether the time delay of the link meets the standard or not, and whether the time delay of the link meets the standard or not cannot be judged according to the actual time delay obtained through simulation, so that judgment is carried out by means of the preset time delay information, occupied resources are large, and judgment is inconvenient.
Based on the reasons, the invention provides a link delay detection system and a link delay detection method which can simply and conveniently detect whether the delay of a link reaches the standard.
In one embodiment, as shown in fig. 1, a link delay detection system is provided, the system comprising:
the vector generating device 10 is connected to the input end of the link 20 to be tested, and is used for inputting the test vector to the link 20 to be tested.
Specifically, the test vector includes a plurality of data arranged in sequence, and the values of two adjacent data are different. The test vectors are logic 1 and logic 0 data for test or operation applied to the device pins for each clock cycle. The data of the test vector is 0 or 1, and the 0 and the 1 are alternately arranged, so that the output result of each clock cycle of the input link to be tested is ensured to be jumped, and the delay information of the link to be tested is conveniently identified.
Specifically, the value of the first data of the test vector is random, and the bit width is the maximum input bit width of the link to be tested. The value of the first data of the test vector does not affect the detection result, and therefore, the value can be a random value of 0 or 1, so long as the data of the test vector is ensured to be alternately arranged with 0 and 1. The bit width of the test vector is determined by the input bit width which can be received by the link to be tested, so that the detection result is more complete.
The measuring equipment 30 is connected with the output end of the link 20 to be measured and is used for acquiring test data obtained by the test vector passing through the link 20 to be measured; respectively delaying the test data for different time lengths to obtain a plurality of delay vectors; according to the relationship between the data of the delay vectors in the preset time range, whether the delay of the link 20 to be tested reaches the standard is determined.
Specifically, the same test data is delayed for different time periods respectively, so that a plurality of delay vectors are obtained, each delay vector corresponds to the corresponding test data delayed for a certain time period, and each delay vector is different.
Specifically, when the data of the delay vectors in the preset time range meet the preset relation, the delay of the link to be tested can be judged to reach the standard, otherwise, the delay of the link to be tested is judged to not reach the standard, and whether the delay of the link to be tested reaches the standard can be judged only according to the test data output by the link to be tested, and the comparison with other standard data is not needed, so that resources are saved.
In this embodiment, a test vector is input to the link to be tested through a vector generating device connected to the input end of the link to be tested, the test vector is a group of data sequentially arranged, and values of two adjacent data are different. The logic levels of adjacent clock cycles of the test vector are different, so that the logic levels of every two clock cycles can be changed, and the time delay of the link to be tested can be conveniently detected. Then through the measuring equipment connected with the output end of the link to be measured, the test data of the test vector after passing through the link to be measured can be obtained, the test data are respectively delayed for different time lengths, a plurality of delay vectors can be obtained, and then whether the delay of the link to be measured reaches the standard is determined according to the relation of the data of the delay vectors in a preset time range. When the data of the delay vectors in the preset time range meet the preset relation, the delay of the link to be tested can be judged to reach the standard, otherwise, the delay of the link to be tested is judged to not reach the standard. Through measuring equipment, can only according to the test data of the link output that awaits measuring, can judge whether the time delay of awaiting measuring the link is up to standard, need not to contrast with other standard data to save the resource, and can simply reliable judge whether the time delay of awaiting measuring the link is up to standard, saved the time of detection.
In one embodiment, as shown in FIG. 2, the measurement device 30 includes:
the first delay sampling module 31 is connected to the output end of the link to be tested, and is configured to delay the test data by a first preset duration, so as to obtain a first delay vector.
The second delay sampling module 32 is connected to the first delay sampling module 31, and is configured to delay the first delay vector by a second preset duration to obtain a second delay vector.
And the third delay sampling module 33 is connected with the second delay sampling module 32 and is used for delaying the second delay vector by a third preset duration to obtain a third delay vector.
The processing module 34 is respectively connected with the first delay sampling module 31, the second delay sampling module 32 and the third delay sampling module 33, and is configured to determine that the delay of the link to be tested reaches the standard when the value of the data in the first delay vector is the same as the value of the data in the second delay vector at least one moment in the preset time range and the value of the data in the second delay vector is different from the value of the data in the third delay vector. And when the value of the data in the first delay vector is different from the value of the data in the second delay vector at any time within the preset time range and/or the value of the data in the second delay vector is the same as the value of the data in the third delay vector, judging that the time delay of the link to be tested does not reach the standard.
Specifically, the duration of the preset time range is equal to the third preset duration. The starting time of the preset time range is the time when the value of the data in the second delay vector with the standard delay of the link to be tested jumps, namely, the time when the value of the data in the second delay vector with the standard delay jumps is taken as the starting time of the preset time range by adopting the link delay detection system in the application to obtain the standard second delay vector, wherein the time when the delay of the link to be tested is completely correct is assumed.
For example, as shown in fig. 3, fig. 3 is a timing chart when the time delay of the link to be tested is completely correct, in the timing chart of fig. 3, the timing chart of the clock time, the timing chart of the first delay vector, the timing chart of the second delay vector, and the timing chart of the third delay vector are sequentially from top to bottom, wherein the starting time 100 of the preset time range is the time when the data value of the standard second delay vector changes, and the duration 200 of the preset time range is the third preset duration.
The duration of the preset time range is fixed, and the starting time is also fixed, so that when the time delay of the link to be tested changes, the jump time of 0/1 of the three delay vectors changes, and the data values of the three delay vectors in the preset time range change, so that whether the time delay of the link to be tested reaches the standard can be judged.
Illustratively, a table for determining whether the link under test meets the standard is shown in table one below.
And a first table and a link to be tested reach the standard judgment table.
In this embodiment, the values of the first delay vector, the second delay vector and the third delay vector in the preset time range are compared, and if the value of the data in the first delay vector is the same as the value of the data in the second delay vector at least at one moment in the preset time range, and the value of the data in the second delay vector is different from the value of the data in the third delay vector, the time delay of the link to be tested is determined to reach the standard. If the value of the data in the first delay vector is different from the value of the data in the second delay vector at any time within the preset time range and/or the value of the data in the second delay vector is the same as the value of the data in the third delay vector, judging that the time delay of the link to be tested does not reach the standard. Therefore, only by delaying the test data for three different time periods to obtain three different delay vectors, and according to the three different delay vectors, whether the delay of the link to be tested reaches the standard can be judged, and the method is convenient and simple.
In one embodiment, as shown in fig. 4, the first delay sampling module 31 includes:
the input of the first buffer 310 is connected to the output of the link under test 20.
The input end of the first register 311 is connected to the output end of the first register 310.
The second delay sampling module 32 includes:
the input of the second buffer 320 is connected to the output of the first buffer 310.
The input end of the second register 321 is connected to the output end of the second register 320.
The third delay sampling module 33 includes:
the input of the third buffer 330 is connected to the output of the second buffer 320.
The input end of the third register 331 is connected to the output end of the third register 330.
The processing module 34 is connected to the output ends of the first register 311, the second register 321 and the third register 331.
The buffer is a memory capable of performing high-speed data exchange, and is used as a delay device in the application, and specifically, the time for reaching the data delay can be designed and adjusted according to actual needs. The register is a D flip-flop or other flip-flop with a storage function.
In this embodiment, by setting three buffers, test data is delayed for three different durations to obtain three delay vectors, and by setting three corresponding registers, three delay vectors can be collected and temporarily stored. And receiving the three delay vectors through the processing module, and judging whether the delay of the link to be tested reaches the standard according to the three delay vectors.
In one embodiment, after determining that the delay of the link under test 20 does not reach the standard, the processing module 34 is further configured to perform the following steps:
s100, if the value of the data in the first delay vector is different from the value of the data in the second delay vector at any time in the preset time range, judging that the delay of the link to be tested is larger than the standard maximum delay.
Specifically, the second preset time length is greater than or equal to the theoretical maximum value which may occur when the standard maximum time delay time length is subtracted from the time delay of the link to be measured. I.e. when the delay of the link to be measured is larger, the maximum value which can occur in theory of the larger time length is smaller than or equal to the second preset time length. Therefore, if the value of the data in the first delay vector is different from the value of the data in the second delay vector at any time in the preset time range, the delay deviation can be judged.
And S120, if the value of the data in the second delay vector is the same as the value of the data in the third delay vector at any time in the preset time range, judging that the delay of the link to be tested is smaller than the standard minimum delay.
Specifically, the standard minimum time delay is the time delay corresponding to the time when the value of the data in the second time delay vector of the standard time delay jumps, and the standard maximum time delay is the time delay corresponding to the time when the value of the data in the third time delay vector of the standard time delay jumps.
As shown in fig. 3, fig. 3 is a timing chart when the delay of the link to be measured is completely correct, wherein the starting time 100 of the preset time range and the preset time range 200 are both fixed.
Therefore, when the value of the data in the first delay vector is different from the value of the data in the second delay vector at any time within the preset time range, the time sequence diagram representing the three delay vectors is moved to the right by a distance as a whole, and the moving range is after the preset time range 200 until the time when the value of the data of the second delay vector jumps, which means that the time delay of the link to be tested is greater than the preset time range 200, and the time delay range corresponding to the preset time range 200 is the standard time delay range. And judging that the time delay of the link to be tested is larger. And, the second preset duration 300 is longer than the duration of most of the time when the time delay of the link to be tested is longer than the standard time delay range, so that the situation that the time sequence diagram moves to the right as a whole and the values of three time delay vectors are the same is avoided.
The value of the data in the second delay vector at any time within the preset time range is the same as the value of the data in the third delay vector, the time sequence diagram representing the three delay vectors is moved leftwards by a certain distance as a whole, the moving range is before the time when the data value of the third delay vector jumps is in the preset time range 200, which means that the time delay of the link to be tested is smaller than the preset time range 200, and the time delay of the link to be tested is judged to be smaller.
In this embodiment, by the values of the first delay vector, the second delay vector and the third delay vector, it can be determined whether the delay of the link to be measured is larger or smaller when the delay of the link to be measured does not reach the standard, so that the state when the delay of the link to be measured does not reach the standard can be accurately determined.
In one embodiment, as shown in FIG. 5, the processing module 34 includes:
exclusive nor gate 341The first input end is connected with the output end of the first delay sampling module 31, and the second input end is connected with the output end of the second delay sampling module 32。
Specifically, the exclusive-or gate outputs a high-level signal when inputs are the same, and outputs a low-level signal when inputs are different.
Exclusive or gate 342 has a first input connected to the output of second delay sampling module 32 and a second input connected to the output of third delay sampling module 33.
Specifically, the exclusive or gate outputs a low level signal when the inputs are the same, and outputs a high level signal when the inputs are different.
The judging unit 343 is respectively connected to the output end of the exclusive-or gate 341 and the output end of the exclusive-or gate 342, and is configured to judge that the time delay of the link 20 to be tested reaches the standard when the output of the exclusive-or gate 341 at least one moment in the preset time range is a high level signal and the output of the exclusive-or gate 342 is a high level signal; when the output of the exclusive-or gate 341 at any time within the preset time range is a low level signal and/or the output of the exclusive-or gate 342 is a low level signal, it is determined that the delay of the link to be tested does not reach the standard.
In this embodiment, the exclusive or gate of the exclusive or gate converts the values of the data of the first delay vector, the second delay vector and the third delay vector into logic levels, so that whether the delay of the link to be tested reaches the standard can be simply and conveniently determined.
In one embodiment, as shown in fig. 6, a link delay detection method is provided, which includes:
step S600, inputting a test vector to the link to be tested, and obtaining test data obtained after the test vector passes through the link to be tested.
Specifically, the test vector includes a plurality of data arranged in sequence, and the values of two adjacent data are different.
Specifically, while inputting a test vector to a link to be tested, an environmental stress is applied to the link to be tested, wherein the environmental stress includes at least one of a high temperature environment, a low temperature environment, a high voltage environment, a low voltage environment, a power supply interference environment, and an electromagnetic interference environment. Therefore, the working of the link to be tested under the environments can be simulated, and the reliability of the time delay of the link to be tested in actual use can be estimated.
Step S620, respectively delaying the test data for different time periods to obtain a plurality of delay vectors.
Step S640, determining whether the time delay of the link to be tested reaches the standard according to the relationship between the data of the delay vectors in the preset time range.
In this embodiment, by inputting a test vector to the link to be tested, the test vector is a group of data sequentially arranged, and values of two adjacent data are different. The logic levels of adjacent clock cycles of the test vector are different, so that the logic levels of every two clock cycles can be changed, and the time delay of the link to be tested can be conveniently detected. And then obtaining test data of the test vector after passing through the link to be tested, respectively delaying the test data for different time lengths to obtain a plurality of delay vectors, and then determining whether the delay of the link to be tested reaches the standard according to the relationship between the data of the delay vectors in a preset time range. When the data of the delay vectors in the preset time range meet the preset relation, the delay of the link to be tested can be judged to reach the standard, otherwise, the delay of the link to be tested is judged to not reach the standard. The method can judge whether the time delay of the link to be tested reaches the standard or not only according to the test data output by the link to be tested, and does not need to be compared with other standard data, thereby saving resources, simply and reliably judging whether the time delay of the link to be tested reaches the standard or not, and saving the detection time.
In one embodiment, as shown in fig. 7, the link delay detection method further includes:
in step S700, a preset circuit is obtained, and the preset circuit includes a plurality of links.
Specifically, after the circuit is designed, a design file in the form of verilog hdl (hardware description language) or VHDL (hardware description language) of the circuit is converted into a form of a gate level netlist, and then laid out on an FPGA, i.e., the circuit can be run on the FPGA. The circuit is designed to include a plurality of links.
In step S720, the theoretical delay of each link is determined.
Specifically, when designing a circuit, theoretical time delay information of each link in the designed circuit, namely estimated time delay information of each link, can be obtained through a design tool.
Step S740, taking the link with theoretical time delay larger than the preset value as the link to be tested.
Specifically, after the theoretical time delay information of each link is obtained, the theoretical time delay information is sequenced, and links with the values larger than a preset value are selected as links to be tested. This is chosen because the link with the greater delay has the greatest effect on the timing of operation of the overall circuit.
Specifically, before measuring a link to be measured, the layout of the link to be measured needs to be fixed, and the layout position of the link to be measured can be restrained and fixed through UCF (user restraint file) in the FPGA.
In this embodiment, the preset circuit is screened to select the link to be tested meeting the requirement. Therefore, the calculation resources can be saved as much as possible, and the link with larger influence on the working time sequence of the circuit is preferentially detected.
It should be understood that, although the steps in the flowcharts of fig. 6 and 7 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 6, 7 may include steps or stages that are not necessarily performed at the same time, but may be performed at different times, or the order in which the steps or stages are performed is not necessarily sequential, but may be performed in rotation or alternatively with at least some of the other steps or stages.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, or the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory. By way of illustration, and not limitation, RAM can be in the form of a variety of forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), and the like.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A link delay detection system, the system comprising:
the vector generation device is connected with the input end of the link to be tested and is used for inputting a test vector to the link to be tested, wherein the test vector comprises a plurality of data which are sequentially arranged, and the values of two adjacent data are different;
a measurement device, the measurement device comprising:
the first delay sampling module is connected with the output end of the link to be tested and is used for acquiring test data obtained by the test vector passing through the link to be tested, and delaying the test data for a first preset duration to obtain a first delay vector;
the second delay sampling module is connected with the first delay sampling module and is used for delaying the first delay vector for a second preset duration to obtain a second delay vector;
the third delay sampling module is connected with the second delay sampling module and is used for delaying the second delay vector for a third preset duration to obtain a third delay vector;
the processing module is respectively connected with the first delay sampling module, the second delay sampling module and the third delay sampling module and is used for judging that the time delay of the link to be tested reaches the standard when the value of the data in the first delay vector is the same as the value of the data in the second delay vector at least at one moment in a preset time range and the value of the data in the second delay vector is different from the value of the data in the third delay vector; and when the value of the data in the first delay vector is different from the value of the data in the second delay vector at any time within the preset time range, and/or the value of the data in the second delay vector is the same as the value of the data in the third delay vector, judging that the time delay of the link to be tested does not reach the standard, wherein the duration of the preset time range is equal to the third preset duration, and the starting time of the preset time range is the time when the value of the data in the second delay vector with the standard time delay of the link to be tested jumps.
2. The system of claim 1, wherein the first delayed sampling module comprises:
the input end of the first buffer is connected with the output end of the link to be tested;
the input end of the first register is connected with the output end of the first register;
the second delay sampling module comprises:
the input end of the second buffer is connected with the output end of the first buffer;
the input end of the second register is connected with the output end of the second register;
the third delay sampling module includes:
the input end of the third buffer is connected with the output end of the second buffer;
the input end of the third register is connected with the output end of the third register;
the processing module is respectively connected with the output ends of the first register, the second register and the third register.
3. The system of claim 2, wherein the third predetermined time period is equal to a time period of the predetermined time range.
4. The system of claim 1, wherein after determining that the delay of the link under test does not reach the standard, the processing module is further configured to:
if the value of the data in the first delay vector is different from the value of the data in the second delay vector at any time within the preset time range, judging that the time delay of the link to be tested is larger than the standard maximum time delay, wherein the standard maximum time delay is the time delay corresponding to the time when the value of the data in the third delay vector of the standard time delay jumps.
5. The system of claim 4, wherein the processing module is further configured to, in the event that a condition is not satisfied that the value of the data in the first delay vector is different from the value of the data in the second delay vector at any time within the preset time range:
if the value of the data in the second delay vector at any time within the preset time range is the same as the value of the data in the third delay vector, determining that the delay of the link to be tested is smaller than the standard minimum delay, wherein the standard minimum delay is the delay corresponding to the time when the value of the data in the second delay vector with the standard delay jumps.
6. The system of any of claims 2-5, wherein the processing module comprises:
an exclusive-OR gate, wherein a first input end is connected with the output end of the first delay sampling module, and a second input end is connected with the output end of the second delay sampling module;
the first input end of the exclusive-OR gate is connected with the output end of the second delay sampling module, and the second input end of the exclusive-OR gate is connected with the output end of the third delay sampling module;
the judging unit is respectively connected with the output end of the exclusive-or gate and is used for judging that the time delay of the link to be tested reaches the standard when the output of the exclusive-or gate at least one moment in the preset time range is a high-level signal and the output of the exclusive-or gate is a high-level signal; and when the output of the exclusive-or gate at any time in the preset time range is a low-level signal and/or the output of the exclusive-or gate is a low-level signal, judging that the time delay of the link to be tested does not reach the standard.
7. The system of any of claims 1-5, wherein the first data of the test vector has a random value and a bit width that is the maximum input bit width of the link under test.
8. A method for detecting link delay, the method comprising:
inputting a test vector to a link to be tested, and obtaining test data obtained after the test vector passes through the link to be tested, wherein the test vector comprises a plurality of data which are sequentially arranged, and values of two adjacent data are different;
obtaining test data obtained by the test vector through the link to be tested, and delaying the test data for a first preset duration to obtain a first delay vector;
delaying the first delay vector for a second preset time length to obtain a second delay vector;
delaying the second delay vector for a third preset duration to obtain a third delay vector;
when the value of the data in the first delay vector is the same as the value of the data in the second delay vector at least at one moment in a preset time range, and the value of the data in the second delay vector is different from the value of the data in the third delay vector, judging that the time delay of the link to be tested reaches the standard;
when the value of the data in the first delay vector is different from the value of the data in the second delay vector at any time within the preset time range, and/or the value of the data in the second delay vector is the same as the value of the data in the third delay vector, judging that the time delay of the link to be tested is not up to standard, wherein the duration of the preset time range is equal to the third preset duration, the starting time of the preset time range is the time when the value of the data in the second delay vector with the link to be tested as the standard time delay jumps, the duration of the preset time range is equal to the third preset duration, and the starting time of the preset time range is the time when the value of the data in the second delay vector with the link to be tested as the standard time delay jumps.
9. The method of claim 8, wherein the method further comprises:
acquiring a preset circuit, wherein the preset circuit comprises a plurality of links;
determining the theoretical time delay of each link;
and taking the link with the theoretical time delay larger than a preset value as the link to be tested.
10. The method of claim 8, wherein the method further comprises:
and simultaneously inputting the test vector to the link to be tested, and applying environmental stress to the link to be tested, wherein the environmental stress comprises at least one of a high-temperature environment, a low-temperature environment, a high-voltage environment, a low-voltage environment, a power supply interference environment and an electromagnetic interference environment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210253517.6A CN114785715B (en) | 2022-03-15 | 2022-03-15 | Link delay detection system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210253517.6A CN114785715B (en) | 2022-03-15 | 2022-03-15 | Link delay detection system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114785715A CN114785715A (en) | 2022-07-22 |
| CN114785715B true CN114785715B (en) | 2024-03-26 |
Family
ID=82424794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210253517.6A Active CN114785715B (en) | 2022-03-15 | 2022-03-15 | Link delay detection system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114785715B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016000423A1 (en) * | 2014-06-30 | 2016-01-07 | 中兴通讯股份有限公司 | Delay compensation method and device |
| CN112260890A (en) * | 2020-09-28 | 2021-01-22 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Digital array time delay measuring method |
-
2022
- 2022-03-15 CN CN202210253517.6A patent/CN114785715B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016000423A1 (en) * | 2014-06-30 | 2016-01-07 | 中兴通讯股份有限公司 | Delay compensation method and device |
| CN112260890A (en) * | 2020-09-28 | 2021-01-22 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Digital array time delay measuring method |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA的多路高速数据传输同步时延测量系统;逄锦昊 等;电子器件(第02期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114785715A (en) | 2022-07-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9495492B1 (en) | Implementing synchronous triggers for waveform capture in an FPGA prototyping system | |
| US8336010B1 (en) | Design-specific on chip variation de-rating factors for static timing analysis of integrated circuits | |
| US20080177488A1 (en) | Method and apparatus for analyzing power consumption | |
| US8401828B1 (en) | Methods and systems for analog object fetch in mixed-signal simulation | |
| CA2399670A1 (en) | Method and apparatus for modeling and simulating the effects of bridge defects in integrated circuits | |
| CN109445365B (en) | Screening test method of FPGA embedded multiplier | |
| CN104461812A (en) | Method for constructing UVM verification component by utilizing existing Verilog BFM | |
| US8060847B2 (en) | Clock model for formal verification of a digital circuit description | |
| US20050228616A1 (en) | Method and system for providing fast design for testability prototyping in integrated circuit designs | |
| CN114280454A (en) | Chip testing method and device, chip testing machine and storage medium | |
| US20060026543A1 (en) | Accurate timing analysis of integrated circuits when combinatorial logic offers a load | |
| Ruan et al. | A Built-In Self-Test (BIST) system with non-intrusive TPG and ORA for FPGA test and diagnosis | |
| CN109901049B (en) | Method and device for detecting asynchronous path in time sequence path for integrated circuit | |
| US6077305A (en) | Latch inference using dataflow analysis | |
| EP3944126A1 (en) | Methods and systems for verifying a property of an integrated circuit hardware design using a quiescent state | |
| CN107784185B (en) | Method and device for extracting pseudo path in gate-level netlist and terminal equipment | |
| EP2824466B1 (en) | Multi-tier field-programmable gate array hardward requirements assessment and verification for airborne electronic systems | |
| CN114785715B (en) | Link delay detection system and method | |
| Srivastava et al. | Interdependent latch setup/hold time characterization via Euler-Newton curve tracing on state-transition equations | |
| US9057765B2 (en) | Scan compression ratio based on fault density | |
| US20100131910A1 (en) | Simulating Scan Tests with Reduced Resources | |
| CN113609804B (en) | Case generation method and device, test method and testability design method | |
| CN114662429A (en) | Non-destructive read back and write back for integrated circuit devices | |
| WO2022081898A1 (en) | High-speed functional protocol based test and debug | |
| Hamad et al. | Efficient multilevel formal analysis and estimation of design vulnerability to single event transients |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |