JP2001155043A - Timing check method for logic simulation and recording medium with recorded timing check method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output only a true error by removing a pseudo timing check error in an event-driven type logic simulation. SOLUTION: When a timing error is discriminated in a timing check, flag information is added together with timing error information and written in a temporary file 11. A logical operation value is propagated as a state value with the flag information, and when the expected value of a verification pattern is a non-fixed value, the state value is scheduled as it is. When the expected value is not the non-fixed value, the flag information added to that state value is written in an error output flag file 13. When the logic simulation is finished, only the timing error information corresponding to the flag information written in the error output flag file 13 is extracted out of the temporary file 11, written in a result file 12 and outputted so that the pseudo error can be removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing check method in a logic simulation, and more particularly to a timing check method capable of preventing a pseudo timing error from being mixed into an error result, and a computer-readable recording recording the timing check method. Regarding the medium.

[0002]

2. Description of the Related Art In recent years, with the increase in the scale of LSIs, the number of internal sequential circuit cells (hereinafter, referred to as circuit internal cells) having timing specifications included in circuits has been rapidly increasing. Along with this, the number of timing errors detected in the logic simulation also increases, and at the same time, the number of pseudo timing errors (hereinafter referred to as pseudo errors) which are determined to be errors in the simulation but do not cause any problem in actual operation increases. ing. For this reason, after execution of the logic simulation, a large amount of time is spent on the process of determining whether the error presented in the timing error report is a pseudo error or a true error. To determine whether the reported timing error is a pseudo error or a true error, refer to the cell name inside the circuit where the error occurred from the error information in the simulation result file, identify the cell in which the error occurred, and re-simulate Then, it is necessary to obtain signal change information around the error-occurring cell and analyze the propagation path and operation state of the output state value of the error-occurring cell from the obtained signal change information. The criteria for determining the timing error in the logic simulation as a pseudo error are as follows: (1) The output state value “X” of the error cell does not propagate to the external output terminal of the circuit until the verification pattern ends. (2) Even if the output state value “X” of the error cell propagates to the external output terminal of the circuit, the state value of the expected output value is an indefinite value “X” and the state value determined in actual operation is not expected. . There are two ways. Since the circuit designer must determine whether each of a number of timing errors is true or false through the above-described determination process,
It took a lot of time.

A timing check method using a logic simulator to which timing error information reporting means is added based on an event driven logic simulator described in Japanese Patent Application Laid-Open No. 6-4614 will be described as a conventional example. The mixing will be described.

FIG. 7A is a configuration diagram of an event-driven type logic simulator, and FIG. 7B is a diagram showing correspondence between status values handled in the logic simulation and their contents. FIG. 8 is a process flowchart of a conventional event-driven logic simulation. FIG. 9A is an example of a circuit diagram of a circuit to be simulated, and FIG.
Is a data flip-flop (DF) in the circuit of FIG.
F) is a diagram showing the truth value of the selector and the truth value of the selector,
(C) is a diagram showing operation timing specifications of the DFF. First, the configuration of the simulator is described with reference to FIG. 7, and then the simulation flow of FIG. 8 is described. When the circuit of FIG. 9 is simulated, a pseudo error occurs.
A description will be given of a state of being mixed in the error report.

In FIG. 7A, circuit data 1 includes:
The circuit connection information of the designed circuit, for example, an expression for the simulator of the circuit diagram of FIG. 9A is stored. The verification pattern 2 stores operation verification input signal data of the circuit data 1. The library 3 stores logic information of a circuit internal cell, for example, DFF of FIG. 9B, truth value information of a selector, and the like. The circuit SDF4 is a delay timing information file in which an internal delay value, a timing specification, a wiring delay value between cells, and the like of each cell used in the circuit data 1 are defined. The timing specification of the DFF shown in FIG. Is stored here. The simulator main body 5 reads data from the circuit data 1, the verification pattern 2, the library 3, and the circuit SDF 4, executes a logic simulation including a timing check, a logical operation, and a state value schedule, and outputs an execution result including error information to a result file 12. Output to

The simulation is performed in an event-driven system in which an event, which is a signal change, is detected and executed, and the possible state values at the input terminal, the output terminal, and the input / output of the internal cell are shown in FIG. It is as follows. “1”
Indicates a high level, "0" indicates a low level, "Z" indicates a high impedance state, "H", "L", "W".
Are weak pull-up state, weak pull-down state,
Either weak pull-up or pull-down indicates an uncertain state, and “X” indicates a state in which either the high level or the low level is indeterminate.

Next, a conventional timing check method will be described with reference to FIG. In step 181, an input event input from the verification pattern 2, that is, a change in the input signal, for a cell in the simulation circuit input from the circuit data 1 to the simulator body 5 is detected,
In step 182, it is determined whether the input event is an event change in a circuit internal cell or an input / output terminal cell event change. Step 18 if the event change of the cell inside the circuit
The process proceeds to timing check 3 to extract the input event time difference of the cell.

The extracted input event time difference is calculated by the circuit SDF.
If the timing specifications in 4 are not met,
In step 184, it is determined that there is a timing error, and the process proceeds to timing error processing in step 186. The timing error information such as the timing error occurrence time, the circuit internal cell name, the extracted input event time difference, and the timing specification is temporarily stored as a temporary file. After writing to the file 11, an indefinite value "X" which is an output state value indicating occurrence of a timing error is output to a storage unit (not shown) in the simulator body 5. Then, the process proceeds to step 187, where a delay value is added.
Schedule output state values with.

If the input event time difference extracted in step 183 satisfies the timing specification, it is determined in step 184 that there is no timing error,
The operation proceeds to the arithmetic processing of step 185. In step 185, first, the input state value of the cell is input, a logical operation is performed based on the input state value and the logical information of the library 3, and the output state value of the operation result is output to the storage unit in the simulator. . At step 187, a delay value is added based on the delay timing information of the circuit SDF4, and at step 188
Schedule output state values with.

If it is determined in step 182 that the input event is an event change of an input / output terminal cell, the flow advances to step 188 to schedule the state value as it is.

The status value scheduled in step 188 is written to a temporary file as a calculation result. This processing is repeated until the end of the pattern stored in the verification pattern 2 is detected in step 189, and when the end of the pattern is detected, the process proceeds to step 190, where the timing error information stored in the temporary file 11 is transferred to the result file 12 And ends the processing. Next, FIG.
(A) DFF (A1) having a circuit internal cell name of A1, DFF (A2) having a circuit internal cell name of A2, DFF (A3) having a circuit internal cell name of A3, and A4 having a circuit internal cell name of A4
As an example, an internal circuit composed of the selector (A4)
A case where a timing error occurs in the simulation flow of the conventional example of FIG. 8 will be described with reference to a timing chart of FIG. DFF (A1), DFF (A
2) and DFF (A3) read and output data at the rising edge of the clock signal applied to clock terminal C as shown in FIG. 9B. Selector (A4)
Selects and outputs the signal at terminal A when the signal input to select terminal S is "0", and outputs the signal at terminal B when the signal input to select terminal S is "1". As shown in FIG. 9C, the timing specification of each DFF has a setup time of 0.5 ns and a hold time of 0.5 ns, and the clock signal has a high-level width and a low-level width of 1 ns each. And For the sake of simplicity, it is assumed that the output change delay value with respect to the input event of each circuit internal cell is the same.

In FIG. 10, the first data input terminal D1 in FIG. 9A changes at 29 time (2.9 ns), and at time T1 (30 time = 3 ns), at step 181 the clock input terminal CK is If an input event is detected, in step 182, the input event is DFF (A1), DFF
(A2), it is determined that there is an event change of the DFF (A3), and in step 183, the time difference between the signal change of the clock terminal C and the signal change of the data terminal D of each DFF is extracted.
Compare with the timing specification, and
It is determined that a setup timing error has occurred only in (A1).

The DFF (A2) and the DFF (A3)
It is determined that there is no timing error, and a logical operation is performed based on the input state value in step 185, and the output state value is output.

For the DFF (A1) determined to have a timing error in step 184, step 186
After writing the error occurrence time, the circuit internal cell name (A1) in which the error occurred, and the error determination reason as timing error information in the temporary file,
An undefined value “X” is output as the output state value of (A1).

FIG. 11 is a diagram showing the contents of the temporary file 11 and the result file 12. In the timing error information written in the temporary file 11,
(Time 30) indicates that the error time is 3 ns, A1 (DFF) indicates that the circuit internal cell in which the error has occurred is DFF (A1), and (DC = 1 (s)
ped: 5)) is 5 unit times (0.5 ns) for the setup time specification of the DFF (A1), while the time from the signal change of the data terminal D to the rising of the clock terminal C is 1 unit time (0 ns). .1 ns).

Subsequently, a delay value is added in step 187, and a state value is scheduled in step 188. Up to this point, “X” is applied to the terminal Q of the DFF (A1),
This means that a state value schedule of “1” is set to the terminal Q of 2) and a state value of “0” is set to the terminal Q of the DFF (A3). In step 189, since the pattern has not been completed, the process returns to step 181 to continue the simulation. Step 1
The output state value of each DFF scheduled at 88 is detected as an event at step 181, and at step 182, "X" is applied to the terminal A, "1" is applied to the terminal B, and "0" is applied to the terminal S of the selector (A4) of the circuit internal cell. Is determined to have been input, and since there is no timing specification in the selector (A4), Step 183 is omitted, Step 184 has no error, and in the operation processing of Step 185, the state value of the operation result is set to the indefinite value “X”. And output the status value. At step 187, a delay value is added, and at step 188, a state value schedule is performed.

Next, the input event to the output terminal cell N2 is determined to be a change in the input / output terminal cell in step 182, and the input state value is scheduled to be output as it is in step 188. Similarly, for an input event to the output terminal cell N1, it is determined in step 182 that the input / output terminal cell has changed, and in step 188, the input state value is scheduled for output as it is. Thus, the process for the event at the time T1 is completed.

Similarly, a time T2 (50 time = 50 time) with respect to a change of 49 time (4.9 ns) at the data input terminal D3.
5 ns), a temporary error is detected in the temporary file 11 even if a timing error of the DFF (A3) is detected.
(Time 50) is written.

129 time of the data input terminal D1 (12.
Time T3 (130 time = 13n) for a change of 9 ns
s), the timing error is detected by the DFF (A1), and (Ti) is stored in the temporary file 11.
The timing error information of the item of “me 130)” is written.

The time 149 at the data input terminal D3 (14.
9 ns) at the time T4 (150 time = 15n)
In the processing in s), the timing error in the DFF (A3) is detected, and (Ti
The timing error information of the item of “me 150)” is written.

When the end of the verification pattern is detected in step 189, the temporary file 1
The timing error information written in No. 1 is written in the result file, and the process is terminated. FIG. 11 shows the timing error information recorded in the temporary file 11 and the timing error information recorded in the result file 12 generated in a series of processing. According to the simulation flow of the conventional example in FIG. 8, the timing error information of the temporary file 11 and the timing error information of the result file 12 are the same.

Referring to FIG. 10, whether each error is a true error or a pseudo error is examined, the error at time T1 becomes the expected value "1" of the output state value of output terminal N1. On the other hand, since the operation value is "X", this is a true error, and the error at time T2 is a true error because the operation value is "X" with respect to the expected value "1" of the output state value of the output terminal N2. But the error at time T3 and the time T4
Is actually a pseudo error. The error at time T3 is a pseudo error corresponding to the criterion (1) given above because the output state value “X” due to this error does not appear at the output terminal N1 until the end of the verification pattern. The error at time T4 is a pseudo error corresponding to the criterion (2) because the expected value of the output state value of the output terminal N2 is "X".

[0023]

As described above, in the conventional example, a pseudo error is mixed in a result file for outputting final timing error information. For this reason, after the execution of the logic simulation, the cell in which the error has occurred is grasped from the timing error information in the result file with respect to the reported timing error, and the re-simulation is executed to obtain the signal change information around the error cell (corresponding to FIG. ) And analyzing the propagation path of the output state value and the operation state to determine whether the error is a pseudo error or a true error, and the determination process takes a lot of time.

An object of the present invention is to provide a timing check method capable of extracting only true errors and writing the same in a result file when writing timing error information from a temporary file to a result file.

[0025]

According to a first aspect of the present invention, there is provided a timing check method in a logic simulator, comprising: a logic simulator having a function of checking timing of a circuit internal cell and an input / output terminal cell, and performing a logical operation and a comparison with an expected value; In the timing check method described above, when it is determined that a timing error has occurred in the timing check, flag information corresponding to the error information on a one-to-one basis is added and stored in the first storage means, and an undefined value with flag information is output as a state value. A timing error processing step with flag information, and flag information for inputting a state value and performing a logical operation on a circuit internal cell while propagating the flag information when the state value has flag information, and outputting a state value of the operation result Operation processing step, and the flag is added to the output state value of the output terminal cell. A pseudo error erasure processing step of storing the flag information in the second storage means when the information is added and the output expected value of the verification pattern is not an indefinite value; Error extraction / result file creation processing step of extracting only error information corresponding to the flag information stored in the second storage means from the error information stored in the means and creating an error result file. ing.

A timing check method in a logic simulator according to a second aspect of the present invention includes an event detecting step of detecting an event input, a target determining step of determining whether an event input target is a circuit internal cell or an input / output terminal cell,
A timing check step of performing a timing check of the circuit internal cell when the target is determined to be a circuit internal cell in the target determination step; an error determining step of determining whether there is an error in the timing check; and A timing error processing step with flag information for outputting an undefined value with flag information as a status value after adding a flag information corresponding to the error information of the timing error in a one-to-one manner and storing it in a temporary file when there is a timing error; When it is determined in the error determination step that there is no timing error, a state value is input, and when the state value has flag information, a logic operation is performed on a circuit internal cell while propagating the flag information, and a state of the operation result is obtained. Operation step with flag information to output a value A delay addition processing step of adding a delay value specific to a cell type to a state value of a circuit internal cell output in the timing error processing step with flag information or the timing error processing step with arithmetic processing with flag information; When the flag information is added to the output state value of the target cell when the target is determined as the input / output terminal cell in the determination step, and the output expected value of the verification pattern is not an undefined value, the flag information is output as an error. A pseudo error erasure processing step for writing to a file; a state value scheduling step for scheduling the state value output by the delay addition processing step or the pseudo error erasure processing step; When the process returns to the event detection step and ends, the process proceeds to the next step. Ending judgment step, extracting only error information corresponding to the flag information written and registered in the error output flag file from the error information added with the flag information stored in the temporary file and outputting the extracted error information to a result file Error extraction / result file creation processing step. In the second invention, the arithmetic processing step with flag information includes a first sub-step of inputting an input state value to an internal circuit cell, and a second step of determining whether flag information is added to the input state value. A third step of storing the flag information when the flag information has been added;
A sub-step of executing a logical operation based on a logical operation function of the circuit internal cell when it is determined that the flag information is not added in the second sub-step or after the third sub-step. A fourth sub-step, a fifth sub-step of determining whether an output state value of the circuit internal cell is an indefinite value based on a result of the logical operation, and an output state value having an indefinite value in the fifth sub-step. A sixth sub-step of adding the flag information stored in the third sub-step to the output state value when it is determined that the output state value is not an indefinite value in the fifth sub-step; or A seventh sub-step of outputting an output state value following the sixth sub-step may be adopted.

According to a third aspect of the present invention, there is provided a timing check method for a logic simulator, comprising the steps of: inputting a status value to the flag calculation processing step in the second invention when it is determined in the error determination step that there is no timing error; When the flag information is included, the logic operation of the circuit internal cell is performed while propagating the flag information, and when the state value of the operation result is an indefinite value, the name of the circuit internal cell and the flag information are stored and then the An operation processing step with flag information for outputting a state value of an operation result is replaced.In addition, the state value scheduling step schedules the state value output in the delay addition processing step or the pseudo error elimination processing step and performs the operation processing with flag information. The name and flag information of the circuit internal cell stored in the step It is replaced with a state value schedule step of writing to a temporary file. In the third aspect, the arithmetic processing step with flag information includes a first sub-step of inputting an input state value to an internal circuit cell, and a second sub-step of determining whether flag information is added to the input state value. Step, a third sub-step for storing the flag information when the flag information has been added, and when the flag information is determined not to be added in the second sub-step or when the third sub-step is performed. A fourth sub-step of performing a logical operation based on a logical operation function of the circuit internal cell; and a fifth step of determining whether an output state value of the circuit internal cell is an indefinite value based on a result of the logical operation. And outputting the flag information stored in the third sub-step when the output state value is determined to be indefinite in the sub-step and the fifth sub-step. A sixth sub-step of adding the state value to the state value, a seventh sub-step of storing the name of the circuit internal cell whose output state value is determined to be an indefinite value, and the flag information, and a fifth sub-step. When the output state value is not an indefinite value, an eighth sub-step of outputting the output state value following the sixth sub-step may be provided.

In the first and second inventions, the pseudo error erasure processing step includes a first sub-step for determining whether an event target is an output terminal cell, and an output terminal for the first sub-step. A second sub-step of determining whether or not flag information is added to the output state value of the output terminal cell when it is determined that the cell is a cell; and if the flag information is added in the second sub-step, A third step of determining whether an expected value for the output state value is an indefinite value
And a fourth sub-step of writing and registering the flag information added to the output state value in the error output flag when it is determined in the third sub-step that the expected value is not an undefined value. And may be configured to include:

A computer-readable recording medium on which the timing check method of the fourth invention is recorded,
First event detection for detecting an event input and determination of whether the event input target is a circuit internal cell or an input / output terminal cell
A second program for performing a timing check of the circuit internal cell when the target is determined to be a circuit internal cell in the target determining step, and determining whether there is an error in the timing check; A third program that, when there is an error, adds flag information one-to-one with the error information of the timing error and stores it in a temporary file, and then outputs an indefinite value with flag information as a status value; When it is determined that there is no timing error, a state value is input, and when the state value has flag information, a logic operation of the circuit internal cell is performed while propagating the flag information, and a state value of the operation result is output. 4 and the cell type specific delay value in the output circuit internal cell state value The fifth program to be added, and when the flag information is added to the output state value of the target cell when the event input target is determined to be an input / output terminal cell, and the expected output value of the verification pattern is not an indefinite value A sixth program for writing the flag information to an error output file, and judging the end of the verification pattern after scheduling the output state values. If the verification pattern has not been ended, connect to the first program for verification. If the pattern is completed, only the error information corresponding to the flag information written and registered in the error output flag file is extracted from the error information added with the flag information stored in the temporary file and output to the result file. Seventh
Program.

A computer-readable recording medium on which the timing check method according to the fifth invention is recorded is characterized in that the fourth program according to the fourth invention is provided by inputting a state value when it is determined that there is no timing error. When the value has the flag information, the logic operation of the circuit internal cell is performed while propagating the flag information. When the state value of the operation result is an indefinite value, the name of the circuit internal cell and the flag information are stored. And a fourth program which outputs the state value of the operation result from the fourth program. The seventh program schedules the output state value and stores the name of the circuit internal cell stored in the operation step with flag information. And the flag information are written to the temporary file, and then the end of the verification pattern is determined. Then, if the connection to the first program is made and the verification pattern is completed, an error corresponding to the flag information written and registered in the error output flag file from the error information added with the flag information stored in the temporary file is registered. It is replaced with a seventh program that extracts only information and outputs it to a result file.

[0031]

According to the present invention, when a timing error is determined in a timing check, flag information which is a specific code corresponding to each timing error is added to the temporary file together with the timing error information. After the operation step, the state value with the flag information is propagated to schedule the output state value. When the state value with the flag information is propagated to the output terminal cell, the pseudo error erasure processing is performed and the true error is performed. Timing information that excludes pseudo-errors by extracting only the error information having the flag information determined to be a true error from the timing error information recorded in the temporary file and writing it to the result file. Information can be obtained.

FIG. 1 is a processing flowchart of an embodiment of a timing check method in a logic simulation according to the present invention. Here, the overall configuration of the logic simulator that executes the logic simulation of FIG. 1 is the same as the configuration of the conventional example of FIG. 7A. FIG. 2 is a diagram showing the correspondence between the state values and the contents that can be input and output to and from the input terminal, the output terminal, and the internal cell in the present embodiment. In the conventional example of FIG. “X (1)” representing a value
“X (n)” is added. Hereinafter, the processing flow of FIG. 1 will be described.

In an event detection step 101, an input event input from the verification pattern 2 is detected for a cell in the simulation circuit input from the circuit data 1 to the simulator body 5, and an object determination step 10
In step 2, it is determined whether the input event is an event change in a circuit internal cell or an input / output terminal cell event change. If the event changes in a cell inside the circuit, the process proceeds to the timing check of the timing check step 103 to extract the input event time difference of the cell.

If the extracted input event time difference does not satisfy the timing specifications, it is determined that there is a timing error in the error determination step 104, the process proceeds to the timing error processing step with flag information step 106, and in the sub-step 121, an error is specified. A temporary file 11 as a temporary storage file stores a code (here, a serial number in the order of error occurrence), a timing error occurrence time, a circuit internal cell name, an extracted input event time difference, timing specification and other timing error information.
After that, in the sub-step 122, the undefined value “X (n)” with the flag information is output to the storage unit in the simulator body 5 as the output state value. Next, the process proceeds to a delay addition processing step 107 to add a delay value, and an output state value is scheduled in a state value scheduling step 108.

If the input event time difference extracted in the timing check step 103 satisfies the timing specification, it is determined in the error determination step 104 that there is no timing error, and the flow proceeds to the arithmetic processing step 105 with flag information.

FIG. 3 is a detailed flowchart of the arithmetic processing with flag information 105. First, in step 131, the input state value of the target cell is input.
It is determined whether flag information has already been added. If the input state value has flag information, sub-step 1
The program proceeds to 33, where the flag information is stored in the storage section in the simulator body 5, and the procedure proceeds to sub-step 134. Substep 1
If it is determined in S32 that no flag information is added to any of the input state values, the process proceeds to substep 134. In sub-step 134, a logical operation is performed based on the input state value and the logic information of library 3 to obtain an output state value. At sub-step 135, it is determined whether or not the output state value is an undefined value. If the output state value is undefined, the process proceeds to step 136, at which the flag information stored at sub-step 133 is read out and added to the output state value. , The sub-step 137 is performed to output the output state value. Substep 1
If it is determined at 35 that the output state value is not an indefinite value, the process proceeds to sub-step 137 to output the output state value.
After the above-described arithmetic processing step 105 with flag information,
The process proceeds to the delay addition processing step 107.

In the delay adding processing step 107, the circuit SD
A delay value is added based on the delay timing information of F4, and an output state value is scheduled in a state value scheduling step 108.

If the input event is an event change of the input / output terminal cell in the object determination step 102,
The process proceeds to the pseudo error erasure processing step 111. FIG. 4 is a detailed flowchart of the pseudo error erasure processing step 111. First, in sub-step 141, it is determined whether or not the event target is an output terminal cell. If it is an output terminal, the flow advances to sub-step 142 to determine whether or not flag information is added to the output state value of the output terminal. If the flag information is added in the sub-step 142, the process proceeds to the sub-step 143, and it is determined whether or not the expected value of the output state value of the output terminal is the indefinite value “X”. When it is determined in substep 141 that the terminal is not an output terminal, when it is determined in substep 142 that flag information is not added to the output state value, and when the expected value is indefinite value “X” in substep 143.
If, the pseudo error erasing process is completed and the process proceeds to the status value scheduling step 108. Sub-step 14
When the expected value is not the undefined value “X” in 3, since the status value with flag information of this output terminal indicates a true error, the process proceeds to sub-step 144 and the flag information is written to the error output flag file 13. Thereafter, the pseudo error erasing process is completed, and the process proceeds to the state value scheduling step 108.

The status value scheduled in the status value scheduling step 108 is written to the temporary file 11 as a calculation result. Pattern end judgment step 1
This processing is repeated until the end of the pattern stored in the verification pattern 2 is detected in step 09, and when the end of the pattern is detected, the process proceeds to the error extraction / result file creation processing step 110, and the timing stored in the temporary file 11 Only the timing error information corresponding to the flag information written in the error output flag file 13 out of the error information is extracted, written in the result file 12 as true timing error information, and the process ends.

In this embodiment, even if a timing error occurs in a cell inside the simulation circuit, the timing error state value “X” output from the cell inside the circuit is output.
Is not propagated to the external output terminal, or if the expected value of the verification pattern is an undefined value “X” even if it propagates, the timing error is automatically determined as a pseudo error and written to the result file. Since no pseudo error is included, the pseudo error can be prevented from being mixed, and the number of steps of the pseudo error analysis can be greatly reduced. Next, in the case where a timing error has occurred in the simulation flow of FIG. 1, similarly to the description of the conventional example, the internal circuit of FIG. Will be explained. DFF (A1), DFF (A2), DFF (A
The functions and timing specifications of 3) are also shown in FIGS. 9B and 9C as in the conventional example.

In FIG. 10, the first data input terminal D1 in FIG. 9A changes at 29 time (2.9 ns), and at time T1 (30 time = 3 ns), the clock input terminal at the event detection step 101 is detected. If an input event of CK is detected, the input event is
F (A1), DFF (A2), and DFF (A3) are determined to be event changes, and in a timing check step 103, a time difference between a signal change of the clock terminal C of each DFF and a signal change of the data terminal D is extracted. , DFF (A
It is determined that a setup timing error has occurred only in 1).

As for DFF (A2) and DFF (A3), it is determined that there is no timing error, and the flow advances to the arithmetic processing step with flag information 105, where the input state value is input in the sub-step 131 in the arithmetic processing step with flag information 105. In sub-step 132, it is determined whether or not flag information is included. Since the state value is not flag information-added, the flow proceeds to sub-step 134 to perform a logical operation. DFF (A
The calculation result that the calculation state value of 2) is “1” and the calculation state value of DFF (A3) is “0” is obtained, and sub-step 135
Then, it is determined whether or not the operation state value is an indefinite value "X". However, since the operation state value is not the indefinite value "X", the process proceeds to substep 137 to output the operation result as an output state value.

On the other hand, error determination step 104
For the DFF (A1) determined to have a timing error in the sub-step 121 of the timing error processing step 106 with flag information, the error information flag (0
1), the error occurrence time, the name of the cell in the circuit in which the error occurred (A1), and the reason for the error determination are written in the temporary file 11 as timing error information, and then the flag is set as the output state value of the DFF (A1). It outputs an undefined value “X (01)” with information. FIG.
3 is a diagram showing the contents of a temporary file 11, an error output flag file 13, and a result file 12. FIG. Paying attention to the timing error information written in the temporary file 11, it differs from the timing error information in FIG. 11 of the conventional example in that (01) indicating the flag information is added.

Subsequently, a delay value is added in a delay addition processing step 107, and a state value is scheduled in a state value scheduling step 108. By the processing so far, DFF
This means that the status value schedule of “X (01)” at the terminal Q of (A1), “1” at the terminal Q of the DFF (A2), and “0” at the terminal Q of the DFF (A3). Since the pattern has not ended in the pattern end determination step 109, the process returns to the event detection step 101 and the simulation is continued. The output state value of each DFF scheduled in the state value scheduling step 108 is the event detection step 1
01 is detected as an event, and the target determination step 10
Although the event is determined as an event of a circuit internal cell in step 2, the timing check step 103 is omitted because there is no timing specification in the selector (A4), the error determination step 104 has no error, and the process proceeds to the arithmetic processing step 105 with flag information. . In the arithmetic processing with the flag, in sub-step 131, “X” is input to the terminal A of the selector (A4).
(01) ", the input state value of" 1 "is input to the terminal B, and the input state value of" 0 "is input to the terminal S. In the sub-step 132, the flag information (01) is added to the input state value of the terminal A. In sub-step 134, a logical operation is performed, and the state value of the operation result is set to an indefinite value “X”.
In step 5, since the output state value is an indefinite value,
5, the flag information (01) stored in the sub-step 133 is read out, added to the output state value, and "X (0
1) The state value is output as "". Subsequently, a delay value is added in a delay addition processing step 107, and a state value schedule is performed in a state value scheduling step 108.

Next, the input event to the output terminal cell N2 is determined as a change in the input / output terminal cell in the target determination step 102, and the process proceeds to the pseudo error erasure processing step 111.
In the pseudo error erasure processing step 111, it is determined in step 141 that the output terminal cell has changed. In step 142, the state value is 0 and no flag information is attached, so the state value is scheduled in the state value scheduling step 108. The logical operation is not performed on the input / output terminal cells, and the input state value is scheduled to be output as it is.

By the processing up to this point, the state value of "X (01)" has been scheduled at the output terminal Q of the selector (A4), and the flow proceeds to the pattern end determination step 109. Event detection step 10
1, the input state value “X (0
1) It is detected that "" is input. In the object determination step 102, the input event is determined to be a change in the input / output terminal cell, and in the sub-step 141 in the pseudo error erasure processing step 111, it is determined to be a change in the output terminal cell. Step 1
Proceeding to 42, the status value is accompanied by flag information, so the flow proceeds to step 143 to determine whether the expected value stored in the verification pattern is the undefined value "X", and the expected value is not the undefined value "X". Therefore, in step 144, the flag information (01) is written in the error output flag file 13 as shown in FIG. 5, and the state value is scheduled in the state value scheduling step 108. Thus, the process for the event at the time T1 is completed. Data input terminal D3
At the time 49 (4.9 ns), the time T2
Even when a timing error of DFF (A3) is detected in the process at (50 time = 5 ns), the flag information (temporary file 11) is stored in the temporary file 11 as shown in FIG. 02) (Time 5
The timing error information of the item (0) is written, and the flag information (02) is written in the error output flag file 13.

129 time of the data input terminal D1 (12.
Time T3 (130 time = 13n) for a change of 9 ns
In the process of s), similarly, a timing error is detected by the DFF (A1), and the timing error information of the item (Time 130) to which the flag information (03) is added is written in the temporary file 11. In this case, the state value “X (0)
3) is output, but the state value of the operation result becomes “0” in the logical operation in the sub-step 134 of FIG. 3 in the operation processing step 105 with the flag information for the selector (A4), and the sub-step 135 It is determined that the state value is not an indefinite value, the state value is output in substep 137, the delay value is added in delay addition processing step 107, and the state value schedule is performed in state value schedule step 108. The selector (A4) Since the output state value “0” is scheduled at the terminal Q, when returning to the event detection step 101, it is detected that “0” is input to the output terminal cell N1, and the object determination step 1
02, it is determined that the input / output terminal cell has changed.
In step 142, it is determined that the output terminal cell has changed. In step 142, since the state value is "0" and no flag information is attached, the process proceeds to the state value scheduling step 108, where the state value is scheduled. Thus, for the timing error at time T3, which is actually a pseudo error,
The flag information (03) is not written in the error output flag file 13 because it does not pass through the sub-step 144 of FIG. 4. 149 time of data input terminal D3 (14.9n
Time T4 for change in s) (150 time = 15 ns)
As for the processing in, a timing error in the DFF (A3) is detected, and (Time
The timing error information of the item 150) is written. The terminal Q of the DFF (A3) has an output state value “X (0
3) is output, and in the event detection step 101, the event detection of the output terminal cell N2 is detected.
Is determined as a change in the input / output terminal cell. In this case,
Subsequent sub-step 141 in pseudo error erasure processing step 111 determines that the output terminal cell has changed, and sub-step 142 determines that the state value has flag information. However, in sub-step 143, state value “X (03) )), The expected value in the verification pattern is an indefinite value “X”.
Proceeding to state value schedule step 108, a state value schedule is performed. Also in this case, regarding the timing error at time T4, which is actually a pseudo error,
The flag information (04) is not written in the error output flag file 13 because it does not pass through the sub-step 144 of FIG. 4. When the end of the verification pattern is reached, the end of the pattern is determined in a pattern end determination step 109, and error extraction /
In the result file creation processing step 110, only the timing error information corresponding to the flag information written in the error output flag file 13 is extracted from the timing error information written in the temporary file 11, and Write it and end the process.

FIG. 5 shows the contents of the temporary file 11, the error output flag file 13, and the result file 12 generated in a series of processing. The timing errors at times T3 and T4 are recognized as pseudo errors in the pseudo error erasure processing step 111 and are removed, so that all the timing errors recorded in the result file 12 are true errors. According to the present embodiment, as described above, it is possible to significantly reduce timing error analysis man-hours by automatically determining whether or not a timing error generated in a logic simulation is a pseudo error and reflecting it in a result file. Development time can be shortened. In a simulation of a circuit in which the number of cells in the circuit is about 2,000 cells, 100
Since the timing pseudo error of the order is detected and the judgment of the pseudo error requires about two hours per error on average, the design time of about 200 hours can be reduced by applying the present invention. .

FIG. 6 is a flowchart of an arithmetic operation with flag information according to the second embodiment of the present invention. In the previous embodiment, the arithmetic processing step 105 with the flag information in FIG. 1 is constituted by the sub-steps 131 to 137 in FIG. 3, but in the present embodiment, the sub-processing in the arithmetic processing with the flag information 105 in FIG. Sub-step 161 is added after step 136. The sub-step 136 stores the circuit internal cell name in which the flag information is added to the output state value and the flag information together with the time in the storage unit of the simulator body. 137 is replaced by a calculation process 105a with flag information changed to proceed to 137. With the addition of the sub-step 161, the state value is scheduled in the state value scheduling step 108, and the internal cell name with the flag information and the flag information stored in the storage unit of the simulator body are temporarily stored together with the time. Store in file 11. After the pattern is completed, the name of the circuit internal cell to which the flag information is added and the flag information together with the timing error information corresponding to the flag information recorded in the error output file 13 in the error extraction / result file creation processing step 110 are obtained. By outputting to the file 12, it is possible to easily obtain information as to which circuit internal cell the state value to which the flag information has been added has propagated. For example,
For the error at the time T1 (= 30 time), in addition to the previous flag information (01) and the timing error information of the DFF (A1), this error causes the selector (A4) in the next processing loop. ) Is an indefinite value “X
(01) "is recorded in the result file 12. Such information indicating how the state value affected by the error has propagated to the circuit internal cell is the true information detected. This is very useful information for timing error analysis and circuit correction.Conventionally, the analysis of the propagation path of the state value uses the function of the simulator called traceback. In this case, the output terminal and the traceback start time must be set in advance when the simulation is executed, and the execution of the resimulation is substantially required. Thus, the design efficiency can be improved.

[0050]

As described above, according to the first embodiment of the present invention, the timing error generated in the logic simulation is automatically determined as to whether it is a pseudo error, and the timing error is reflected in the result file. Error analysis man-hours can be greatly reduced, and the development period can be shortened.

In a simulation of a circuit in which the number of cells in the circuit is about 2,000, conventionally,
Since a timing pseudo error of about 0 is detected and the pseudo error determination requires about 2 hours per error on average, it is possible to reduce the design time of about 200 hours by applying the present invention. Become.

In addition, in the second embodiment, information about how the state value "X" is propagated to the circuit internal cells when a timing error occurs can be easily obtained. Further, an additional simulation for error analysis for the purpose of correcting a defect in the timing design can be omitted, and the effect that the design efficiency can be further improved is produced.

[Brief description of the drawings]

FIG. 1 is a processing flowchart of an embodiment of a timing check method in a logic simulation according to the present invention.

FIG. 2 is a diagram showing correspondences between state values and contents that are possible in input / output of input terminals, output terminals, and internal cells.

FIG. 3 is a detailed flowchart of an arithmetic operation with flag information.

FIG. 4 is a detailed flowchart of a pseudo error erasing process.

FIG. 5 is a diagram showing contents of a temporary file, an error output flag file, and a result file according to the first embodiment of the present invention.

FIG. 6 is a flowchart of an arithmetic operation with flag information according to the second embodiment of the present invention.

FIG. 7A is a configuration diagram of an event-driven logic simulator, and FIG. 7B is a correspondence diagram of state values handled in the logic simulation and their contents.

FIG. 8 is a processing flowchart of a conventional event-driven logic simulation.

9A is an example of a circuit diagram of a circuit to be simulated, and FIG. 9B is a diagram showing a truth value of a data flip-flop (DFF) and a truth value of a selector in the circuit of FIG. 9A. (C) is a diagram showing operation timing specifications of the DFF.

FIG. 10 is a timing chart of a simulation result of the circuit of FIG.

FIG. 11 is a diagram showing the contents of a temporary file and a result file in a conventional example.

[Explanation of symbols]

 1 Circuit Data 2 Verification Pattern 3 Library 4 Circuit SDF 5 Simulator Body 11 Temporary File 12 Result File 13 Error Output Flag File

Claims (8)

[Claims] 1. A timing check method in a logic simulator having a function of checking a timing of a circuit internal cell and an input / output terminal cell and comparing a logical operation and an expected value, wherein when a timing error is determined in the timing check, error information is output. A timing error processing step with flag information for adding flag information corresponding to one to one and storing the flag information in the first storage means and outputting an undefined value with flag information as a state value; When the flag information is provided, the flag information is added to the output state value of the output terminal cell, and the flag information is added to the output state value of the output terminal cell. The flag information if the output expected value of the verification pattern is not an indefinite value A pseudo error erasure processing step stored in the second storage means; and after completion of the execution of the logic simulation, the error information stored in the first storage means corresponds to the flag information stored in the second storage means. Extraction / extract only error information to create error result file
A timing check method in a logic simulator, comprising a result file creation processing step. 2. An event detection step of detecting an input of an event; a target determination step of determining whether an event input target is a circuit internal cell or an input / output terminal cell; and the target determination step determines that the target is a circuit internal cell. A timing check step of performing a timing check of the circuit internal cell when the error occurs, an error determination step of determining whether there is an error in the timing check, and error information of the timing error when there is a timing error in the error determination step. A timing error processing step with flag information that outputs an indefinite value with flag information as a state value after adding the flag information corresponding to one-to-one and storing it in a temporary file, and it is determined that there is no timing error in the error determination step When the state value is entered, the state value When flag information is included, an arithmetic processing step with flag information for executing a logical operation of the circuit internal cell while propagating the flag information and outputting a state value of the operation result; and the timing error processing step with flag information or the flag information A delay addition processing step of adding a delay value specific to the cell type to the state value of the circuit internal cell output in the timing error processing step with the operation processing; and a case where the target is determined to be an input / output terminal cell in the target determination step. A pseudo error erasure processing step of writing the flag information to an error output file when the flag information is added to the output state value of the target cell and the output expected value of the verification pattern is not an indefinite value; Or the status value output by the pseudo error erasure processing step. A state value scheduling step for judging, a pattern end determination step for determining the end of the verification pattern and returning to the event detection step if not completed and proceeding to the next step if completed, and the flag stored in the temporary file An error extraction / result file creation processing step of extracting only error information corresponding to the flag information written and registered in the error output flag file from the error information to which the information is added and outputting the extracted error information to a result file. Checking method in a logic simulator. 3. An arithmetic processing step with flag information includes: a first sub-step of inputting an input state value to an internal circuit cell; and a second sub-step of determining whether flag information is added to the input state value. A third sub-step of storing the flag information when the flag information has been added; and a step of determining whether the flag information has not been added in the second sub-step or the third sub-step. A fourth sub-step of executing a logical operation based on a logical operation function of the circuit internal cell; and a fifth step of determining whether an output state value of the circuit internal cell is an indefinite value based on a result of the logical operation. Sub-step; and when the output state value is determined to be indefinite in the fifth sub-step, the flag information stored in the third sub-step is output to the output section. A sixth sub-step of adding an output state value to the force state value, and a seventh sub-step of outputting an output state value when the output state value is not an indefinite value in the fifth sub-step or after the sixth sub-step. 3. The timing check method in the logic simulator according to claim 2, comprising: 4. An event detecting step of detecting an event input; a target determining step of determining whether an event input target is a circuit internal cell or an input / output terminal cell; and the target determining step determines that the target is a circuit internal cell. A timing check step of performing a timing check of the circuit internal cell when the error occurs, an error determination step of determining whether there is an error in the timing check, and error information of the timing error when there is a timing error in the error determination step. A timing error processing step with flag information that outputs an indefinite value with flag information as a state value after adding the flag information corresponding to one-to-one and storing it in a temporary file, and it is determined that there is no timing error in the error determination step When the state value is entered, the state value When the flag information is included, the logic operation of the circuit internal cell is performed while propagating the flag information, and when the state value of the operation result is an indefinite value, the name of the circuit internal cell and the flag information are stored and then the An operation processing step with flag information for outputting the state value of the operation result; a cell type specific to the state value of the circuit internal cell output in the timing error processing step with flag information or the timing error processing step with operation processing with flag information A delay addition processing step of adding a delay value to the output state value of the target cell when the target is determined to be an input / output terminal cell in the target determination step; A pseudo error erasure processing step of writing the flag information to an error output file when the value is not an undefined value. The temporary file schedules the state values output in the delay adding processing step or the pseudo error erasing processing step, and stores the names of the circuit internal cells and the flag information stored in the arithmetic processing step with flag information in the temporary file. A status value scheduling step for writing to the following; a pattern end determination step for determining the end of the verification pattern and returning to the event detection step if not completed and proceeding to the next step if completed; and the flag stored in the temporary file An error extraction / result file creation processing step of extracting only error information corresponding to the flag information written and registered in the error output flag file from the error information to which the information is added and outputting the extracted error information to a result file. Logic simulator Lee timing check method. 5. The arithmetic processing step with flag information includes: a first sub-step of inputting an input state value to an internal circuit cell; and a second sub-step of determining whether flag information is added to the input state value. A third sub-step of storing the flag information when the flag information has been added; and a step of determining whether the flag information has not been added in the second sub-step or the third sub-step. A fourth sub-step of executing a logical operation based on a logical operation function of the circuit internal cell; and a fifth step of determining whether an output state value of the circuit internal cell is an indefinite value based on a result of the logical operation. Sub-step; and when the output state value is determined to be indefinite in the fifth sub-step, the flag information stored in the third sub-step is output to the output section. A sixth sub-step of adding to the force state value, a seventh sub-step of storing the name of the circuit internal cell whose output state value has been determined to be indefinite, and the flag information, and a fifth sub-step. 5. The method according to claim 4, further comprising: when the output state value is not an indefinite value, or after the sixth sub-step, outputting an output state value. 6. The pseudo error erasure processing step includes: a first sub-step for determining whether an event target is an output terminal cell; and an output when the event is determined to be an output terminal cell in the first sub-step. A second sub-step of determining whether or not flag information has been added to the output state value of the terminal cell; and if the flag information has been added in the second sub-step, the expected value for the output state value is undefined. A third sub-step of determining whether the expected value is not an indefinite value in the third sub-step. 4. A timing check method in a logic simulator according to claim 2, further comprising: a fourth sub-step of writing and registering the timing. 7. A first program for detecting an event to detect an input of an event and determining whether an event input target is a circuit internal cell or an input / output terminal cell, and the target determining step determines that the target is a circuit internal cell. A second program for executing a timing check of the circuit internal cell and determining whether there is an error in the timing check; and a flag corresponding to the error information of the timing error in a one-to-one correspondence when there is a timing error in the timing check. A third program for outputting an indefinite value with flag information as a status value after storing the information in a temporary file after adding information, and inputting a status value when it is determined that there is no timing error in the timing check. Is provided with the flag information, while transmitting the flag information, A fourth program that executes a logical operation and outputs a state value of the operation result, a fifth program that adds a cell type-specific delay value to the output circuit internal cell state value, A sixth program for writing the flag information to an error output file when the flag information is added to the output state value of the target cell when the terminal cell is determined and the expected output value of the verification pattern is not an undefined value; After the output state value is scheduled, the end of the verification pattern is determined. If the verification pattern is not completed, the program is connected to the first program. If the verification pattern is completed, the program is stored in the temporary file. From the error information with the flag information added, only the error information corresponding to the flag information written and registered in the error output flag file is read. Out by computer-readable recording medium recording a timing check method characterized by having a seventh program that outputs the result file. 8. A first program for detecting an event to detect an input of an event and determining whether an event input target is a circuit internal cell or an input / output terminal cell, and the target determining step determines that the target is a circuit internal cell. A second program for executing a timing check of the circuit internal cell and determining whether there is an error in the timing check; and a flag corresponding to the error information of the timing error in a one-to-one correspondence when there is a timing error in the timing check. A third program that outputs an undefined value with flag information as a status value after storing the information in a temporary file with information added, and a status value is input when it is determined that there is no timing error, and the status value is added with flag information. , The logic operation of the circuit internal cell is executed while propagating the flag information, and the operation result is obtained. A fourth program for storing the name of the circuit internal cell and the flag information when the state value is an indefinite value, and then outputting the state value of the operation result; A fifth program for adding a delay value specific to the cell type; and when the flag information is added to the output state value of the target cell when the event input target is determined to be an input / output terminal cell, and the output expectation of the verification pattern is expected. A sixth program for writing the flag information to an error output file when the value is not an indefinite value; and a name and a flag of a circuit internal cell stored in the arithmetic processing step with the flag information while scheduling the output state value. After the information is written to the temporary file, the end of the verification pattern is determined. If the verification pattern is not completed, the first program When the verification pattern is completed, only the error information corresponding to the flag information written and registered in the error output flag file is extracted from the error information added with the flag information stored in the temporary file, and the result is obtained. A computer-readable recording medium recording a timing check method, comprising: a seventh program for outputting to a file.