JP2000305977A - Method for verifying logical data, logic verification system for executing the verification method and recording medium recording program for executing the verification method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the accuracy of preparation of check item information and to easily check that logical data are not degraded when logical data are changed. SOLUTION: Waveform data 13 are prepared from the logical data 10 of a semiconductor integrated circuit prepared by a hardware description language and test pattern data 11 by using logical simulation and check item information 18 is prepared from the waveform data 13 and information inputted from a user specification part 15. A means for inputting check item information 14 prepared the last time adds a part not included in the information 14 out of check item information generated from information applied from the user specification part 15 to the information 18 prepared this time and outputs the added information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of verifying logical data of a semiconductor integrated circuit created in a hardware description language using model checking, and a logic for executing the logical verifying method. The present invention relates to a verification system and a logic verification system on a recording medium storing a program for executing the logic verification method.

[0002]

2. Description of the Related Art In general, a semiconductor integrated circuit creates logical data of a circuit in a hardware description language, and mathematically determines whether the logical data satisfies a proposition regarding a logical specification given by a user. Formal Logic Verification (Formal Verification) using Model Checking to verify and verify, and inputting test pattern data and confirming that the behavior of the logic under verification is as expected Verification is performed using a logic simulation for making a determination.

In the logic simulation, test pattern data describing an input pattern for testing design data is input, and it is determined whether the operation of the logic to be verified is as expected. This logic simulation can verify a specified input pattern, but requires a great deal of man-hours to create and verify a test pattern for checking all functions to be verified.

[0004] On the other hand, in formal logic verification using model checking to verify, for all possible input patterns of logic data, whether the logic to be verified satisfies the proposition regarding the logic specification given by the user. Can be proved mathematically and its validity can be guaranteed, so that the verification can be completed with less man-hours than the logic simulation. As a formal logic verification method using this model checking, for example, JP-A-9-3259
A method as disclosed in Japanese Patent No. 75 is known. In this verification method, as shown in FIG. 2, using a logical data 10 to be verified and a logical specification 20 serving as a basis of the logical data 10, the user extracts a portion to be verified by model checking. Is converted into check item information 18 in a format that can be input by model checking, and model checking is performed by the model checking means 19 based on the logical data 10 and the check item information 18, and the result is referred to as a model checking result. 1A.

As described above, although the verification by model checking has an advantage over the logic verification by the logic simulation as described above, the verification by both is generally used together. The reason for this is that when verifying a logical operation in a specific input pattern, that is, a logical operation in a so-called corner case, it is better to define the above input pattern using test pattern data for logic simulation and confirm the operation by model checking. It is difficult to display the operation of the logic under test in time-course with model checking because it is easier to verify than when using This is because it is more convenient to use logic simulation.

Therefore, the semiconductor integrated circuit is efficiently and highly accurate by using the formal logic verification using the model checking and the advantages and disadvantages of the logic simulation using the test pattern data and using them together. Logical verification has been performed.

In the course of designing an actual semiconductor integrated circuit, the logic configuration of a circuit to be verified is frequently changed because a logic defect is corrected or a specification is changed. When this logic is changed, it is of course to confirm that the changed part operates as expected. However, functions that have been operating normally and do not depend on this change will operate correctly. It is important to make sure they are not. This is because there is a possibility that the contents of the logical change may break the existing logical operation even though the designer does not intend.

For this reason, in general, when a logical change is made, all or a part of the test pattern data for the logical simulation that has been confirmed in the past to be operating as expected without depending on the logical change. And perform a logic simulation again using the logic after the change, compare it with the results of the logic simulation performed in the past and confirm it.At least the functions confirmed before the logic under verification was changed It is necessary to ensure that no degradation has occurred.

The degrading will be described with reference to FIG. FIG. 3A shows an example of a logical configuration based on logical data before logical change, and FIG. 3B shows an example of a logical configuration based on logical data after logical change.
FIG. 3B shows the logical configuration of the AND circuits 34 and 32 on the input side shown in FIG. 3A and the flip-flop 33 and the AND circuit 30 respectively connected to the output side of the circuit.
It is assumed that the AND circuit 30 is changed to an OR circuit 31 as shown in FIG.

When this change is made, with respect to the circuit portion 33 in which the OR circuit 31 has been changed, whether or not the changed portion operates as expected is checked, and the circuit portion 32 which should not depend on this change is checked. It is also necessary to confirm that no degrading has occurred.

The method of checking whether or not the circuit portion 32 that does not depend on the change has undergone a degrading is a test pattern data for logic simulation that has been confirmed in the past that the logic is operating as expected without depending on the logical change. , Specifically, each input terminal 'INPUT0', 'INPUT1', 'CLK'
Select test pattern data to provide an input pattern for each, perform a logic simulation again using all or a part of the test pattern data, and confirm by comparing with the logic simulation results performed in the past It is done by.

[0012]

The conventional formal logic verification method for verifying using model checking uses a logical specification 20 when creating check item information 18 which is a core in performing the above verification. It is necessary to manually extract the required verification part from, and manually convert the extracted part into a format that can be input by model checking. There is a problem that there is a possibility that an error may occur when creating check item information due to misunderstanding of the above.

Further, since the conventional verification method uses completely independent logic simulation and model checking together, there is no correspondence as to which function of the logic data has been verified by both. When confirming that the logical data has not been degraded, it is necessary to carry out both a reconfirmation of test patterns independent of logical changes and a model simulation that extracts check item information independent of logical changes. Yes,
The items to be verified in the logic simulation and the model checking overlap, and it is said that both verifications in the logic simulation and the model checking should be sufficient for both of them, resulting in unnecessary verification man-hours. There was a defect.

Further, in the conventional verification method, in order to confirm that no degrading has occurred at the time of the logic change, it is necessary to perform a logic simulation on the verified test pattern every time the logic is changed as described above. However, the amount of test patterns to be reconfirmed increases as the verification progresses, and there is a problem that a large number of man-hours and computer resources are required.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the problems caused by the above-mentioned conventional technology, and to reduce conversion errors to check item information, reduce check item information creation errors, and use both logic simulation and model checking. A logic data verification method capable of reducing useless verification man-hours by efficient logic verification, reducing the number of logic simulations at the time of degrade verification to reduce verification man-hours and computer resources, and a program for executing the logic verification method And a logic verification system that executes the logic verification method.

[0016]

In order to achieve the above object, a method for verifying logical data according to the present invention comprises a method for verifying logical data and a test pattern data defining a logical simulation test pattern for testing the logical data. Create waveform data in a time chart format, check the names of the signals to be subjected to model checking, input based on the waveform data, the conditions for defining the signals, and the format that can be input in the model checking from the waveform data. Generating item information, when the logical data is changed, performing model checking using the check item information for a part that is not a logical data change target; Enter the check item information, and enter the waveform data, the input signal name and Of check item information generated from conditions, characterized by adding only the portion that is not included in the check item information previously generated the check item information previously generated.

A logic verification system for verifying according to the present invention provides a logic simulation system for generating waveform data in a time chart format from the logic data and test pattern data defining a test pattern of a logic simulation for testing the logic data. Means, input means for inputting a signal name to be subjected to model checking based on the waveform data and determination conditions of the signal, and a model based on the waveform data, the signal name input by the input means, and the determination conditions. Check item generation means for generating check item information in a format that can be input by checking;
Means for inputting the check item information and performing model checking of logical data, wherein when the logical data is changed, model checking is executed using the check item information for a part which is not a logical data change target. Further, in the logic verification system of the feature, a means for inputting the previously generated check item information is provided to the check item generating means, and the check item generating means is configured to input the check item information based on the waveform data, the signal name specified by the input means, and the fixing condition Check item generation means is provided which adds only a part of the generated check item information that is not included in the previously generated check item information to the previously generated check item information and outputs the result.

Further, a recording medium for storing a program for a method of verifying logical data according to the present invention, comprises:
Create waveform data in the form of a time chart from test pattern data defining the logic data and a test pattern of a logic simulation for testing the logic data, and perform a model checking input based on the waveform data. A check name information in a format that can be input by model checking based on the signal name and the determination condition of the signal and the waveform data, and when the logical data is changed, the check is performed for a part that is not a logical data change target. It is a program for executing model checking using item information.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a logic data verification method according to the present invention, a recording medium storing a program for executing the logic verification method, and a logic verification system for executing the logic verification method. This will be described in detail with reference to FIG.

FIG. 1 is a diagram for explaining an overall schematic configuration of a logic verification system for executing a logic verification method according to the present invention. The logic verification system according to the present embodiment includes a logic data 10 described in a hardware description language such as VHDL or Verilog-HDL before logic change and a hardware description language for verifying the logic data 10 by logic simulation. A logic simulation is performed by inputting the described test pattern data 11 and waveform data 13 in which the operation of the logic data 10 with respect to the test pattern described by the test pattern data 11 is described for each signal with time tracking is output. Logic simulation means 12 for performing
The signal name to be subjected to model checking specified by the user based on the check item information 14 and the newly created check item information 14 and the waveform data 13 which are created at a stage before the logical change is made, and A user designation unit 15 for inputting a signal determination condition;
Model check check item generation means 16 for generating check item information 18 in a format that can be input by model checking based on the signal name designated by the user 3 and the user designation section 15 and the condition for determining the signal;
Logic data 17 to be verified logic changed with respect to
And model checking means 19 for performing model checking of the logical data based on the logical data 17 after the logical change and the check item information 18 and outputting a checking result 1A, wherein the logical data is changed. At this time, model checking is performed using the check item information for a part that is not a logical data change target.

The model checking check item generating means 16 adds the previously generated check item information 14 to the input of the check item generating means 16 to generate the waveform data 13 and the signal specified by the user specifying unit 15. Only the part that is not included in the previously generated check item information among the check item information generated from the name and the confirmation condition is added to the previously generated check item information 14 and the check item information 18 is output.

Next, the processing method of the check item generating means 16 will be described with reference to the drawings. FIG. 4 is a diagram showing a schematic flow chart of the check item generating means 16, and FIG. 5 is a diagram showing data related to the check item generating means 16.

The check item generating means 16 reads the time chart format waveform data 13 output from the logic simulation means 12 (step 4).
0), a GUI (Graphical User Interface) as an input means of a signal name to be subjected to model checking designated by a user based on the waveform data and a condition for defining the signal.
e) to the user designation unit 15 (step 4).
1).

The data provided to the user designating section 15 includes waveform data 13 as shown by reference numeral 15 in FIG.
And a confirmation condition button C for notifying the user designation section 15 that the user designates the confirmation condition.
0, 'AND [logical product]' or 'OR
Buttons for specifying [OR] ',' ([parentheses] ',') [same as left] ', C2, C7, C10, C11, and fixed value button C4 for specifying a signal to be a fixed value Is done.

The user who sees this display designates the signal name and condition as the decision condition, the signal name as the decision value, and the like on the screen of the user designation section 15 by clicking the mouse or the like (step 42). . In the example of FIG. 5, when the signal A and the signal B are High at the rising edge of CLK [determination condition], the signal C always becomes High after one cycle [Determining value], and the signal A at the rising edge of CLK. Alternatively, it is assumed that when the signal B is Low [determination condition], the signal C always becomes Low after one cycle [determination value]. Waveforms satisfying both of these specifications are displayed on the user designation section 15 (51 and 52 in the waveform data display 13).

When these logical specifications are specified by the user specifying section 15, for example, when the logical specification (reference numeral 51 in FIG. 5) at which the signal C becomes High is specified, the confirmation condition button C
0, click the position C1 of the signal A that is the final condition, click the AND button C2, click the position C3 of the signal B that is the final condition, and click the final value button C4.
Is clicked, and the position C5 of the signal C serving as the final value is clicked. Similarly, the logic specification that the signal C becomes Low (FIG. 5)
When the reference numeral 52) is designated, the confirmation condition button C0
Is clicked, the position C6 of the signal A serving as the final condition is clicked, the OR button C7 is clicked, the position C8 of the signal B serving as the final condition is clicked, and the final value button C4 is clicked, and the signal serving as the final value is clicked. This is performed by clicking the position C9 of C.

Next, the check item generating means 16 generates check item information 53 specified by the user based on the information specified by the user in step 42 (step 4).
3). This check item information 53 is indicated by reference numeral 53 in FIG.
As shown in FIG. 7, two items 54 and 55 are defined, and each item is divided into a part for defining a fixed condition and a part for defining a fixed value. That is, the item 54 includes a decision condition 541 in which "always" means "always when an expression enclosed by the following '(', ')'" is satisfied, and an "implies" indicates that the "determination condition is satisfied." Then, a definite value 544 indicating that the expression enclosed by the following '(', ')' is satisfied ", and in this example," the signal A becomes a logical value 1 and the signal B becomes If the logical value is 1 [always ((A = '1') && (B =
'1'))], the logic value of the signal C is always 1 after one cycle.
[Implies (C = '1' at t + 1)] "("
at t + 1 "represents one cycle after the determination condition is satisfied. The same applies to item 55, and this example is described in the case of" Signal A
Has a logical value 0 or the signal B has a logical value of 0 [always ((A = '0') ‖ (B = '0'))], the logical value of the signal C always becomes 0 after one cycle. [Implies (C = '
0 'at t + 1)] ".

The check item information 53 specified by the user, the previously generated check item information 14 and the check item information 18 are all described in the language of the same specification. For example, the generation of the check item information 53 will be specifically described. When the signal C in the waveform data 13 in FIG.
When an item 541 serving as a determination condition is generated for the logic specification (reference numeral 51) that becomes high, the determination is made based on whether the determination condition button C0 is clicked, and the signal name and the signal value are determined. The item 542 is determined based on the click positions of C1 and C3 specified by the user on the time chart, and the condition item 543 is AND or OR.
Judgment is made with the button, and the information is generated based on the information.

In the case of generating the item 544 to be the final value, the final value is determined by whether or not the final value button C4 is clicked, and is determined by the signal name and the time until the final signal value is determined. The item 545 is determined based on the click position of C5 specified by the user on the time chart.
Similarly, the logic specification (reference numeral 52) in which the signal C becomes Low is determined for each item from the click position and the like, and is generated based on the information in accordance with the description format of the check item information.

Next, the check item generation means 16 determines whether the
It is determined whether the user has input / designated the previously generated check item information 14 based on a command option or the like at the time of execution of the process (step 44). The process is performed, and if the input has not been designated, the check item information 53 specified by the user generated in step 43 is output as the check item information 18 as it is, and the process ends (step 49).

When the input is designated in step 45, the previously generated check item information 14 is inputted (step 46), and in the check item information 53 specified by the user generated in step 43, the previously generated check item information 53 is selected. Check item information not included in the information 14 is extracted as difference information 56 (step 47).

In the example shown in FIG. 5, among the check item information 53 specified by the user, the item 54 has the same content defined in the item 50 defined on the check item information 14 generated last time. On the other hand, since the item 55 does not match any item defined in the item 50, the difference information 56 is the item 55.

Next, the check item generation means 16 checks the check item information 5 of the difference information 56 extracted in step 47.
5 is added to the check item information 50 of the previously generated check item information 14 input in step 46 (step 4
8) Then, the added check item information 18 is generated and output (step 49), and the processing ends. The above is the flow of the check item generation processing by the check item generation unit 16.

Next, the process of verifying the changed logical data in the logical verification system that executes the above-described logical verification method will be described with reference to the flowchart of FIG. First, in the present process, when the logical data 10 is changed (step 601) and the logically changed logical data 17 is created,
Test pattern data 11 is created (step 602) to verify that the logic-changed part operates as expected using the logic simulation means 12 (step 602), and a logic simulation is performed using the test pattern data 11 (step 60).
3) Then, the verifier checks the logic simulation means 12
It is determined whether the logic is operating as expected with reference to the waveform data 13 (FIG. 5) which is the output of FIG. 1 (step 604).

If the logic is operating as expected in step 604, the check item information 18 and the check item generating means 16 are used to generate the check item information 18 for the degrading verification at the next logical change. (Step 608) and the process ends.

If the logic does not operate as expected in the step 604, the logic data is changed (step 605), and the model checking means 19 (FIG. 1) checks the logic generated before the current logic change. Item information 1
(Step 60)
6). If there is no check item information 14 generated before the logic change in step 605, the logic simulation using the existing test pattern data as in the related art is performed, or the waveform when the logic simulation is executed before the current logic change is performed. Check item information 14 is generated from the data 13.

Next, in the present process, it is determined whether or not there is an error due to occurrence of degrading in the model checking result in the step 605 (step 607). If there is an error, the process returns to the step 605 to correct the logic again and there is no error. In this case, the process returns to step 603 to perform the logic simulation again, and the process proceeds to step 604 until it is determined in step 604 that the logic operates as expected.
Step 604 is performed to repeat the processing of Steps 607 to 607.
When it is determined that the logic is operating as expected in the above, the check item information 18 and the check item generating means 16 existing for degrading verification at the next logical change are used to check the check item information 18 in the same manner as described above. Generation (step 608) ends the processing. The details are as described with reference to FIGS.

As described above, according to the logic data verification method and the logic verification system for executing the verification method according to the present embodiment, it becomes unnecessary to repeatedly execute a logic simulation for a huge test pattern for degrade verification. It has the effect of saying

FIG. 7 is a diagram showing an example of a hardware configuration for executing the logic data verification method according to the present invention in a general computer system. The system configuration according to the present embodiment includes a computer body including a CPU 72, a memory 76, a hard disk 77, and a recording medium writing unit 73, a display unit 71 such as a CRT connected to the computer, an input unit 75, and the recording medium writing unit 7.
3, a recording medium 70 such as a floppy disk / magneto-optical recording disk, a printer for outputting an output result 74, etc. (not shown). A program for executing the described logical data verification method and necessary data are stored.

In the computer system according to the present embodiment, the CPU 72 reads out a program for executing the method of verifying the logical data recorded on the hard disk 77 and reads out the logical data and the test pattern and other data from the memory 76.
The processing result is expanded and executed on the basis of the logic verification method described in the above-described embodiment. It operates to output the result 74.

In the present embodiment, an example has been described in which a program for executing a method of verifying logical data and data are stored in the hard disk 77. However, the present invention is not limited to this, and the storage medium 70 stores the program and data. And the data may be stored, and the stored logic verification method may be read by the storage medium reading means 73 to execute the above-described processing. The storage medium in this case may be a dynamic storage means of a floppy disk / magneto-optical recording disk / optical disk, or a static storage means such as a flash memory for storing data in a semiconductor.

As described above, according to the present invention, waveform data in a time chart format is created based on logic data of a semiconductor integrated circuit created in a hardware description language and test pattern data describing a test pattern for logic simulation. Logic simulation means, input means for a user to specify a signal name to be subjected to model checking based on the waveform data and conditions for defining the signal, and a signal designated by the waveform data and the input means A check item generation unit for generating check item information in a format that can be input by model checking based on a name and a determination condition; a unit for inputting the check item information and performing model checking of logical data; Means for inputting check item information generated last time is provided in the generating means, Of the check item information generated from the waveform data, the signal name specified by the input means, and the confirmation condition, only a portion not included in the previously generated check item information is added to the previously generated check item information and output. Based on the waveform data of the test pattern verified by the logic simulation, check item information is generated simply by the user specifying the name of the signal to be subjected to model checking by the input means and the conditions for determining the signal. can do.

According to the present invention, conversion errors to check item information can be reduced, and check item information is generated based on waveform data confirmed by logic simulation. Creation errors can be reduced, and the accuracy of creating check item information can be improved. In addition, since both the logic simulation and the model checking correspond to which function has been verified, efficient logic verification using both functions can be performed. As a result, when verifying whether or not a function that does not depend on this change is degraded when the logic is changed, the waveform data of the test data for realizing this function, which was verified by a logic simulation before the logic change, is verified. The verification can be performed by generating check item information based on the information and executing model checking using the generated information to confirm that no error is indicated.

Conventionally, it has been necessary to perform logic simulation on a large number of test patterns for verification for degrade verification, but by performing degrade verification mainly on model checking, it is possible to check from waveform data of these test patterns. By generating and storing the item information, the degrade verification can be performed only by performing the model checking once using the stored check item information.

As a result, the number of logic simulations at the time of degrade verification can be reduced, and verification man-hours and computer resources can be reduced.

Note that the present invention can be represented as the following embodiments.

Embodiment 1 In a formal logic verification method for verifying logic data of a semiconductor integrated circuit created in a hardware description language using model checking,
Logic simulation means for creating waveform data in the form of a time chart from the logic data and test pattern data defining a logic simulation test pattern for testing the logic data; and a model checking object based on the waveform data. Input means for the user to specify a signal name to be and a decision condition of the signal,
Check item generation means for generating check item information in a format that can be input by model checking based on the waveform data, the signal name specified by the input means, and the confirmation condition, and inputting the check item information, Model checking is provided, and when the logical data is changed, by performing model checking using the check item information for a part that is not subject to logical data change, it is confirmed that there is no degrading of the part. Logic verification method characterized by performing.

<Embodiment 2> A means for inputting the previously generated check item information is provided in the check item generating means, and the check item information generated from the waveform data, the signal name designated by the input means and the confirmation condition is provided. home,
The logic verification method according to the first embodiment, further comprising: a check item generation unit that adds only a portion not included in the previously generated check item information to the previously generated check item information and outputs the result.

Embodiment 3 In a formal logic verification method for verifying logic data of a semiconductor integrated circuit created in a hardware description language using model checking,
Logic simulation means for creating waveform data in the form of a time chart from the logic data and test pattern data defining a logic simulation test pattern for testing the logic data; and a model checking object based on the waveform data. Input means for the user to specify a signal name to be and a decision condition of the signal,
Check item generation means for generating check item information in a format that can be input by model checking based on the waveform data, the signal name specified by the input means, and the confirmation condition, and inputting the check item information, Model checking is provided, and when the logical data is changed, by performing model checking using the check item information for a part that is not subject to logical data change, it is confirmed that there is no degrading of the part. A medium storing a program for realizing a logic verification method characterized by performing the following.

<Embodiment 4> A means for inputting previously generated check item information is provided in the check item generating means, and the check item information generated from the waveform data, the signal name designated by the input means and the confirmation condition is provided. home,
A program for realizing the logic verification method according to the first embodiment, further comprising a check item generation unit that adds only a portion not included in the previously generated check item information to the previously generated check item information and outputs the result. Medium on which is recorded.

[0051]

According to the present invention, the check item information can be generated from the waveform data of the test pattern once verified by the logic simulation, so that the accuracy of creating the check item information can be improved.

When confirming that the logical data has not been degraded at the time of the logical change, a function that does not depend on the logical change was confirmed by a logical simulation before the logical change, and a test pattern for realizing this function was checked. By generating check item information based on waveform data and performing model checking based on the check item information, it is possible to verify that the logical data has not been degraded. It is not necessary to execute a logic simulation every time the logic is changed, and the efficiency of the verification operation can be increased.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining an embodiment of the overall schematic configuration of a logic verification system that executes a logic verification method according to the present invention.

FIG. 2 is a diagram for explaining a processing configuration of formal logic verification that performs verification using conventional model checking.

FIG. 3 is a logical diagram showing logical data before and after a change according to the embodiment;

FIG. 4 is a schematic flowchart of a check item generation unit according to the embodiment;

FIG. 5 is a view showing data related to a check item generation unit according to the embodiment.

FIG. 6 is a diagram showing a logic verification flow using the present invention according to the present embodiment.

FIG. 7 is a hardware configuration diagram of a formal logic verification method for verifying using model checking according to the embodiment;

[Explanation of symbols]

10: logical data, 11: test pattern data, 12
... Logic simulation means, 13 ... Waveform data, 14
... Check item information generated last time, 15... User designation section, 16... Check item generating means, 17... Logical data after logic change, 18. …
Logical specifications, 70: storage medium, 71: display means, 72 ...
CPU, 73: storage medium reading means, 74: output result, 75: input means, 76: memory, 77: hard disk.

Claims (5)

[Claims] 1. A method for verifying logical data of a semiconductor integrated circuit created in a hardware description language by model checking, the method comprising the steps of: executing the logical data and a logical simulation for testing the logical data. A waveform data in a time chart format is created from test pattern data defining a test pattern, and a signal name to be subjected to model checking input based on the waveform data, a condition for determining the signal, and the waveform data are used. Check item information in a format that can be input by model checking is generated, and when the logical data is changed, model checking is performed using the check item information for a part that is not a logical data change target. Validation method for logical data. 2. Check item information generated last time is input, and of the check item information generated based on the waveform data and the input signal name and confirmation condition, only a part that is not included in the previously generated check item information is deleted. 2. The method according to claim 1, wherein the information is added to the generated check item information.
Verification method of the described logical data. 3. A logic verification system for verifying logic data of a semiconductor integrated circuit created in a hardware description language by model checking, wherein said logic data and a test pattern of a logic simulation for testing said logic data are defined. Logic simulation means for creating waveform data in a time chart format based on the obtained test pattern data; input means for inputting a signal name to be subjected to model checking based on the waveform data and a condition for determining the signal; Check item generating means for generating check item information in a format that can be input by model checking based on data, a signal name input by the input means, and a determination condition; and inputting the check item information and performing a model check of logical data. Means for performing a king. When over data is changed, the logic verification system, characterized by performing model checking using the check item information for the portion outside the logical data changed. 4. A means for inputting previously generated check item information to the check item generating means, wherein the check item information generated from the waveform data, the signal name specified by the input means and the confirmation condition is selected from the last. 4. The logic verification system according to claim 3, further comprising a check item generation unit that adds only a portion not included in the generated check item information to the previously generated check item information and outputs the result. 5. A storage medium for storing a program for a method of verifying logical data for verifying, by model checking, logical data of a semiconductor integrated circuit created in a hardware description language, wherein the program for the method of verifying logical data is stored. Creates waveform data in the form of a time chart from test pattern data defining the logic data and a test pattern of a logic simulation for testing the logic data, and performs model checking based on the waveform data. Generates check item information in a format that can be input by model checking based on the name of the target signal and the decision condition of the signal, and the waveform data, and when the logical data is changed, a part outside the logical data change target is generated. A program for executing model checking using the check item information Recording medium, which is a beam.